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Searched refs:CLK_PCLK_SYSREG_BUS (Results 1 – 2 of 2) sorted by relevance

/linux-6.1.9/include/dt-bindings/clock/
Dexynos5433.h837 #define CLK_PCLK_SYSREG_BUS 7 macro
/linux-6.1.9/drivers/clk/samsung/
Dclk-exynos5433.c3123 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus0", "div_pclk_bus0_133",
3148 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus1", "div_pclk_bus1_133",
3183 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus2", "div_pclk_bus2_133",