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Searched refs:CLK_PCLK_DDR_PHY0 (Results 1 – 2 of 2) sorted by relevance

/linux-6.1.9/include/dt-bindings/clock/
Dexynos5433.h376 #define CLK_PCLK_DDR_PHY0 179 macro
/linux-6.1.9/drivers/clk/samsung/
Dclk-exynos5433.c1468 GATE(CLK_PCLK_DDR_PHY0, "pclk_ddr_phy0", "div_aclk_mif_133",