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Searched refs:CLK_GSCL_WB (Results 1 – 4 of 4) sorted by relevance

/linux-6.1.9/include/dt-bindings/clock/
Dexynos5250.h65 #define CLK_GSCL_WB 261 macro
Dexynos5420.h163 #define CLK_GSCL_WB 464 macro
/linux-6.1.9/drivers/clk/samsung/
Dclk-exynos5250.c526 GATE(CLK_GSCL_WB, "gscl_wb", "div_gscl_wb", GATE_IP_GSCL, 6, 0, 0),
Dclk-exynos5420.c1167 GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13,