| /linux-6.1.9/drivers/clk/hisilicon/ |
| D | clk-hi3660.c | 336 CLK_SET_RATE_PARENT, 0xb0, 4, 4, CLK_DIVIDER_HIWORD_MASK, },
338 CLK_SET_RATE_PARENT, 0xb0, 8, 4, CLK_DIVIDER_HIWORD_MASK, },
340 CLK_SET_RATE_PARENT, 0xb0, 12, 4, CLK_DIVIDER_HIWORD_MASK, },
342 CLK_SET_RATE_PARENT, 0xb4, 3, 4, CLK_DIVIDER_HIWORD_MASK, },
344 CLK_SET_RATE_PARENT, 0xb8, 0, 4, CLK_DIVIDER_HIWORD_MASK, },
346 CLK_SET_RATE_PARENT, 0xbc, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
348 CLK_SET_RATE_PARENT, 0xbc, 10, 6, CLK_DIVIDER_HIWORD_MASK, },
350 CLK_SET_RATE_PARENT, 0xc0, 0, 4, CLK_DIVIDER_HIWORD_MASK, },
352 CLK_SET_RATE_PARENT, 0xc0, 8, 6, CLK_DIVIDER_HIWORD_MASK, },
354 CLK_SET_RATE_PARENT, 0xc4, 12, 4, CLK_DIVIDER_HIWORD_MASK, },
[all …]
|
| D | clk-hi3670.c | 488 CLK_SET_RATE_PARENT, 0xEC, 0, 2, CLK_DIVIDER_HIWORD_MASK, },
490 CLK_SET_RATE_PARENT, 0x0EC, 2, 1, CLK_DIVIDER_HIWORD_MASK, },
492 CLK_SET_RATE_PARENT, 0x0EC, 3, 1, CLK_DIVIDER_HIWORD_MASK, },
494 CLK_SET_RATE_PARENT, 0xb4, 6, 4, CLK_DIVIDER_HIWORD_MASK, },
496 CLK_SET_RATE_PARENT, 0x0BC, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
498 CLK_SET_RATE_PARENT, 0xB8, 0, 4, CLK_DIVIDER_HIWORD_MASK, },
500 CLK_SET_RATE_PARENT, 0xC0, 0, 4, CLK_DIVIDER_HIWORD_MASK, },
502 CLK_SET_RATE_PARENT, 0xB0, 12, 4, CLK_DIVIDER_HIWORD_MASK, },
504 CLK_SET_RATE_PARENT, 0xB0, 8, 4, CLK_DIVIDER_HIWORD_MASK, },
506 CLK_SET_RATE_PARENT, 0xB0, 4, 4, CLK_DIVIDER_HIWORD_MASK, },
[all …]
|
| D | clk-hi3620.c | 124 { HI3620_SHAREAXI_DIV, "saxi_div", "saxi_mux", 0, 0x100, 0, 5, CLK_DIVIDER_HIWORD_MASK, NULL, },
125 { HI3620_CFGAXI_DIV, "cfgaxi_div", "saxi_div", 0, 0x100, 5, 2, CLK_DIVIDER_HIWORD_MASK, NULL, },
126 { HI3620_SD_DIV, "sd_div", "sd_mux", 0, 0x108, 0, 4, CLK_DIVIDER_HIWORD_MASK, NULL, },
127 { HI3620_MMC1_DIV, "mmc1_div", "mmc1_mux", 0, 0x108, 5, 4, CLK_DIVIDER_HIWORD_MASK, NULL, },
128 { HI3620_HSIC_DIV, "hsic_div", "rclk_hsic", 0, 0x130, 0, 2, CLK_DIVIDER_HIWORD_MASK, NULL, },
129 { HI3620_MMC2_DIV, "mmc2_div", "mmc2_mux", 0, 0x140, 0, 4, CLK_DIVIDER_HIWORD_MASK, NULL, },
130 { HI3620_MMC3_DIV, "mmc3_div", "mmc3_mux", 0, 0x140, 5, 4, CLK_DIVIDER_HIWORD_MASK, NULL, },
|
| /linux-6.1.9/drivers/clk/rockchip/ |
| D | clk-half-divider.c | 125 if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { in clk_half_divider_set_rate()
|
| D | clk-rk3036.c | 146 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
|
| D | clk-rk3128.c | 170 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
|
| D | clk-rk3228.c | 180 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
|
| D | clk-rk3188.c | 238 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
|
| D | clk-rk3328.c | 233 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
|
| D | clk-rv1108.c | 163 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
|
| D | clk-rk3368.c | 152 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
|
| D | clk-rk3288.c | 246 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
|
| D | clk-px30.c | 205 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
|
| D | clk-rk3308.c | 195 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
|
| D | clk-rv1126.c | 211 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
|
| D | clk-rk3399.c | 241 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
|
| D | clk-rk3568.c | 342 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
|
| /linux-6.1.9/drivers/clk/renesas/ |
| D | rzg2l-cpg.h | 142 .flag = CLK_DIVIDER_HIWORD_MASK)
|
| /linux-6.1.9/drivers/clk/ |
| D | clk-divider.c | 505 if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { in clk_divider_set_rate()
549 if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) { in __clk_hw_register_divider()
|
| /linux-6.1.9/drivers/clk/zynqmp/ |
| D | divider.c | 307 ccf_flag |= CLK_DIVIDER_HIWORD_MASK; in zynqmp_clk_map_divider_ccf_flags()
|
| /linux-6.1.9/drivers/clk/stm32/ |
| D | clk-stm32-core.c | 242 if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { in stm32_divider_set_rate()
|
| /linux-6.1.9/include/linux/ |
| D | clk-provider.h | 674 #define CLK_DIVIDER_HIWORD_MASK BIT(3) macro
|