| /linux-6.1.9/drivers/clk/ralink/ |
| D | clk-mt7621.c | 289 #define CLK_BASE(_name, _parent, _recalc) { \ macro
304 { CLK_BASE("xtal", NULL, mt7621_xtal_recalc_rate) },
305 { CLK_BASE("cpu", "xtal", mt7621_cpu_recalc_rate) },
306 { CLK_BASE("bus", "cpu", mt7621_bus_recalc_rate) },
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
| D | rv1_clk_mgr_clk.c | 44 CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| D | clk_mgr_internal.h | 81 #define CLK_BASE(inst) \ macro
85 .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
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| /linux-6.1.9/drivers/gpu/drm/amd/amdgpu/ |
| D | vega10_reg_init.c | 53 adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i])); in vega10_reg_base_init()
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| D | vega20_reg_init.c | 51 adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i])); in vega20_reg_base_init()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| D | dcn316_clk_mgr.c | 58 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } }, variable
77 (CLK_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
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| /linux-6.1.9/drivers/gpu/drm/amd/include/ |
| D | cyan_skillfish_ip_offset.h | 45 static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0, 0, 0, 0 } }, variable
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| D | navi10_ip_offset.h | 43 static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x00016E00, 0x00017000, 0x0001… variable
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| D | dimgrey_cavefish_ip_offset.h | 46 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } }, variable
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| D | navi12_ip_offset.h | 46 static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x02401800, 0, 0, 0 } }, variable
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| D | navi14_ip_offset.h | 46 static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x02401800, 0, 0, 0 } }, variable
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| D | vega20_ip_offset.h | 45 static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x00016E00, 0x00017000, 0x0001… variable
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| D | sienna_cichlid_ip_offset.h | 46 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0 } }, variable
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| D | beige_goby_ip_offset.h | 47 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } }, variable
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| D | renoir_ip_offset.h | 53 static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x00016E00, 0x00017000, 0x00017E00, 0 } }, variable
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| D | vega10_ip_offset.h | 203 static const struct IP_BASE __maybe_unused CLK_BASE = { { { { 0x00016C00, 0, 0, 0, 0 } }, variable
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| D | vangogh_ip_offset.h | 58 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } }, variable
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| D | yellow_carp_offset.h | 34 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } }, variable
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| D | arct_ip_offset.h | 47 static const struct IP_BASE CLK_BASE ={ { { { 0x000120C0, 0x00016C00, 0x00401800, 0, 0, … variable
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| D | aldebaran_ip_offset.h | 42 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } }, variable
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| D | dcn314_clk_mgr.c | 72 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0, 0, 0 } }, variable
91 (CLK_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn301/ |
| D | dcn301_resource.c | 183 #define CLK_BASE(seg) \ macro
187 .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| D | vg_clk_mgr.c | 59 (CLK_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| D | rn_clk_mgr.c | 51 (CLK_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| D | dcn31_clk_mgr.c | 69 (CLK_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
|