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Searched refs:CLKID_VCLK_DIV4 (Results 1 – 8 of 8) sorted by relevance

/linux-6.1.9/include/dt-bindings/clock/
Daxg-clkc.h89 #define CLKID_VCLK_DIV4 124 macro
Dgxbb-clkc.h136 #define CLKID_VCLK_DIV4 187 macro
Dg12a-clkc.h115 #define CLKID_VCLK_DIV4 150 macro
/linux-6.1.9/drivers/clk/meson/
Dmeson8b.h130 #define CLKID_VCLK_DIV4 144 macro
Dmeson8b.c2918 [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
3126 [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
3345 [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
Dgxbb.c2913 [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw,
3124 [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw,
Dg12a.c4400 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
4629 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
4893 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
Daxg.c2018 [CLKID_VCLK_DIV4] = &axg_vclk_div4.hw,