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Searched refs:CLKID_VCLK_DIV1 (Results 1 – 8 of 8) sorted by relevance

/linux-6.1.9/include/dt-bindings/clock/
Daxg-clkc.h87 #define CLKID_VCLK_DIV1 122 macro
Dgxbb-clkc.h134 #define CLKID_VCLK_DIV1 185 macro
Dg12a-clkc.h113 #define CLKID_VCLK_DIV1 148 macro
/linux-6.1.9/drivers/clk/meson/
Dmeson8b.h126 #define CLKID_VCLK_DIV1 140 macro
Dmeson8b.c2914 [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
3122 [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
3341 [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
Dgxbb.c2909 [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw,
3120 [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw,
Dg12a.c4389 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
4618 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
4882 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
Daxg.c2016 [CLKID_VCLK_DIV1] = &axg_vclk_div1.hw,