1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #ifndef _smuio_13_0_2_SH_MASK_HEADER 25 #define _smuio_13_0_2_SH_MASK_HEADER 26 27 28 // addressBlock: smuio_smuio_SmuSmuioDec 29 //SMUSVI0_TEL_PLANE0 30 #define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_IDDCOR__SHIFT 0x0 31 #define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT 0x10 32 #define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_IDDCOR_MASK 0x000000FFL 33 #define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK 0x01FF0000L 34 //SMUSVI0_PLANE0_CURRENTVID 35 #define SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID__SHIFT 0x18 36 #define SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID_MASK 0xFF000000L 37 //SMUIO_MCM_CONFIG 38 #define SMUIO_MCM_CONFIG__DIE_ID__SHIFT 0x0 39 #define SMUIO_MCM_CONFIG__PKG_TYPE__SHIFT 0x1 40 #define SMUIO_MCM_CONFIG__SOCKET_ID__SHIFT 0x4 41 #define SMUIO_MCM_CONFIG__PKG_SUBTYPE__SHIFT 0x8 42 #define SMUIO_MCM_CONFIG__TOPOLOGY_ID__SHIFT 0xa 43 #define SMUIO_MCM_CONFIG__DIE_ID_MASK 0x00000001L 44 #define SMUIO_MCM_CONFIG__PKG_TYPE_MASK 0x0000000EL 45 #define SMUIO_MCM_CONFIG__SOCKET_ID_MASK 0x000000F0L 46 #define SMUIO_MCM_CONFIG__PKG_SUBTYPE_MASK 0x00000300L 47 #define SMUIO_MCM_CONFIG__TOPOLOGY_ID_MASK 0x00007C00L 48 //CKSVII2C_IC_CON 49 #define CKSVII2C_IC_CON__IC_MASTER_MODE__SHIFT 0x0 50 #define CKSVII2C_IC_CON__IC_MAX_SPEED_MODE__SHIFT 0x1 51 #define CKSVII2C_IC_CON__IC_10BITADDR_SLAVE__SHIFT 0x3 52 #define CKSVII2C_IC_CON__IC_10BITADDR_MASTER__SHIFT 0x4 53 #define CKSVII2C_IC_CON__IC_RESTART_EN__SHIFT 0x5 54 #define CKSVII2C_IC_CON__IC_SLAVE_DISABLE__SHIFT 0x6 55 #define CKSVII2C_IC_CON__STOP_DET_IFADDRESSED__SHIFT 0x7 56 #define CKSVII2C_IC_CON__TX_EMPTY_CTRL__SHIFT 0x8 57 #define CKSVII2C_IC_CON__RX_FIFO_FULL_HLD_CTRL__SHIFT 0x9 58 #define CKSVII2C_IC_CON__IC_MASTER_MODE_MASK 0x00000001L 59 #define CKSVII2C_IC_CON__IC_MAX_SPEED_MODE_MASK 0x00000006L 60 #define CKSVII2C_IC_CON__IC_10BITADDR_SLAVE_MASK 0x00000008L 61 #define CKSVII2C_IC_CON__IC_10BITADDR_MASTER_MASK 0x00000010L 62 #define CKSVII2C_IC_CON__IC_RESTART_EN_MASK 0x00000020L 63 #define CKSVII2C_IC_CON__IC_SLAVE_DISABLE_MASK 0x00000040L 64 #define CKSVII2C_IC_CON__STOP_DET_IFADDRESSED_MASK 0x00000080L 65 #define CKSVII2C_IC_CON__TX_EMPTY_CTRL_MASK 0x00000100L 66 #define CKSVII2C_IC_CON__RX_FIFO_FULL_HLD_CTRL_MASK 0x00000200L 67 //CKSVII2C_IC_TAR 68 #define CKSVII2C_IC_TAR__IC_TAR__SHIFT 0x0 69 #define CKSVII2C_IC_TAR__GC_OR_START__SHIFT 0xa 70 #define CKSVII2C_IC_TAR__SPECIAL__SHIFT 0xb 71 #define CKSVII2C_IC_TAR__IC_10BITADDR_MASTER__SHIFT 0xc 72 #define CKSVII2C_IC_TAR__IC_TAR_MASK 0x000003FFL 73 #define CKSVII2C_IC_TAR__GC_OR_START_MASK 0x00000400L 74 #define CKSVII2C_IC_TAR__SPECIAL_MASK 0x00000800L 75 #define CKSVII2C_IC_TAR__IC_10BITADDR_MASTER_MASK 0x00001000L 76 //CKSVII2C_IC_SAR 77 #define CKSVII2C_IC_SAR__IC_SAR__SHIFT 0x0 78 #define CKSVII2C_IC_SAR__IC_SAR_MASK 0x000003FFL 79 //CKSVII2C_IC_HS_MADDR 80 #define CKSVII2C_IC_HS_MADDR__IC_HS_MADDR__SHIFT 0x0 81 #define CKSVII2C_IC_HS_MADDR__IC_HS_MADDR_MASK 0x00000007L 82 //CKSVII2C_IC_DATA_CMD 83 #define CKSVII2C_IC_DATA_CMD__DAT__SHIFT 0x0 84 #define CKSVII2C_IC_DATA_CMD__CMD__SHIFT 0x8 85 #define CKSVII2C_IC_DATA_CMD__STOP__SHIFT 0x9 86 #define CKSVII2C_IC_DATA_CMD__RESTART__SHIFT 0xa 87 #define CKSVII2C_IC_DATA_CMD__DAT_MASK 0x000000FFL 88 #define CKSVII2C_IC_DATA_CMD__CMD_MASK 0x00000100L 89 #define CKSVII2C_IC_DATA_CMD__STOP_MASK 0x00000200L 90 #define CKSVII2C_IC_DATA_CMD__RESTART_MASK 0x00000400L 91 //CKSVII2C_IC_SS_SCL_HCNT 92 #define CKSVII2C_IC_SS_SCL_HCNT__IC_SS_SCL_HCNT__SHIFT 0x0 93 #define CKSVII2C_IC_SS_SCL_HCNT__IC_SS_SCL_HCNT_MASK 0x0000FFFFL 94 //CKSVII2C_IC_SS_SCL_LCNT 95 #define CKSVII2C_IC_SS_SCL_LCNT__IC_SS_SCL_LCNT__SHIFT 0x0 96 #define CKSVII2C_IC_SS_SCL_LCNT__IC_SS_SCL_LCNT_MASK 0x0000FFFFL 97 //CKSVII2C_IC_FS_SCL_HCNT 98 #define CKSVII2C_IC_FS_SCL_HCNT__IC_FS_SCL_HCNT__SHIFT 0x0 99 #define CKSVII2C_IC_FS_SCL_HCNT__IC_FS_SCL_HCNT_MASK 0x0000FFFFL 100 //CKSVII2C_IC_FS_SCL_LCNT 101 #define CKSVII2C_IC_FS_SCL_LCNT__IC_FS_SCL_LCNT__SHIFT 0x0 102 #define CKSVII2C_IC_FS_SCL_LCNT__IC_FS_SCL_LCNT_MASK 0x0000FFFFL 103 //CKSVII2C_IC_HS_SCL_HCNT 104 #define CKSVII2C_IC_HS_SCL_HCNT__IC_HS_SCL_HCNT__SHIFT 0x0 105 #define CKSVII2C_IC_HS_SCL_HCNT__IC_HS_SCL_HCNT_MASK 0x0000FFFFL 106 //CKSVII2C_IC_HS_SCL_LCNT 107 #define CKSVII2C_IC_HS_SCL_LCNT__IC_HS_SCL_LCNT__SHIFT 0x0 108 #define CKSVII2C_IC_HS_SCL_LCNT__IC_HS_SCL_LCNT_MASK 0x0000FFFFL 109 //CKSVII2C_IC_INTR_STAT 110 #define CKSVII2C_IC_INTR_STAT__R_RX_UNDER__SHIFT 0x0 111 #define CKSVII2C_IC_INTR_STAT__R_RX_OVER__SHIFT 0x1 112 #define CKSVII2C_IC_INTR_STAT__R_RX_FULL__SHIFT 0x2 113 #define CKSVII2C_IC_INTR_STAT__R_TX_OVER__SHIFT 0x3 114 #define CKSVII2C_IC_INTR_STAT__R_TX_EMPTY__SHIFT 0x4 115 #define CKSVII2C_IC_INTR_STAT__R_RD_REQ__SHIFT 0x5 116 #define CKSVII2C_IC_INTR_STAT__R_TX_ABRT__SHIFT 0x6 117 #define CKSVII2C_IC_INTR_STAT__R_RX_DONE__SHIFT 0x7 118 #define CKSVII2C_IC_INTR_STAT__R_ACTIVITY__SHIFT 0x8 119 #define CKSVII2C_IC_INTR_STAT__R_STOP_DET__SHIFT 0x9 120 #define CKSVII2C_IC_INTR_STAT__R_START_DET__SHIFT 0xa 121 #define CKSVII2C_IC_INTR_STAT__R_GEN_CALL__SHIFT 0xb 122 #define CKSVII2C_IC_INTR_STAT__R_RESTART_DET__SHIFT 0xc 123 #define CKSVII2C_IC_INTR_STAT__R_MST_ON_HOLD__SHIFT 0xd 124 #define CKSVII2C_IC_INTR_STAT__R_RX_UNDER_MASK 0x00000001L 125 #define CKSVII2C_IC_INTR_STAT__R_RX_OVER_MASK 0x00000002L 126 #define CKSVII2C_IC_INTR_STAT__R_RX_FULL_MASK 0x00000004L 127 #define CKSVII2C_IC_INTR_STAT__R_TX_OVER_MASK 0x00000008L 128 #define CKSVII2C_IC_INTR_STAT__R_TX_EMPTY_MASK 0x00000010L 129 #define CKSVII2C_IC_INTR_STAT__R_RD_REQ_MASK 0x00000020L 130 #define CKSVII2C_IC_INTR_STAT__R_TX_ABRT_MASK 0x00000040L 131 #define CKSVII2C_IC_INTR_STAT__R_RX_DONE_MASK 0x00000080L 132 #define CKSVII2C_IC_INTR_STAT__R_ACTIVITY_MASK 0x00000100L 133 #define CKSVII2C_IC_INTR_STAT__R_STOP_DET_MASK 0x00000200L 134 #define CKSVII2C_IC_INTR_STAT__R_START_DET_MASK 0x00000400L 135 #define CKSVII2C_IC_INTR_STAT__R_GEN_CALL_MASK 0x00000800L 136 #define CKSVII2C_IC_INTR_STAT__R_RESTART_DET_MASK 0x00001000L 137 #define CKSVII2C_IC_INTR_STAT__R_MST_ON_HOLD_MASK 0x00002000L 138 //CKSVII2C_IC_INTR_MASK 139 #define CKSVII2C_IC_INTR_MASK__M_RX_UNDER__SHIFT 0x0 140 #define CKSVII2C_IC_INTR_MASK__M_RX_OVER__SHIFT 0x1 141 #define CKSVII2C_IC_INTR_MASK__M_RX_FULL__SHIFT 0x2 142 #define CKSVII2C_IC_INTR_MASK__M_TX_OVER__SHIFT 0x3 143 #define CKSVII2C_IC_INTR_MASK__M_TX_EMPTY__SHIFT 0x4 144 #define CKSVII2C_IC_INTR_MASK__M_RD_REQ__SHIFT 0x5 145 #define CKSVII2C_IC_INTR_MASK__M_TX_ABRT__SHIFT 0x6 146 #define CKSVII2C_IC_INTR_MASK__M_RX_DONE__SHIFT 0x7 147 #define CKSVII2C_IC_INTR_MASK__M_ACTIVITY__SHIFT 0x8 148 #define CKSVII2C_IC_INTR_MASK__M_STOP_DET__SHIFT 0x9 149 #define CKSVII2C_IC_INTR_MASK__M_START_DET__SHIFT 0xa 150 #define CKSVII2C_IC_INTR_MASK__M_GEN_CALL__SHIFT 0xb 151 #define CKSVII2C_IC_INTR_MASK__M_RESTART_DET__SHIFT 0xc 152 #define CKSVII2C_IC_INTR_MASK__M_MST_ON_HOLD__SHIFT 0xd 153 #define CKSVII2C_IC_INTR_MASK__M_RX_UNDER_MASK 0x00000001L 154 #define CKSVII2C_IC_INTR_MASK__M_RX_OVER_MASK 0x00000002L 155 #define CKSVII2C_IC_INTR_MASK__M_RX_FULL_MASK 0x00000004L 156 #define CKSVII2C_IC_INTR_MASK__M_TX_OVER_MASK 0x00000008L 157 #define CKSVII2C_IC_INTR_MASK__M_TX_EMPTY_MASK 0x00000010L 158 #define CKSVII2C_IC_INTR_MASK__M_RD_REQ_MASK 0x00000020L 159 #define CKSVII2C_IC_INTR_MASK__M_TX_ABRT_MASK 0x00000040L 160 #define CKSVII2C_IC_INTR_MASK__M_RX_DONE_MASK 0x00000080L 161 #define CKSVII2C_IC_INTR_MASK__M_ACTIVITY_MASK 0x00000100L 162 #define CKSVII2C_IC_INTR_MASK__M_STOP_DET_MASK 0x00000200L 163 #define CKSVII2C_IC_INTR_MASK__M_START_DET_MASK 0x00000400L 164 #define CKSVII2C_IC_INTR_MASK__M_GEN_CALL_MASK 0x00000800L 165 #define CKSVII2C_IC_INTR_MASK__M_RESTART_DET_MASK 0x00001000L 166 #define CKSVII2C_IC_INTR_MASK__M_MST_ON_HOLD_MASK 0x00002000L 167 //CKSVII2C_IC_RAW_INTR_STAT 168 //CKSVII2C_IC_RX_TL 169 #define CKSVII2C_IC_RX_TL__RX_TL__SHIFT 0x0 170 #define CKSVII2C_IC_RX_TL__RX_TL_MASK 0x000000FFL 171 //CKSVII2C_IC_TX_TL 172 #define CKSVII2C_IC_TX_TL__TX_TL__SHIFT 0x0 173 #define CKSVII2C_IC_TX_TL__TX_TL_MASK 0x000000FFL 174 //CKSVII2C_IC_CLR_INTR 175 //CKSVII2C_IC_CLR_RX_UNDER 176 //CKSVII2C_IC_CLR_RX_OVER 177 //CKSVII2C_IC_CLR_TX_OVER 178 //CKSVII2C_IC_CLR_RD_REQ 179 //CKSVII2C_IC_CLR_TX_ABRT 180 //CKSVII2C_IC_CLR_RX_DONE 181 //CKSVII2C_IC_CLR_ACTIVITY 182 //CKSVII2C_IC_CLR_STOP_DET 183 //CKSVII2C_IC_CLR_START_DET 184 //CKSVII2C_IC_CLR_GEN_CALL 185 //CKSVII2C_IC_ENABLE 186 #define CKSVII2C_IC_ENABLE__ENABLE__SHIFT 0x0 187 #define CKSVII2C_IC_ENABLE__ABORT__SHIFT 0x1 188 #define CKSVII2C_IC_ENABLE__TX_CMD_BLOCK__SHIFT 0x2 189 #define CKSVII2C_IC_ENABLE__ENABLE_MASK 0x00000001L 190 #define CKSVII2C_IC_ENABLE__ABORT_MASK 0x00000002L 191 #define CKSVII2C_IC_ENABLE__TX_CMD_BLOCK_MASK 0x00000004L 192 //CKSVII2C_IC_STATUS 193 #define CKSVII2C_IC_STATUS__ACTIVITY__SHIFT 0x0 194 #define CKSVII2C_IC_STATUS__TFNF__SHIFT 0x1 195 #define CKSVII2C_IC_STATUS__TFE__SHIFT 0x2 196 #define CKSVII2C_IC_STATUS__RFNE__SHIFT 0x3 197 #define CKSVII2C_IC_STATUS__RFF__SHIFT 0x4 198 #define CKSVII2C_IC_STATUS__MST_ACTIVITY__SHIFT 0x5 199 #define CKSVII2C_IC_STATUS__SLV_ACTIVITY__SHIFT 0x6 200 #define CKSVII2C_IC_STATUS__ACTIVITY_MASK 0x00000001L 201 #define CKSVII2C_IC_STATUS__TFNF_MASK 0x00000002L 202 #define CKSVII2C_IC_STATUS__TFE_MASK 0x00000004L 203 #define CKSVII2C_IC_STATUS__RFNE_MASK 0x00000008L 204 #define CKSVII2C_IC_STATUS__RFF_MASK 0x00000010L 205 #define CKSVII2C_IC_STATUS__MST_ACTIVITY_MASK 0x00000020L 206 #define CKSVII2C_IC_STATUS__SLV_ACTIVITY_MASK 0x00000040L 207 //CKSVII2C_IC_TXFLR 208 #define CKSVII2C_IC_TXFLR__TXFLR__SHIFT 0x0 209 #define CKSVII2C_IC_TXFLR__TXFLR_MASK 0x0000003FL 210 //CKSVII2C_IC_RXFLR 211 #define CKSVII2C_IC_RXFLR__RXFLR__SHIFT 0x0 212 #define CKSVII2C_IC_RXFLR__RXFLR_MASK 0x0000003FL 213 //CKSVII2C_IC_SDA_HOLD 214 #define CKSVII2C_IC_SDA_HOLD__IC_SDA_TX_HOLD__SHIFT 0x0 215 #define CKSVII2C_IC_SDA_HOLD__IC_SDA_RX_HOLD__SHIFT 0x10 216 #define CKSVII2C_IC_SDA_HOLD__IC_SDA_TX_HOLD_MASK 0x0000FFFFL 217 #define CKSVII2C_IC_SDA_HOLD__IC_SDA_RX_HOLD_MASK 0x00FF0000L 218 //CKSVII2C_IC_TX_ABRT_SOURCE 219 //CKSVII2C_IC_SLV_DATA_NACK_ONLY 220 //CKSVII2C_IC_DMA_CR 221 //CKSVII2C_IC_DMA_TDLR 222 //CKSVII2C_IC_DMA_RDLR 223 //CKSVII2C_IC_SDA_SETUP 224 #define CKSVII2C_IC_SDA_SETUP__SDA_SETUP__SHIFT 0x0 225 #define CKSVII2C_IC_SDA_SETUP__SDA_SETUP_MASK 0x000000FFL 226 //CKSVII2C_IC_ACK_GENERAL_CALL 227 #define CKSVII2C_IC_ACK_GENERAL_CALL__ACK_GEN_CALL__SHIFT 0x0 228 #define CKSVII2C_IC_ACK_GENERAL_CALL__ACK_GEN_CALL_MASK 0x00000001L 229 //CKSVII2C_IC_ENABLE_STATUS 230 #define CKSVII2C_IC_ENABLE_STATUS__IC_EN__SHIFT 0x0 231 #define CKSVII2C_IC_ENABLE_STATUS__SLV_DISABLED_WHILE_BUSY__SHIFT 0x1 232 #define CKSVII2C_IC_ENABLE_STATUS__SLV_RX_DATA_LOST__SHIFT 0x2 233 #define CKSVII2C_IC_ENABLE_STATUS__IC_EN_MASK 0x00000001L 234 #define CKSVII2C_IC_ENABLE_STATUS__SLV_DISABLED_WHILE_BUSY_MASK 0x00000002L 235 #define CKSVII2C_IC_ENABLE_STATUS__SLV_RX_DATA_LOST_MASK 0x00000004L 236 //CKSVII2C_IC_FS_SPKLEN 237 #define CKSVII2C_IC_FS_SPKLEN__IC_FS_SPKLEN__SHIFT 0x0 238 #define CKSVII2C_IC_FS_SPKLEN__IC_FS_SPKLEN_MASK 0x000000FFL 239 //CKSVII2C_IC_HS_SPKLEN 240 #define CKSVII2C_IC_HS_SPKLEN__IC_HS_SPKLEN__SHIFT 0x0 241 #define CKSVII2C_IC_HS_SPKLEN__IC_HS_SPKLEN_MASK 0x000000FFL 242 //CKSVII2C_IC_CLR_RESTART_DET 243 //CKSVII2C_IC_COMP_PARAM_1 244 #define CKSVII2C_IC_COMP_PARAM_1__APB_DATA_WIDTH__SHIFT 0x0 245 #define CKSVII2C_IC_COMP_PARAM_1__MAX_SPEED_MODE__SHIFT 0x2 246 #define CKSVII2C_IC_COMP_PARAM_1__HC_COUNT_VALUES__SHIFT 0x4 247 #define CKSVII2C_IC_COMP_PARAM_1__INTR_IO__SHIFT 0x5 248 #define CKSVII2C_IC_COMP_PARAM_1__HAS_DMA__SHIFT 0x6 249 #define CKSVII2C_IC_COMP_PARAM_1__ADD_ENCODED_PARAMS__SHIFT 0x7 250 #define CKSVII2C_IC_COMP_PARAM_1__RX_BUFFER_DEPTH__SHIFT 0x8 251 #define CKSVII2C_IC_COMP_PARAM_1__TX_BUFFER_DEPTH__SHIFT 0x10 252 #define CKSVII2C_IC_COMP_PARAM_1__APB_DATA_WIDTH_MASK 0x00000003L 253 #define CKSVII2C_IC_COMP_PARAM_1__MAX_SPEED_MODE_MASK 0x0000000CL 254 #define CKSVII2C_IC_COMP_PARAM_1__HC_COUNT_VALUES_MASK 0x00000010L 255 #define CKSVII2C_IC_COMP_PARAM_1__INTR_IO_MASK 0x00000020L 256 #define CKSVII2C_IC_COMP_PARAM_1__HAS_DMA_MASK 0x00000040L 257 #define CKSVII2C_IC_COMP_PARAM_1__ADD_ENCODED_PARAMS_MASK 0x00000080L 258 #define CKSVII2C_IC_COMP_PARAM_1__RX_BUFFER_DEPTH_MASK 0x0000FF00L 259 #define CKSVII2C_IC_COMP_PARAM_1__TX_BUFFER_DEPTH_MASK 0x00FF0000L 260 //CKSVII2C_IC_COMP_VERSION 261 #define CKSVII2C_IC_COMP_VERSION__IC_COMP_VERSION__SHIFT 0x0 262 #define CKSVII2C_IC_COMP_VERSION__IC_COMP_VERSION_MASK 0xFFFFFFFFL 263 //CKSVII2C_IC_COMP_TYPE 264 #define CKSVII2C_IC_COMP_TYPE__IC_COMP_TYPE__SHIFT 0x0 265 #define CKSVII2C_IC_COMP_TYPE__IC_COMP_TYPE_MASK 0xFFFFFFFFL 266 //CKSVII2C1_IC_CON 267 #define CKSVII2C1_IC_CON__IC1_MASTER_MODE__SHIFT 0x0 268 #define CKSVII2C1_IC_CON__IC1_MAX_SPEED_MODE__SHIFT 0x1 269 #define CKSVII2C1_IC_CON__IC1_10BITADDR_SLAVE__SHIFT 0x3 270 #define CKSVII2C1_IC_CON__IC1_10BITADDR_MASTER__SHIFT 0x4 271 #define CKSVII2C1_IC_CON__IC1_RESTART_EN__SHIFT 0x5 272 #define CKSVII2C1_IC_CON__IC1_SLAVE_DISABLE__SHIFT 0x6 273 #define CKSVII2C1_IC_CON__STOP1_DET_IFADDRESSED__SHIFT 0x7 274 #define CKSVII2C1_IC_CON__TX1_EMPTY_CTRL__SHIFT 0x8 275 #define CKSVII2C1_IC_CON__RX1_FIFO_FULL_HLD_CTRL__SHIFT 0x9 276 #define CKSVII2C1_IC_CON__IC1_MASTER_MODE_MASK 0x00000001L 277 #define CKSVII2C1_IC_CON__IC1_MAX_SPEED_MODE_MASK 0x00000006L 278 #define CKSVII2C1_IC_CON__IC1_10BITADDR_SLAVE_MASK 0x00000008L 279 #define CKSVII2C1_IC_CON__IC1_10BITADDR_MASTER_MASK 0x00000010L 280 #define CKSVII2C1_IC_CON__IC1_RESTART_EN_MASK 0x00000020L 281 #define CKSVII2C1_IC_CON__IC1_SLAVE_DISABLE_MASK 0x00000040L 282 #define CKSVII2C1_IC_CON__STOP1_DET_IFADDRESSED_MASK 0x00000080L 283 #define CKSVII2C1_IC_CON__TX1_EMPTY_CTRL_MASK 0x00000100L 284 #define CKSVII2C1_IC_CON__RX1_FIFO_FULL_HLD_CTRL_MASK 0x00000200L 285 //CKSVII2C1_IC_TAR 286 #define CKSVII2C1_IC_TAR__IC1_TAR__SHIFT 0x0 287 #define CKSVII2C1_IC_TAR__GC1_OR_START__SHIFT 0xa 288 #define CKSVII2C1_IC_TAR__SPECIAL1__SHIFT 0xb 289 #define CKSVII2C1_IC_TAR__IC1_10BITADDR_MASTER__SHIFT 0xc 290 #define CKSVII2C1_IC_TAR__IC1_TAR_MASK 0x000003FFL 291 #define CKSVII2C1_IC_TAR__GC1_OR_START_MASK 0x00000400L 292 #define CKSVII2C1_IC_TAR__SPECIAL1_MASK 0x00000800L 293 #define CKSVII2C1_IC_TAR__IC1_10BITADDR_MASTER_MASK 0x00001000L 294 //CKSVII2C1_IC_SAR 295 #define CKSVII2C1_IC_SAR__IC1_SAR__SHIFT 0x0 296 #define CKSVII2C1_IC_SAR__IC1_SAR_MASK 0x000003FFL 297 //CKSVII2C1_IC_HS_MADDR 298 #define CKSVII2C1_IC_HS_MADDR__IC1_HS_MADDR__SHIFT 0x0 299 #define CKSVII2C1_IC_HS_MADDR__IC1_HS_MADDR_MASK 0x00000007L 300 //CKSVII2C1_IC_DATA_CMD 301 #define CKSVII2C1_IC_DATA_CMD__DAT1__SHIFT 0x0 302 #define CKSVII2C1_IC_DATA_CMD__CMD1__SHIFT 0x8 303 #define CKSVII2C1_IC_DATA_CMD__STOP1__SHIFT 0x9 304 #define CKSVII2C1_IC_DATA_CMD__RESTART1__SHIFT 0xa 305 #define CKSVII2C1_IC_DATA_CMD__DAT1_MASK 0x000000FFL 306 #define CKSVII2C1_IC_DATA_CMD__CMD1_MASK 0x00000100L 307 #define CKSVII2C1_IC_DATA_CMD__STOP1_MASK 0x00000200L 308 #define CKSVII2C1_IC_DATA_CMD__RESTART1_MASK 0x00000400L 309 //CKSVII2C1_IC_SS_SCL_HCNT 310 #define CKSVII2C1_IC_SS_SCL_HCNT__IC1_SS_SCL_HCNT__SHIFT 0x0 311 #define CKSVII2C1_IC_SS_SCL_HCNT__IC1_SS_SCL_HCNT_MASK 0x0000FFFFL 312 //CKSVII2C1_IC_SS_SCL_LCNT 313 #define CKSVII2C1_IC_SS_SCL_LCNT__IC1_SS_SCL_LCNT__SHIFT 0x0 314 #define CKSVII2C1_IC_SS_SCL_LCNT__IC1_SS_SCL_LCNT_MASK 0x0000FFFFL 315 //CKSVII2C1_IC_FS_SCL_HCNT 316 #define CKSVII2C1_IC_FS_SCL_HCNT__IC1_FS_SCL_HCNT__SHIFT 0x0 317 #define CKSVII2C1_IC_FS_SCL_HCNT__IC1_FS_SCL_HCNT_MASK 0x0000FFFFL 318 //CKSVII2C1_IC_FS_SCL_LCNT 319 #define CKSVII2C1_IC_FS_SCL_LCNT__IC1_FS_SCL_LCNT__SHIFT 0x0 320 #define CKSVII2C1_IC_FS_SCL_LCNT__IC1_FS_SCL_LCNT_MASK 0x0000FFFFL 321 //CKSVII2C1_IC_HS_SCL_HCNT 322 #define CKSVII2C1_IC_HS_SCL_HCNT__IC1_HS_SCL_HCNT__SHIFT 0x0 323 #define CKSVII2C1_IC_HS_SCL_HCNT__IC1_HS_SCL_HCNT_MASK 0x0000FFFFL 324 //CKSVII2C1_IC_HS_SCL_LCNT 325 #define CKSVII2C1_IC_HS_SCL_LCNT__IC1_HS_SCL_LCNT__SHIFT 0x0 326 #define CKSVII2C1_IC_HS_SCL_LCNT__IC1_HS_SCL_LCNT_MASK 0x0000FFFFL 327 //CKSVII2C1_IC_INTR_STAT 328 #define CKSVII2C1_IC_INTR_STAT__R1_RX_UNDER__SHIFT 0x0 329 #define CKSVII2C1_IC_INTR_STAT__R1_RX_OVER__SHIFT 0x1 330 #define CKSVII2C1_IC_INTR_STAT__R1_RX_FULL__SHIFT 0x2 331 #define CKSVII2C1_IC_INTR_STAT__R1_TX_OVER__SHIFT 0x3 332 #define CKSVII2C1_IC_INTR_STAT__R1_TX_EMPTY__SHIFT 0x4 333 #define CKSVII2C1_IC_INTR_STAT__R1_RD_REQ__SHIFT 0x5 334 #define CKSVII2C1_IC_INTR_STAT__R1_TX_ABRT__SHIFT 0x6 335 #define CKSVII2C1_IC_INTR_STAT__R1_RX_DONE__SHIFT 0x7 336 #define CKSVII2C1_IC_INTR_STAT__R1_ACTIVITY__SHIFT 0x8 337 #define CKSVII2C1_IC_INTR_STAT__R1_STOP_DET__SHIFT 0x9 338 #define CKSVII2C1_IC_INTR_STAT__R1_START_DET__SHIFT 0xa 339 #define CKSVII2C1_IC_INTR_STAT__R1_GEN_CALL__SHIFT 0xb 340 #define CKSVII2C1_IC_INTR_STAT__R1_RESTART_DET__SHIFT 0xc 341 #define CKSVII2C1_IC_INTR_STAT__R1_MST_ON_HOLD__SHIFT 0xd 342 #define CKSVII2C1_IC_INTR_STAT__R1_RX_UNDER_MASK 0x00000001L 343 #define CKSVII2C1_IC_INTR_STAT__R1_RX_OVER_MASK 0x00000002L 344 #define CKSVII2C1_IC_INTR_STAT__R1_RX_FULL_MASK 0x00000004L 345 #define CKSVII2C1_IC_INTR_STAT__R1_TX_OVER_MASK 0x00000008L 346 #define CKSVII2C1_IC_INTR_STAT__R1_TX_EMPTY_MASK 0x00000010L 347 #define CKSVII2C1_IC_INTR_STAT__R1_RD_REQ_MASK 0x00000020L 348 #define CKSVII2C1_IC_INTR_STAT__R1_TX_ABRT_MASK 0x00000040L 349 #define CKSVII2C1_IC_INTR_STAT__R1_RX_DONE_MASK 0x00000080L 350 #define CKSVII2C1_IC_INTR_STAT__R1_ACTIVITY_MASK 0x00000100L 351 #define CKSVII2C1_IC_INTR_STAT__R1_STOP_DET_MASK 0x00000200L 352 #define CKSVII2C1_IC_INTR_STAT__R1_START_DET_MASK 0x00000400L 353 #define CKSVII2C1_IC_INTR_STAT__R1_GEN_CALL_MASK 0x00000800L 354 #define CKSVII2C1_IC_INTR_STAT__R1_RESTART_DET_MASK 0x00001000L 355 #define CKSVII2C1_IC_INTR_STAT__R1_MST_ON_HOLD_MASK 0x00002000L 356 //CKSVII2C1_IC_INTR_MASK 357 #define CKSVII2C1_IC_INTR_MASK__M1_RX_UNDER__SHIFT 0x0 358 #define CKSVII2C1_IC_INTR_MASK__M1_RX_OVER__SHIFT 0x1 359 #define CKSVII2C1_IC_INTR_MASK__M1_RX_FULL__SHIFT 0x2 360 #define CKSVII2C1_IC_INTR_MASK__M1_TX_OVER__SHIFT 0x3 361 #define CKSVII2C1_IC_INTR_MASK__M1_TX_EMPTY__SHIFT 0x4 362 #define CKSVII2C1_IC_INTR_MASK__M1_RD_REQ__SHIFT 0x5 363 #define CKSVII2C1_IC_INTR_MASK__M1_TX_ABRT__SHIFT 0x6 364 #define CKSVII2C1_IC_INTR_MASK__M1_RX_DONE__SHIFT 0x7 365 #define CKSVII2C1_IC_INTR_MASK__M1_ACTIVITY__SHIFT 0x8 366 #define CKSVII2C1_IC_INTR_MASK__M1_STOP_DET__SHIFT 0x9 367 #define CKSVII2C1_IC_INTR_MASK__M1_START_DET__SHIFT 0xa 368 #define CKSVII2C1_IC_INTR_MASK__M1_GEN_CALL__SHIFT 0xb 369 #define CKSVII2C1_IC_INTR_MASK__M1_RESTART_DET__SHIFT 0xc 370 #define CKSVII2C1_IC_INTR_MASK__M1_MST_ON_HOLD__SHIFT 0xd 371 #define CKSVII2C1_IC_INTR_MASK__M1_RX_UNDER_MASK 0x00000001L 372 #define CKSVII2C1_IC_INTR_MASK__M1_RX_OVER_MASK 0x00000002L 373 #define CKSVII2C1_IC_INTR_MASK__M1_RX_FULL_MASK 0x00000004L 374 #define CKSVII2C1_IC_INTR_MASK__M1_TX_OVER_MASK 0x00000008L 375 #define CKSVII2C1_IC_INTR_MASK__M1_TX_EMPTY_MASK 0x00000010L 376 #define CKSVII2C1_IC_INTR_MASK__M1_RD_REQ_MASK 0x00000020L 377 #define CKSVII2C1_IC_INTR_MASK__M1_TX_ABRT_MASK 0x00000040L 378 #define CKSVII2C1_IC_INTR_MASK__M1_RX_DONE_MASK 0x00000080L 379 #define CKSVII2C1_IC_INTR_MASK__M1_ACTIVITY_MASK 0x00000100L 380 #define CKSVII2C1_IC_INTR_MASK__M1_STOP_DET_MASK 0x00000200L 381 #define CKSVII2C1_IC_INTR_MASK__M1_START_DET_MASK 0x00000400L 382 #define CKSVII2C1_IC_INTR_MASK__M1_GEN_CALL_MASK 0x00000800L 383 #define CKSVII2C1_IC_INTR_MASK__M1_RESTART_DET_MASK 0x00001000L 384 #define CKSVII2C1_IC_INTR_MASK__M1_MST_ON_HOLD_MASK 0x00002000L 385 //CKSVII2C1_IC_RAW_INTR_STAT 386 //CKSVII2C1_IC_RX_TL 387 #define CKSVII2C1_IC_RX_TL__RX1_TL__SHIFT 0x0 388 #define CKSVII2C1_IC_RX_TL__RX1_TL_MASK 0x000000FFL 389 //CKSVII2C1_IC_TX_TL 390 #define CKSVII2C1_IC_TX_TL__TX1_TL__SHIFT 0x0 391 #define CKSVII2C1_IC_TX_TL__TX1_TL_MASK 0x000000FFL 392 //CKSVII2C1_IC_CLR_INTR 393 //CKSVII2C1_IC_CLR_RX_UNDER 394 //CKSVII2C1_IC_CLR_RX_OVER 395 //CKSVII2C1_IC_CLR_TX_OVER 396 //CKSVII2C1_IC_CLR_RD_REQ 397 //CKSVII2C1_IC_CLR_TX_ABRT 398 //CKSVII2C1_IC_CLR_RX_DONE 399 //CKSVII2C1_IC_CLR_ACTIVITY 400 //CKSVII2C1_IC_CLR_STOP_DET 401 //CKSVII2C1_IC_CLR_START_DET 402 //CKSVII2C1_IC_CLR_GEN_CALL 403 //CKSVII2C1_IC_ENABLE 404 #define CKSVII2C1_IC_ENABLE__ENABLE1__SHIFT 0x0 405 #define CKSVII2C1_IC_ENABLE__ABORT1__SHIFT 0x1 406 #define CKSVII2C1_IC_ENABLE__TX1_CMD_BLOCK__SHIFT 0x2 407 #define CKSVII2C1_IC_ENABLE__ENABLE1_MASK 0x00000001L 408 #define CKSVII2C1_IC_ENABLE__ABORT1_MASK 0x00000002L 409 #define CKSVII2C1_IC_ENABLE__TX1_CMD_BLOCK_MASK 0x00000004L 410 //CKSVII2C1_IC_STATUS 411 #define CKSVII2C1_IC_STATUS__ACTIVITY1__SHIFT 0x0 412 #define CKSVII2C1_IC_STATUS__TFNF1__SHIFT 0x1 413 #define CKSVII2C1_IC_STATUS__TFE1__SHIFT 0x2 414 #define CKSVII2C1_IC_STATUS__RFNE1__SHIFT 0x3 415 #define CKSVII2C1_IC_STATUS__RFF1__SHIFT 0x4 416 #define CKSVII2C1_IC_STATUS__MST1_ACTIVITY__SHIFT 0x5 417 #define CKSVII2C1_IC_STATUS__SLV1_ACTIVITY__SHIFT 0x6 418 #define CKSVII2C1_IC_STATUS__ACTIVITY1_MASK 0x00000001L 419 #define CKSVII2C1_IC_STATUS__TFNF1_MASK 0x00000002L 420 #define CKSVII2C1_IC_STATUS__TFE1_MASK 0x00000004L 421 #define CKSVII2C1_IC_STATUS__RFNE1_MASK 0x00000008L 422 #define CKSVII2C1_IC_STATUS__RFF1_MASK 0x00000010L 423 #define CKSVII2C1_IC_STATUS__MST1_ACTIVITY_MASK 0x00000020L 424 #define CKSVII2C1_IC_STATUS__SLV1_ACTIVITY_MASK 0x00000040L 425 //CKSVII2C1_IC_TXFLR 426 #define CKSVII2C1_IC_TXFLR__TXFLR1__SHIFT 0x0 427 #define CKSVII2C1_IC_TXFLR__TXFLR1_MASK 0x0000003FL 428 //CKSVII2C1_IC_RXFLR 429 #define CKSVII2C1_IC_RXFLR__RXFLR1__SHIFT 0x0 430 #define CKSVII2C1_IC_RXFLR__RXFLR1_MASK 0x0000003FL 431 //CKSVII2C1_IC_SDA_HOLD 432 #define CKSVII2C1_IC_SDA_HOLD__IC1_SDA_TX_HOLD__SHIFT 0x0 433 #define CKSVII2C1_IC_SDA_HOLD__IC1_SDA_RX_HOLD__SHIFT 0x10 434 #define CKSVII2C1_IC_SDA_HOLD__IC1_SDA_TX_HOLD_MASK 0x0000FFFFL 435 #define CKSVII2C1_IC_SDA_HOLD__IC1_SDA_RX_HOLD_MASK 0x00FF0000L 436 //CKSVII2C1_IC_TX_ABRT_SOURCE 437 //CKSVII2C1_IC_SLV_DATA_NACK_ONLY 438 //CKSVII2C1_IC_DMA_CR 439 //CKSVII2C1_IC_DMA_TDLR 440 //CKSVII2C1_IC_DMA_RDLR 441 //CKSVII2C1_IC_SDA_SETUP 442 #define CKSVII2C1_IC_SDA_SETUP__SDA1_SETUP__SHIFT 0x0 443 #define CKSVII2C1_IC_SDA_SETUP__SDA1_SETUP_MASK 0x000000FFL 444 //CKSVII2C1_IC_ACK_GENERAL_CALL 445 #define CKSVII2C1_IC_ACK_GENERAL_CALL__ACK1_GEN_CALL__SHIFT 0x0 446 #define CKSVII2C1_IC_ACK_GENERAL_CALL__ACK1_GEN_CALL_MASK 0x00000001L 447 //CKSVII2C1_IC_ENABLE_STATUS 448 #define CKSVII2C1_IC_ENABLE_STATUS__IC1_EN__SHIFT 0x0 449 #define CKSVII2C1_IC_ENABLE_STATUS__SLV1_DISABLED_WHILE_BUSY__SHIFT 0x1 450 #define CKSVII2C1_IC_ENABLE_STATUS__SLV1_RX_DATA_LOST__SHIFT 0x2 451 #define CKSVII2C1_IC_ENABLE_STATUS__IC1_EN_MASK 0x00000001L 452 #define CKSVII2C1_IC_ENABLE_STATUS__SLV1_DISABLED_WHILE_BUSY_MASK 0x00000002L 453 #define CKSVII2C1_IC_ENABLE_STATUS__SLV1_RX_DATA_LOST_MASK 0x00000004L 454 //CKSVII2C1_IC_FS_SPKLEN 455 #define CKSVII2C1_IC_FS_SPKLEN__IC1_FS_SPKLEN__SHIFT 0x0 456 #define CKSVII2C1_IC_FS_SPKLEN__IC1_FS_SPKLEN_MASK 0x000000FFL 457 //CKSVII2C1_IC_HS_SPKLEN 458 #define CKSVII2C1_IC_HS_SPKLEN__IC1_HS_SPKLEN__SHIFT 0x0 459 #define CKSVII2C1_IC_HS_SPKLEN__IC1_HS_SPKLEN_MASK 0x000000FFL 460 //CKSVII2C1_IC_CLR_RESTART_DET 461 //CKSVII2C1_IC_COMP_PARAM_1 462 #define CKSVII2C1_IC_COMP_PARAM_1__APB1_DATA_WIDTH__SHIFT 0x0 463 #define CKSVII2C1_IC_COMP_PARAM_1__MAX1_SPEED_MODE__SHIFT 0x2 464 #define CKSVII2C1_IC_COMP_PARAM_1__HC1_COUNT_VALUES__SHIFT 0x4 465 #define CKSVII2C1_IC_COMP_PARAM_1__INTR1_IO__SHIFT 0x5 466 #define CKSVII2C1_IC_COMP_PARAM_1__HAS1_DMA__SHIFT 0x6 467 #define CKSVII2C1_IC_COMP_PARAM_1__ADD1_ENCODED_PARAMS__SHIFT 0x7 468 #define CKSVII2C1_IC_COMP_PARAM_1__RX1_BUFFER_DEPTH__SHIFT 0x8 469 #define CKSVII2C1_IC_COMP_PARAM_1__TX1_BUFFER_DEPTH__SHIFT 0x10 470 #define CKSVII2C1_IC_COMP_PARAM_1__APB1_DATA_WIDTH_MASK 0x00000003L 471 #define CKSVII2C1_IC_COMP_PARAM_1__MAX1_SPEED_MODE_MASK 0x0000000CL 472 #define CKSVII2C1_IC_COMP_PARAM_1__HC1_COUNT_VALUES_MASK 0x00000010L 473 #define CKSVII2C1_IC_COMP_PARAM_1__INTR1_IO_MASK 0x00000020L 474 #define CKSVII2C1_IC_COMP_PARAM_1__HAS1_DMA_MASK 0x00000040L 475 #define CKSVII2C1_IC_COMP_PARAM_1__ADD1_ENCODED_PARAMS_MASK 0x00000080L 476 #define CKSVII2C1_IC_COMP_PARAM_1__RX1_BUFFER_DEPTH_MASK 0x0000FF00L 477 #define CKSVII2C1_IC_COMP_PARAM_1__TX1_BUFFER_DEPTH_MASK 0x00FF0000L 478 //CKSVII2C1_IC_COMP_VERSION 479 #define CKSVII2C1_IC_COMP_VERSION__IC1_COMP_VERSION__SHIFT 0x0 480 #define CKSVII2C1_IC_COMP_VERSION__IC1_COMP_VERSION_MASK 0xFFFFFFFFL 481 //CKSVII2C1_IC_COMP_TYPE 482 #define CKSVII2C1_IC_COMP_TYPE__IC1_COMP_TYPE__SHIFT 0x0 483 #define CKSVII2C1_IC_COMP_TYPE__IC1_COMP_TYPE_MASK 0xFFFFFFFFL 484 //SMUIO_MP_RESET_INTR 485 #define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR__SHIFT 0x0 486 #define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR_MASK 0x00000001L 487 //SMUIO_SOC_HALT 488 #define SMUIO_SOC_HALT__WDT_FORCE_PWROK_EN__SHIFT 0x2 489 #define SMUIO_SOC_HALT__WDT_FORCE_RESETn_EN__SHIFT 0x3 490 #define SMUIO_SOC_HALT__WDT_FORCE_PWROK_EN_MASK 0x00000004L 491 #define SMUIO_SOC_HALT__WDT_FORCE_RESETn_EN_MASK 0x00000008L 492 //SMUIO_PWRMGT 493 #define SMUIO_PWRMGT__i2c_clk_gate_en__SHIFT 0x0 494 #define SMUIO_PWRMGT__i2c1_clk_gate_en__SHIFT 0x4 495 #define SMUIO_PWRMGT__i2c_clk_gate_en_MASK 0x00000001L 496 #define SMUIO_PWRMGT__i2c1_clk_gate_en_MASK 0x00000010L 497 //SMUIO_GFX_MISC_CNTL 498 #define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff__SHIFT 0x0 499 #define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff_MASK 0x00000001L 500 //ROM_CNTL 501 #define ROM_CNTL__CLOCK_GATING_EN__SHIFT 0x0 502 #define ROM_CNTL__READ_MODE__SHIFT 0x1 503 #define ROM_CNTL__READ_MODE_OVERRIDE__SHIFT 0x3 504 #define ROM_CNTL__SPI_TIMING_RELAX_SCK__SHIFT 0x4 505 #define ROM_CNTL__SPI_TIMING_RELAX_SCK_OVERRIDE__SHIFT 0x5 506 #define ROM_CNTL__FOUR_BYTE_ADDRESS_MODE__SHIFT 0x6 507 #define ROM_CNTL__DUMMY_CYCLE_NUM__SHIFT 0x8 508 #define ROM_CNTL__SPI_TIMING_RELAX__SHIFT 0x14 509 #define ROM_CNTL__SPI_TIMING_RELAX_OVERRIDE__SHIFT 0x15 510 #define ROM_CNTL__SPI_FAST_MODE__SHIFT 0x16 511 #define ROM_CNTL__SPI_FAST_MODE_OVERRIDE__SHIFT 0x17 512 #define ROM_CNTL__SCK_PRESCALE_REFCLK__SHIFT 0x18 513 #define ROM_CNTL__SCK_PRESCALE_REFCLK_OVERRIDE__SHIFT 0x1c 514 #define ROM_CNTL__ROM_INDEX_ADDRESS_AUTO_INCREASE__SHIFT 0x1d 515 #define ROM_CNTL__CLOCK_GATING_EN_MASK 0x00000001L 516 #define ROM_CNTL__READ_MODE_MASK 0x00000006L 517 #define ROM_CNTL__READ_MODE_OVERRIDE_MASK 0x00000008L 518 #define ROM_CNTL__SPI_TIMING_RELAX_SCK_MASK 0x00000010L 519 #define ROM_CNTL__SPI_TIMING_RELAX_SCK_OVERRIDE_MASK 0x00000020L 520 #define ROM_CNTL__FOUR_BYTE_ADDRESS_MODE_MASK 0x00000040L 521 #define ROM_CNTL__DUMMY_CYCLE_NUM_MASK 0x00000F00L 522 #define ROM_CNTL__SPI_TIMING_RELAX_MASK 0x00100000L 523 #define ROM_CNTL__SPI_TIMING_RELAX_OVERRIDE_MASK 0x00200000L 524 #define ROM_CNTL__SPI_FAST_MODE_MASK 0x00400000L 525 #define ROM_CNTL__SPI_FAST_MODE_OVERRIDE_MASK 0x00800000L 526 #define ROM_CNTL__SCK_PRESCALE_REFCLK_MASK 0x0F000000L 527 #define ROM_CNTL__SCK_PRESCALE_REFCLK_OVERRIDE_MASK 0x10000000L 528 #define ROM_CNTL__ROM_INDEX_ADDRESS_AUTO_INCREASE_MASK 0x20000000L 529 //PAGE_MIRROR_CNTL 530 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR__SHIFT 0x0 531 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE__SHIFT 0x19 532 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE__SHIFT 0x1a 533 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE__SHIFT 0x1c 534 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR_MASK 0x01FFFFFFL 535 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE_MASK 0x02000000L 536 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE_MASK 0x0C000000L 537 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE_MASK 0x10000000L 538 //ROM_STATUS 539 #define ROM_STATUS__ROM_BUSY__SHIFT 0x0 540 #define ROM_STATUS__ROM_BUSY_MASK 0x00000001L 541 //CGTT_ROM_CLK_CTRL0 542 #define CGTT_ROM_CLK_CTRL0__ON_DELAY__SHIFT 0x0 543 #define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 544 #define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e 545 #define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f 546 #define CGTT_ROM_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL 547 #define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L 548 #define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L 549 #define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L 550 //ROM_INDEX 551 #define ROM_INDEX__ROM_INDEX__SHIFT 0x0 552 #define ROM_INDEX__ROM_INDEX_MASK 0x01FFFFFFL 553 //ROM_DATA 554 #define ROM_DATA__ROM_DATA__SHIFT 0x0 555 #define ROM_DATA__ROM_DATA_MASK 0xFFFFFFFFL 556 //ROM_START 557 #define ROM_START__ROM_START__SHIFT 0x0 558 #define ROM_START__ROM_START_MASK 0x01FFFFFFL 559 //ROM_SW_CNTL 560 #define ROM_SW_CNTL__DATA_SIZE__SHIFT 0x0 561 #define ROM_SW_CNTL__COMMAND_SIZE__SHIFT 0x10 562 #define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE__SHIFT 0x13 563 #define ROM_SW_CNTL__DATA_SIZE_MASK 0x0000FFFFL 564 #define ROM_SW_CNTL__COMMAND_SIZE_MASK 0x00070000L 565 #define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE_MASK 0x00080000L 566 //ROM_SW_STATUS 567 #define ROM_SW_STATUS__ROM_SW_DONE__SHIFT 0x0 568 #define ROM_SW_STATUS__ROM_SW_DONE_MASK 0x00000001L 569 //ROM_SW_COMMAND 570 #define ROM_SW_COMMAND__ROM_SW_INSTRUCTION__SHIFT 0x0 571 #define ROM_SW_COMMAND__ROM_SW_ADDRESS__SHIFT 0x8 572 #define ROM_SW_COMMAND__ROM_SW_INSTRUCTION_MASK 0x000000FFL 573 #define ROM_SW_COMMAND__ROM_SW_ADDRESS_MASK 0xFFFFFF00L 574 //ROM_SW_DATA_1 575 #define ROM_SW_DATA_1__ROM_SW_DATA__SHIFT 0x0 576 #define ROM_SW_DATA_1__ROM_SW_DATA_MASK 0xFFFFFFFFL 577 //ROM_SW_DATA_2 578 #define ROM_SW_DATA_2__ROM_SW_DATA__SHIFT 0x0 579 #define ROM_SW_DATA_2__ROM_SW_DATA_MASK 0xFFFFFFFFL 580 //ROM_SW_DATA_3 581 #define ROM_SW_DATA_3__ROM_SW_DATA__SHIFT 0x0 582 #define ROM_SW_DATA_3__ROM_SW_DATA_MASK 0xFFFFFFFFL 583 //ROM_SW_DATA_4 584 #define ROM_SW_DATA_4__ROM_SW_DATA__SHIFT 0x0 585 #define ROM_SW_DATA_4__ROM_SW_DATA_MASK 0xFFFFFFFFL 586 //ROM_SW_DATA_5 587 #define ROM_SW_DATA_5__ROM_SW_DATA__SHIFT 0x0 588 #define ROM_SW_DATA_5__ROM_SW_DATA_MASK 0xFFFFFFFFL 589 //ROM_SW_DATA_6 590 #define ROM_SW_DATA_6__ROM_SW_DATA__SHIFT 0x0 591 #define ROM_SW_DATA_6__ROM_SW_DATA_MASK 0xFFFFFFFFL 592 //ROM_SW_DATA_7 593 #define ROM_SW_DATA_7__ROM_SW_DATA__SHIFT 0x0 594 #define ROM_SW_DATA_7__ROM_SW_DATA_MASK 0xFFFFFFFFL 595 //ROM_SW_DATA_8 596 #define ROM_SW_DATA_8__ROM_SW_DATA__SHIFT 0x0 597 #define ROM_SW_DATA_8__ROM_SW_DATA_MASK 0xFFFFFFFFL 598 //ROM_SW_DATA_9 599 #define ROM_SW_DATA_9__ROM_SW_DATA__SHIFT 0x0 600 #define ROM_SW_DATA_9__ROM_SW_DATA_MASK 0xFFFFFFFFL 601 //ROM_SW_DATA_10 602 #define ROM_SW_DATA_10__ROM_SW_DATA__SHIFT 0x0 603 #define ROM_SW_DATA_10__ROM_SW_DATA_MASK 0xFFFFFFFFL 604 //ROM_SW_DATA_11 605 #define ROM_SW_DATA_11__ROM_SW_DATA__SHIFT 0x0 606 #define ROM_SW_DATA_11__ROM_SW_DATA_MASK 0xFFFFFFFFL 607 //ROM_SW_DATA_12 608 #define ROM_SW_DATA_12__ROM_SW_DATA__SHIFT 0x0 609 #define ROM_SW_DATA_12__ROM_SW_DATA_MASK 0xFFFFFFFFL 610 //ROM_SW_DATA_13 611 #define ROM_SW_DATA_13__ROM_SW_DATA__SHIFT 0x0 612 #define ROM_SW_DATA_13__ROM_SW_DATA_MASK 0xFFFFFFFFL 613 //ROM_SW_DATA_14 614 #define ROM_SW_DATA_14__ROM_SW_DATA__SHIFT 0x0 615 #define ROM_SW_DATA_14__ROM_SW_DATA_MASK 0xFFFFFFFFL 616 //ROM_SW_DATA_15 617 #define ROM_SW_DATA_15__ROM_SW_DATA__SHIFT 0x0 618 #define ROM_SW_DATA_15__ROM_SW_DATA_MASK 0xFFFFFFFFL 619 //ROM_SW_DATA_16 620 #define ROM_SW_DATA_16__ROM_SW_DATA__SHIFT 0x0 621 #define ROM_SW_DATA_16__ROM_SW_DATA_MASK 0xFFFFFFFFL 622 //ROM_SW_DATA_17 623 #define ROM_SW_DATA_17__ROM_SW_DATA__SHIFT 0x0 624 #define ROM_SW_DATA_17__ROM_SW_DATA_MASK 0xFFFFFFFFL 625 //ROM_SW_DATA_18 626 #define ROM_SW_DATA_18__ROM_SW_DATA__SHIFT 0x0 627 #define ROM_SW_DATA_18__ROM_SW_DATA_MASK 0xFFFFFFFFL 628 //ROM_SW_DATA_19 629 #define ROM_SW_DATA_19__ROM_SW_DATA__SHIFT 0x0 630 #define ROM_SW_DATA_19__ROM_SW_DATA_MASK 0xFFFFFFFFL 631 //ROM_SW_DATA_20 632 #define ROM_SW_DATA_20__ROM_SW_DATA__SHIFT 0x0 633 #define ROM_SW_DATA_20__ROM_SW_DATA_MASK 0xFFFFFFFFL 634 //ROM_SW_DATA_21 635 #define ROM_SW_DATA_21__ROM_SW_DATA__SHIFT 0x0 636 #define ROM_SW_DATA_21__ROM_SW_DATA_MASK 0xFFFFFFFFL 637 //ROM_SW_DATA_22 638 #define ROM_SW_DATA_22__ROM_SW_DATA__SHIFT 0x0 639 #define ROM_SW_DATA_22__ROM_SW_DATA_MASK 0xFFFFFFFFL 640 //ROM_SW_DATA_23 641 #define ROM_SW_DATA_23__ROM_SW_DATA__SHIFT 0x0 642 #define ROM_SW_DATA_23__ROM_SW_DATA_MASK 0xFFFFFFFFL 643 //ROM_SW_DATA_24 644 #define ROM_SW_DATA_24__ROM_SW_DATA__SHIFT 0x0 645 #define ROM_SW_DATA_24__ROM_SW_DATA_MASK 0xFFFFFFFFL 646 //ROM_SW_DATA_25 647 #define ROM_SW_DATA_25__ROM_SW_DATA__SHIFT 0x0 648 #define ROM_SW_DATA_25__ROM_SW_DATA_MASK 0xFFFFFFFFL 649 //ROM_SW_DATA_26 650 #define ROM_SW_DATA_26__ROM_SW_DATA__SHIFT 0x0 651 #define ROM_SW_DATA_26__ROM_SW_DATA_MASK 0xFFFFFFFFL 652 //ROM_SW_DATA_27 653 #define ROM_SW_DATA_27__ROM_SW_DATA__SHIFT 0x0 654 #define ROM_SW_DATA_27__ROM_SW_DATA_MASK 0xFFFFFFFFL 655 //ROM_SW_DATA_28 656 #define ROM_SW_DATA_28__ROM_SW_DATA__SHIFT 0x0 657 #define ROM_SW_DATA_28__ROM_SW_DATA_MASK 0xFFFFFFFFL 658 //ROM_SW_DATA_29 659 #define ROM_SW_DATA_29__ROM_SW_DATA__SHIFT 0x0 660 #define ROM_SW_DATA_29__ROM_SW_DATA_MASK 0xFFFFFFFFL 661 //ROM_SW_DATA_30 662 #define ROM_SW_DATA_30__ROM_SW_DATA__SHIFT 0x0 663 #define ROM_SW_DATA_30__ROM_SW_DATA_MASK 0xFFFFFFFFL 664 //ROM_SW_DATA_31 665 #define ROM_SW_DATA_31__ROM_SW_DATA__SHIFT 0x0 666 #define ROM_SW_DATA_31__ROM_SW_DATA_MASK 0xFFFFFFFFL 667 //ROM_SW_DATA_32 668 #define ROM_SW_DATA_32__ROM_SW_DATA__SHIFT 0x0 669 #define ROM_SW_DATA_32__ROM_SW_DATA_MASK 0xFFFFFFFFL 670 //ROM_SW_DATA_33 671 #define ROM_SW_DATA_33__ROM_SW_DATA__SHIFT 0x0 672 #define ROM_SW_DATA_33__ROM_SW_DATA_MASK 0xFFFFFFFFL 673 //ROM_SW_DATA_34 674 #define ROM_SW_DATA_34__ROM_SW_DATA__SHIFT 0x0 675 #define ROM_SW_DATA_34__ROM_SW_DATA_MASK 0xFFFFFFFFL 676 //ROM_SW_DATA_35 677 #define ROM_SW_DATA_35__ROM_SW_DATA__SHIFT 0x0 678 #define ROM_SW_DATA_35__ROM_SW_DATA_MASK 0xFFFFFFFFL 679 //ROM_SW_DATA_36 680 #define ROM_SW_DATA_36__ROM_SW_DATA__SHIFT 0x0 681 #define ROM_SW_DATA_36__ROM_SW_DATA_MASK 0xFFFFFFFFL 682 //ROM_SW_DATA_37 683 #define ROM_SW_DATA_37__ROM_SW_DATA__SHIFT 0x0 684 #define ROM_SW_DATA_37__ROM_SW_DATA_MASK 0xFFFFFFFFL 685 //ROM_SW_DATA_38 686 #define ROM_SW_DATA_38__ROM_SW_DATA__SHIFT 0x0 687 #define ROM_SW_DATA_38__ROM_SW_DATA_MASK 0xFFFFFFFFL 688 //ROM_SW_DATA_39 689 #define ROM_SW_DATA_39__ROM_SW_DATA__SHIFT 0x0 690 #define ROM_SW_DATA_39__ROM_SW_DATA_MASK 0xFFFFFFFFL 691 //ROM_SW_DATA_40 692 #define ROM_SW_DATA_40__ROM_SW_DATA__SHIFT 0x0 693 #define ROM_SW_DATA_40__ROM_SW_DATA_MASK 0xFFFFFFFFL 694 //ROM_SW_DATA_41 695 #define ROM_SW_DATA_41__ROM_SW_DATA__SHIFT 0x0 696 #define ROM_SW_DATA_41__ROM_SW_DATA_MASK 0xFFFFFFFFL 697 //ROM_SW_DATA_42 698 #define ROM_SW_DATA_42__ROM_SW_DATA__SHIFT 0x0 699 #define ROM_SW_DATA_42__ROM_SW_DATA_MASK 0xFFFFFFFFL 700 //ROM_SW_DATA_43 701 #define ROM_SW_DATA_43__ROM_SW_DATA__SHIFT 0x0 702 #define ROM_SW_DATA_43__ROM_SW_DATA_MASK 0xFFFFFFFFL 703 //ROM_SW_DATA_44 704 #define ROM_SW_DATA_44__ROM_SW_DATA__SHIFT 0x0 705 #define ROM_SW_DATA_44__ROM_SW_DATA_MASK 0xFFFFFFFFL 706 //ROM_SW_DATA_45 707 #define ROM_SW_DATA_45__ROM_SW_DATA__SHIFT 0x0 708 #define ROM_SW_DATA_45__ROM_SW_DATA_MASK 0xFFFFFFFFL 709 //ROM_SW_DATA_46 710 #define ROM_SW_DATA_46__ROM_SW_DATA__SHIFT 0x0 711 #define ROM_SW_DATA_46__ROM_SW_DATA_MASK 0xFFFFFFFFL 712 //ROM_SW_DATA_47 713 #define ROM_SW_DATA_47__ROM_SW_DATA__SHIFT 0x0 714 #define ROM_SW_DATA_47__ROM_SW_DATA_MASK 0xFFFFFFFFL 715 //ROM_SW_DATA_48 716 #define ROM_SW_DATA_48__ROM_SW_DATA__SHIFT 0x0 717 #define ROM_SW_DATA_48__ROM_SW_DATA_MASK 0xFFFFFFFFL 718 //ROM_SW_DATA_49 719 #define ROM_SW_DATA_49__ROM_SW_DATA__SHIFT 0x0 720 #define ROM_SW_DATA_49__ROM_SW_DATA_MASK 0xFFFFFFFFL 721 //ROM_SW_DATA_50 722 #define ROM_SW_DATA_50__ROM_SW_DATA__SHIFT 0x0 723 #define ROM_SW_DATA_50__ROM_SW_DATA_MASK 0xFFFFFFFFL 724 //ROM_SW_DATA_51 725 #define ROM_SW_DATA_51__ROM_SW_DATA__SHIFT 0x0 726 #define ROM_SW_DATA_51__ROM_SW_DATA_MASK 0xFFFFFFFFL 727 //ROM_SW_DATA_52 728 #define ROM_SW_DATA_52__ROM_SW_DATA__SHIFT 0x0 729 #define ROM_SW_DATA_52__ROM_SW_DATA_MASK 0xFFFFFFFFL 730 //ROM_SW_DATA_53 731 #define ROM_SW_DATA_53__ROM_SW_DATA__SHIFT 0x0 732 #define ROM_SW_DATA_53__ROM_SW_DATA_MASK 0xFFFFFFFFL 733 //ROM_SW_DATA_54 734 #define ROM_SW_DATA_54__ROM_SW_DATA__SHIFT 0x0 735 #define ROM_SW_DATA_54__ROM_SW_DATA_MASK 0xFFFFFFFFL 736 //ROM_SW_DATA_55 737 #define ROM_SW_DATA_55__ROM_SW_DATA__SHIFT 0x0 738 #define ROM_SW_DATA_55__ROM_SW_DATA_MASK 0xFFFFFFFFL 739 //ROM_SW_DATA_56 740 #define ROM_SW_DATA_56__ROM_SW_DATA__SHIFT 0x0 741 #define ROM_SW_DATA_56__ROM_SW_DATA_MASK 0xFFFFFFFFL 742 //ROM_SW_DATA_57 743 #define ROM_SW_DATA_57__ROM_SW_DATA__SHIFT 0x0 744 #define ROM_SW_DATA_57__ROM_SW_DATA_MASK 0xFFFFFFFFL 745 //ROM_SW_DATA_58 746 #define ROM_SW_DATA_58__ROM_SW_DATA__SHIFT 0x0 747 #define ROM_SW_DATA_58__ROM_SW_DATA_MASK 0xFFFFFFFFL 748 //ROM_SW_DATA_59 749 #define ROM_SW_DATA_59__ROM_SW_DATA__SHIFT 0x0 750 #define ROM_SW_DATA_59__ROM_SW_DATA_MASK 0xFFFFFFFFL 751 //ROM_SW_DATA_60 752 #define ROM_SW_DATA_60__ROM_SW_DATA__SHIFT 0x0 753 #define ROM_SW_DATA_60__ROM_SW_DATA_MASK 0xFFFFFFFFL 754 //ROM_SW_DATA_61 755 #define ROM_SW_DATA_61__ROM_SW_DATA__SHIFT 0x0 756 #define ROM_SW_DATA_61__ROM_SW_DATA_MASK 0xFFFFFFFFL 757 //ROM_SW_DATA_62 758 #define ROM_SW_DATA_62__ROM_SW_DATA__SHIFT 0x0 759 #define ROM_SW_DATA_62__ROM_SW_DATA_MASK 0xFFFFFFFFL 760 //ROM_SW_DATA_63 761 #define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0 762 #define ROM_SW_DATA_63__ROM_SW_DATA_MASK 0xFFFFFFFFL 763 //ROM_SW_DATA_64 764 #define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0 765 #define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xFFFFFFFFL 766 //SMU_GPIOPAD_SW_INT_STAT 767 #define SMU_GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x0 768 #define SMU_GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x00000001L 769 //SMU_GPIOPAD_MASK 770 #define SMU_GPIOPAD_MASK__GPIO_MASK__SHIFT 0x0 771 #define SMU_GPIOPAD_MASK__GPIO_MASK_MASK 0x7FFFFFFFL 772 //SMU_GPIOPAD_A 773 #define SMU_GPIOPAD_A__GPIO_A__SHIFT 0x0 774 #define SMU_GPIOPAD_A__GPIO_A_MASK 0x7FFFFFFFL 775 //SMU_GPIOPAD_TXIMPSEL 776 #define SMU_GPIOPAD_TXIMPSEL__GPIO_TXIMPSEL__SHIFT 0x0 777 #define SMU_GPIOPAD_TXIMPSEL__GPIO_TXIMPSEL_MASK 0x7FFFFFFFL 778 //SMU_GPIOPAD_EN 779 #define SMU_GPIOPAD_EN__GPIO_EN__SHIFT 0x0 780 #define SMU_GPIOPAD_EN__GPIO_EN_MASK 0x7FFFFFFFL 781 //SMU_GPIOPAD_Y 782 #define SMU_GPIOPAD_Y__GPIO_Y__SHIFT 0x0 783 #define SMU_GPIOPAD_Y__GPIO_Y_MASK 0x7FFFFFFFL 784 //SMU_GPIOPAD_RXEN 785 #define SMU_GPIOPAD_RXEN__GPIO_RXEN__SHIFT 0x0 786 #define SMU_GPIOPAD_RXEN__GPIO_RXEN_MASK 0x7FFFFFFFL 787 //SMU_GPIOPAD_RCVR_SEL0 788 #define SMU_GPIOPAD_RCVR_SEL0__GPIO_RCVR_SEL0__SHIFT 0x0 789 #define SMU_GPIOPAD_RCVR_SEL0__GPIO_RCVR_SEL0_MASK 0x7FFFFFFFL 790 //SMU_GPIOPAD_RCVR_SEL1 791 #define SMU_GPIOPAD_RCVR_SEL1__GPIO_RCVR_SEL1__SHIFT 0x0 792 #define SMU_GPIOPAD_RCVR_SEL1__GPIO_RCVR_SEL1_MASK 0x7FFFFFFFL 793 //SMU_GPIOPAD_PU_EN 794 #define SMU_GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x0 795 #define SMU_GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7FFFFFFFL 796 //SMU_GPIOPAD_PD_EN 797 #define SMU_GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x0 798 #define SMU_GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7FFFFFFFL 799 //SMU_GPIOPAD_PINSTRAPS 800 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x0 801 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x1 802 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x2 803 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x3 804 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x4 805 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x5 806 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x6 807 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x7 808 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x8 809 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x9 810 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0xa 811 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0xb 812 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0xc 813 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0xd 814 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0xe 815 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0xf 816 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x10 817 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x11 818 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x12 819 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x13 820 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x14 821 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x15 822 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x16 823 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x17 824 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x18 825 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x19 826 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x1a 827 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x1b 828 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x1c 829 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x1d 830 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x1e 831 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x00000001L 832 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x00000002L 833 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x00000004L 834 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x00000008L 835 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x00000010L 836 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x00000020L 837 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x00000040L 838 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x00000080L 839 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x00000100L 840 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x00000200L 841 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x00000400L 842 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x00000800L 843 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x00001000L 844 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x00002000L 845 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x00004000L 846 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x00008000L 847 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x00010000L 848 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x00020000L 849 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x00040000L 850 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x00080000L 851 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x00100000L 852 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x00200000L 853 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x00400000L 854 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x00800000L 855 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x01000000L 856 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x02000000L 857 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x04000000L 858 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x08000000L 859 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000L 860 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000L 861 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000L 862 //DFT_PINSTRAPS 863 #define DFT_PINSTRAPS__DFT_PINSTRAPS__SHIFT 0x0 864 #define DFT_PINSTRAPS__DFT_PINSTRAPS_MASK 0x000003FFL 865 //SMU_GPIOPAD_INT_STAT_EN 866 #define SMU_GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x0 867 #define SMU_GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x1f 868 #define SMU_GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1FFFFFFFL 869 #define SMU_GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000L 870 //SMU_GPIOPAD_INT_STAT 871 #define SMU_GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x0 872 #define SMU_GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x1f 873 #define SMU_GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1FFFFFFFL 874 #define SMU_GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000L 875 //SMU_GPIOPAD_INT_STAT_AK 876 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x0 877 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x1 878 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x2 879 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x3 880 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x4 881 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x5 882 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x6 883 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x7 884 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x8 885 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x9 886 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0xa 887 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0xb 888 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0xc 889 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0xd 890 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0xe 891 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0xf 892 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x10 893 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x11 894 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x12 895 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x13 896 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x14 897 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x15 898 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x16 899 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x17 900 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x18 901 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x19 902 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x1a 903 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x1b 904 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x1c 905 #define SMU_GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x1f 906 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x00000001L 907 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x00000002L 908 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x00000004L 909 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x00000008L 910 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x00000010L 911 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x00000020L 912 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x00000040L 913 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x00000080L 914 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x00000100L 915 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x00000200L 916 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x00000400L 917 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x00000800L 918 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x00001000L 919 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x00002000L 920 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x00004000L 921 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x00008000L 922 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x00010000L 923 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x00020000L 924 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x00040000L 925 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x00080000L 926 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x00100000L 927 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x00200000L 928 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x00400000L 929 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x00800000L 930 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x01000000L 931 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x02000000L 932 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x04000000L 933 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x08000000L 934 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000L 935 #define SMU_GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000L 936 //SMU_GPIOPAD_INT_EN 937 #define SMU_GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x0 938 #define SMU_GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x1f 939 #define SMU_GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1FFFFFFFL 940 #define SMU_GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000L 941 //SMU_GPIOPAD_INT_TYPE 942 #define SMU_GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x0 943 #define SMU_GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x1f 944 #define SMU_GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1FFFFFFFL 945 #define SMU_GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000L 946 //SMU_GPIOPAD_INT_POLARITY 947 #define SMU_GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x0 948 #define SMU_GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x1f 949 #define SMU_GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1FFFFFFFL 950 #define SMU_GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000L 951 //ROM_CC_BIF_PINSTRAP 952 #define ROM_CC_BIF_PINSTRAP__BIOS_ROM_EN__SHIFT 0x0 953 #define ROM_CC_BIF_PINSTRAP__BIF_MEM_AP_SIZE__SHIFT 0x1 954 #define ROM_CC_BIF_PINSTRAP__ROM_CONFIG__SHIFT 0x4 955 #define ROM_CC_BIF_PINSTRAP__BIF_GEN3_DIS_A__SHIFT 0x7 956 #define ROM_CC_BIF_PINSTRAP__BIF_CLK_PM_EN__SHIFT 0x8 957 #define ROM_CC_BIF_PINSTRAP__BIF_VGA_DIS__SHIFT 0x9 958 #define ROM_CC_BIF_PINSTRAP__BIF_LC_TX_SWING__SHIFT 0xa 959 #define ROM_CC_BIF_PINSTRAP__BIOS_ROM_EN_MASK 0x00000001L 960 #define ROM_CC_BIF_PINSTRAP__BIF_MEM_AP_SIZE_MASK 0x0000000EL 961 #define ROM_CC_BIF_PINSTRAP__ROM_CONFIG_MASK 0x00000070L 962 #define ROM_CC_BIF_PINSTRAP__BIF_GEN3_DIS_A_MASK 0x00000080L 963 #define ROM_CC_BIF_PINSTRAP__BIF_CLK_PM_EN_MASK 0x00000100L 964 #define ROM_CC_BIF_PINSTRAP__BIF_VGA_DIS_MASK 0x00000200L 965 #define ROM_CC_BIF_PINSTRAP__BIF_LC_TX_SWING_MASK 0x00000400L 966 //IO_SMUIO_PINSTRAP 967 #define IO_SMUIO_PINSTRAP__AUD_PORT_CONN__SHIFT 0x0 968 #define IO_SMUIO_PINSTRAP__AUD__SHIFT 0x3 969 #define IO_SMUIO_PINSTRAP__BOARD_CONFIG__SHIFT 0x5 970 #define IO_SMUIO_PINSTRAP__SMBUS_ADDR__SHIFT 0x8 971 #define IO_SMUIO_PINSTRAP__AUD_PORT_CONN_MASK 0x00000007L 972 #define IO_SMUIO_PINSTRAP__AUD_MASK 0x00000018L 973 #define IO_SMUIO_PINSTRAP__BOARD_CONFIG_MASK 0x000000E0L 974 #define IO_SMUIO_PINSTRAP__SMBUS_ADDR_MASK 0x00000100L 975 //SMUIO_PCC_CONTROL 976 #define SMUIO_PCC_CONTROL__PCC_POLARITY__SHIFT 0x0 977 #define SMUIO_PCC_CONTROL__PCC_POLARITY_MASK 0x00000001L 978 //SMUIO_PCC_GPIO_SELECT 979 #define SMUIO_PCC_GPIO_SELECT__GPIO__SHIFT 0x0 980 #define SMUIO_PCC_GPIO_SELECT__GPIO_MASK 0xFFFFFFFFL 981 //SMUIO_GPIO_INT0_SELECT 982 #define SMUIO_GPIO_INT0_SELECT__GPIO_INT0_SELECT__SHIFT 0x0 983 #define SMUIO_GPIO_INT0_SELECT__GPIO_INT0_SELECT_MASK 0xFFFFFFFFL 984 //SMUIO_GPIO_INT1_SELECT 985 #define SMUIO_GPIO_INT1_SELECT__GPIO_INT1_SELECT__SHIFT 0x0 986 #define SMUIO_GPIO_INT1_SELECT__GPIO_INT1_SELECT_MASK 0xFFFFFFFFL 987 //SMUIO_GPIO_INT2_SELECT 988 #define SMUIO_GPIO_INT2_SELECT__GPIO_INT2_SELECT__SHIFT 0x0 989 #define SMUIO_GPIO_INT2_SELECT__GPIO_INT2_SELECT_MASK 0xFFFFFFFFL 990 //SMUIO_GPIO_INT3_SELECT 991 #define SMUIO_GPIO_INT3_SELECT__GPIO_INT3_SELECT__SHIFT 0x0 992 #define SMUIO_GPIO_INT3_SELECT__GPIO_INT3_SELECT_MASK 0xFFFFFFFFL 993 //SMU_GPIOPAD_MP_INT0_STAT 994 #define SMU_GPIOPAD_MP_INT0_STAT__GPIO_MP_INT0_STAT__SHIFT 0x0 995 #define SMU_GPIOPAD_MP_INT0_STAT__GPIO_MP_INT0_STAT_MASK 0x1FFFFFFFL 996 //SMU_GPIOPAD_MP_INT1_STAT 997 #define SMU_GPIOPAD_MP_INT1_STAT__GPIO_MP_INT1_STAT__SHIFT 0x0 998 #define SMU_GPIOPAD_MP_INT1_STAT__GPIO_MP_INT1_STAT_MASK 0x1FFFFFFFL 999 //SMU_GPIOPAD_MP_INT2_STAT 1000 #define SMU_GPIOPAD_MP_INT2_STAT__GPIO_MP_INT2_STAT__SHIFT 0x0 1001 #define SMU_GPIOPAD_MP_INT2_STAT__GPIO_MP_INT2_STAT_MASK 0x1FFFFFFFL 1002 //SMU_GPIOPAD_MP_INT3_STAT 1003 #define SMU_GPIOPAD_MP_INT3_STAT__GPIO_MP_INT3_STAT__SHIFT 0x0 1004 #define SMU_GPIOPAD_MP_INT3_STAT__GPIO_MP_INT3_STAT_MASK 0x1FFFFFFFL 1005 //SMIO_INDEX 1006 #define SMIO_INDEX__SW_SMIO_INDEX__SHIFT 0x0 1007 #define SMIO_INDEX__SW_SMIO_INDEX_MASK 0x00000001L 1008 //S0_VID_SMIO_CNTL 1009 #define S0_VID_SMIO_CNTL__S0_SMIO_VALUES__SHIFT 0x0 1010 #define S0_VID_SMIO_CNTL__S0_SMIO_VALUES_MASK 0xFFFFFFFFL 1011 //S1_VID_SMIO_CNTL 1012 #define S1_VID_SMIO_CNTL__S1_SMIO_VALUES__SHIFT 0x0 1013 #define S1_VID_SMIO_CNTL__S1_SMIO_VALUES_MASK 0xFFFFFFFFL 1014 //OPEN_DRAIN_SELECT 1015 #define OPEN_DRAIN_SELECT__OPEN_DRAIN_SELECT__SHIFT 0x0 1016 #define OPEN_DRAIN_SELECT__RESERVED__SHIFT 0x1f 1017 #define OPEN_DRAIN_SELECT__OPEN_DRAIN_SELECT_MASK 0x7FFFFFFFL 1018 #define OPEN_DRAIN_SELECT__RESERVED_MASK 0x80000000L 1019 //SMIO_ENABLE 1020 #define SMIO_ENABLE__SMIO_ENABLE__SHIFT 0x0 1021 #define SMIO_ENABLE__SMIO_ENABLE_MASK 0xFFFFFFFFL 1022 //SMU_GPIOPAD_S0 1023 #define SMU_GPIOPAD_S0__GPIO_S0__SHIFT 0x0 1024 #define SMU_GPIOPAD_S0__GPIO_S0_MASK 0x7FFFFFFFL 1025 //SMU_GPIOPAD_S1 1026 #define SMU_GPIOPAD_S1__GPIO_S1__SHIFT 0x0 1027 #define SMU_GPIOPAD_S1__GPIO_S1_MASK 0x7FFFFFFFL 1028 //SMU_GPIOPAD_SCL_EN 1029 #define SMU_GPIOPAD_SCL_EN__GPIO_SCL_EN__SHIFT 0x0 1030 #define SMU_GPIOPAD_SCL_EN__GPIO_SCL_EN_MASK 0x7FFFFFFFL 1031 //SMU_GPIOPAD_SDA_EN 1032 #define SMU_GPIOPAD_SDA_EN__GPIO_SDA_EN__SHIFT 0x0 1033 #define SMU_GPIOPAD_SDA_EN__GPIO_SDA_EN_MASK 0x7FFFFFFFL 1034 //SMU_GPIOPAD_SCHMEN 1035 #define SMU_GPIOPAD_SCHMEN__GPIO_SCHMEN__SHIFT 0x0 1036 #define SMU_GPIOPAD_SCHMEN__GPIO_SCHMEN_MASK 0x7FFFFFFFL 1037 1038 1039 // addressBlock: smuio_smuio_pwr_SmuSmuioDec 1040 //IP_DISCOVERY_VERSION 1041 #define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION__SHIFT 0x0 1042 #define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION_MASK 0xFFFFFFFFL 1043 //SOC_GAP_PWROK 1044 #define SOC_GAP_PWROK__soc_gap_pwrok__SHIFT 0x0 1045 #define SOC_GAP_PWROK__soc_gap_pwrok_MASK 0x00000001L 1046 //GFX_GAP_PWROK 1047 #define GFX_GAP_PWROK__gfx_gap_pwrok__SHIFT 0x0 1048 #define GFX_GAP_PWROK__gfx_gap_pwrok_MASK 0x00000001L 1049 //PWROK_REFCLK_GAP_CYCLES 1050 #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles__SHIFT 0x0 1051 #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles__SHIFT 0x8 1052 #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles_MASK 0x000000FFL 1053 #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles_MASK 0x0000FF00L 1054 //GOLDEN_TSC_INCREMENT_UPPER 1055 #define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper__SHIFT 0x0 1056 #define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper_MASK 0x00FFFFFFL 1057 //GOLDEN_TSC_INCREMENT_LOWER 1058 #define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower__SHIFT 0x0 1059 #define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower_MASK 0xFFFFFFFFL 1060 //GOLDEN_TSC_COUNT_UPPER 1061 #define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper__SHIFT 0x0 1062 #define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper_MASK 0x00FFFFFFL 1063 //GOLDEN_TSC_COUNT_LOWER 1064 #define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower__SHIFT 0x0 1065 #define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower_MASK 0xFFFFFFFFL 1066 //SOC_GOLDEN_TSC_SHADOW_UPPER 1067 #define SOC_GOLDEN_TSC_SHADOW_UPPER__SOCGoldenTscShadowUpper__SHIFT 0x0 1068 #define SOC_GOLDEN_TSC_SHADOW_UPPER__SOCGoldenTscShadowUpper_MASK 0x00FFFFFFL 1069 //SOC_GOLDEN_TSC_SHADOW_LOWER 1070 #define SOC_GOLDEN_TSC_SHADOW_LOWER__SOCGoldenTscShadowLower__SHIFT 0x0 1071 #define SOC_GOLDEN_TSC_SHADOW_LOWER__SOCGoldenTscShadowLower_MASK 0xFFFFFFFFL 1072 //GFX_GOLDEN_TSC_SHADOW_UPPER 1073 #define GFX_GOLDEN_TSC_SHADOW_UPPER__GFXGoldenTscShadowUpper__SHIFT 0x0 1074 #define GFX_GOLDEN_TSC_SHADOW_UPPER__GFXGoldenTscShadowUpper_MASK 0x00FFFFFFL 1075 //GFX_GOLDEN_TSC_SHADOW_LOWER 1076 #define GFX_GOLDEN_TSC_SHADOW_LOWER__GFXGoldenTscShadowLower__SHIFT 0x0 1077 #define GFX_GOLDEN_TSC_SHADOW_LOWER__GFXGoldenTscShadowLower_MASK 0xFFFFFFFFL 1078 //SCRATCH_REGISTER0 1079 #define SCRATCH_REGISTER0__ScratchPad0__SHIFT 0x0 1080 #define SCRATCH_REGISTER0__ScratchPad0_MASK 0xFFFFFFFFL 1081 //SCRATCH_REGISTER1 1082 #define SCRATCH_REGISTER1__ScratchPad1__SHIFT 0x0 1083 #define SCRATCH_REGISTER1__ScratchPad1_MASK 0xFFFFFFFFL 1084 //SCRATCH_REGISTER2 1085 #define SCRATCH_REGISTER2__ScratchPad2__SHIFT 0x0 1086 #define SCRATCH_REGISTER2__ScratchPad2_MASK 0xFFFFFFFFL 1087 //SCRATCH_REGISTER3 1088 #define SCRATCH_REGISTER3__ScratchPad3__SHIFT 0x0 1089 #define SCRATCH_REGISTER3__ScratchPad3_MASK 0xFFFFFFFFL 1090 //SCRATCH_REGISTER4 1091 #define SCRATCH_REGISTER4__ScratchPad4__SHIFT 0x0 1092 #define SCRATCH_REGISTER4__ScratchPad4_MASK 0xFFFFFFFFL 1093 //SCRATCH_REGISTER5 1094 #define SCRATCH_REGISTER5__ScratchPad5__SHIFT 0x0 1095 #define SCRATCH_REGISTER5__ScratchPad5_MASK 0xFFFFFFFFL 1096 //SCRATCH_REGISTER6 1097 #define SCRATCH_REGISTER6__ScratchPad6__SHIFT 0x0 1098 #define SCRATCH_REGISTER6__ScratchPad6_MASK 0xFFFFFFFFL 1099 //SCRATCH_REGISTER7 1100 #define SCRATCH_REGISTER7__ScratchPad7__SHIFT 0x0 1101 #define SCRATCH_REGISTER7__ScratchPad7_MASK 0xFFFFFFFFL 1102 //PWR_DISP_TIMER_CONTROL 1103 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 1104 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 1105 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a 1106 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b 1107 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c 1108 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d 1109 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e 1110 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x01FFFFFFL 1111 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x02000000L 1112 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x04000000L 1113 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK_MASK 0x08000000L 1114 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000L 1115 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000L 1116 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000L 1117 //PWR_DISP_TIMER_DEBUG 1118 #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_RUNNING__SHIFT 0x0 1119 #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_STAT__SHIFT 0x1 1120 #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT__SHIFT 0x2 1121 #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_RUN_VAL__SHIFT 0x7 1122 #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_RUNNING_MASK 0x00000001L 1123 #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_STAT_MASK 0x00000002L 1124 #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_MASK 0x00000004L 1125 #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_RUN_VAL_MASK 0xFFFFFF80L 1126 //PWR_DISP_TIMER2_CONTROL 1127 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 1128 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 1129 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a 1130 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b 1131 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c 1132 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d 1133 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e 1134 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x01FFFFFFL 1135 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x02000000L 1136 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x04000000L 1137 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK_MASK 0x08000000L 1138 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000L 1139 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000L 1140 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000L 1141 //PWR_DISP_TIMER2_DEBUG 1142 #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_RUNNING__SHIFT 0x0 1143 #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_STAT__SHIFT 0x1 1144 #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT__SHIFT 0x2 1145 #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_RUN_VAL__SHIFT 0x7 1146 #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_RUNNING_MASK 0x00000001L 1147 #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_STAT_MASK 0x00000002L 1148 #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_MASK 0x00000004L 1149 #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_RUN_VAL_MASK 0xFFFFFF80L 1150 //PWR_DISP_TIMER_GLOBAL_CONTROL 1151 #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH__SHIFT 0x0 1152 #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN__SHIFT 0xa 1153 #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH_MASK 0x000003FFL 1154 #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN_MASK 0x00000400L 1155 //PWR_IH_CONTROL 1156 #define PWR_IH_CONTROL__MAX_CREDIT__SHIFT 0x0 1157 #define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK__SHIFT 0x5 1158 #define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK__SHIFT 0x6 1159 #define PWR_IH_CONTROL__MAX_CREDIT_MASK 0x0000001FL 1160 #define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK_MASK 0x00000020L 1161 #define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK_MASK 0x00000040L 1162 1163 #endif 1164