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Searched refs:CACHE_EVENT_ATTR (Results 1 – 5 of 5) sorted by relevance

/linux-6.1.9/arch/powerpc/perf/
Dpower8-pmu.c133 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1);
134 CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1);
136 CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_L1_PREF);
137 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
138 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
139 CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1);
140 CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_WRITE);
142 CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS);
143 CACHE_EVENT_ATTR(LLC-loads, PM_DATA_FROM_L3);
144 CACHE_EVENT_ATTR(LLC-prefetches, PM_L3_PREF_ALL);
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Dpower9-pmu.c177 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1_FIN);
178 CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1);
179 CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_L1_PREF);
180 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
181 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
182 CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1);
183 CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_WRITE);
184 CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS);
185 CACHE_EVENT_ATTR(LLC-loads, PM_DATA_FROM_L3);
186 CACHE_EVENT_ATTR(LLC-prefetches, PM_L3_PREF_ALL);
[all …]
Dpower10-pmu.c133 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1);
134 CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1);
135 CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_LD_PREFETCH_CACHE_LINE_MISS);
136 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
137 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
138 CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1);
139 CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_REQ);
140 CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS);
141 CACHE_EVENT_ATTR(LLC-loads, PM_DATA_FROM_L3);
142 CACHE_EVENT_ATTR(LLC-prefetches, PM_L3_PF_MISS_L3);
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Dgeneric-compat-pmu.c109 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1);
110 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
111 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
112 CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS);
113 CACHE_EVENT_ATTR(branch-load-misses, PM_BR_MPRED_CMPL);
114 CACHE_EVENT_ATTR(dTLB-load-misses, PM_DTLB_MISS);
115 CACHE_EVENT_ATTR(iTLB-load-misses, PM_ITLB_MISS);
/linux-6.1.9/arch/powerpc/include/asm/
Dperf_event_server.h180 #define CACHE_EVENT_ATTR(_name, _id) EVENT_ATTR(_name, _id, _c) macro