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Searched refs:BIT8 (Results 1 – 18 of 18) sorted by relevance

/linux-6.1.9/drivers/staging/rtl8723bs/include/
Drtl8723b_spec.h206 #define IMR_CPWM_8723B BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */
235 #define IMR_RXFOVW_8723B BIT8 /* Receive FIFO Overflow */
Dosdep_service.h25 #define BIT8 0x00000100 macro
Dhal_com_reg.h555 #define RRSR_24M BIT8
707 #define IMR_HIGHDOK BIT8 /* High Queue DMA OK Interrupt */
723 #define IMR_CPWM BIT8
754 #define RCR_ACRC32 BIT8 /* Accept CRC32 error packet */
Drtw_mlme_ext.h52 #define DYNAMIC_BB_PWR_TRAIN BIT8 /* ODM_BB_PWR_TRAIN */
/linux-6.1.9/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_hw.h220 #define IMR_HIGHDOK BIT8
239 #define TPPoll_HCCAQ BIT8
369 #define RRSR_24M BIT8
/linux-6.1.9/drivers/net/wireless/realtek/rtlwifi/btcoexist/
Dhalbt_precomp.h39 #define BIT8 0x00000100 macro
Dhalbtcoutsrc.h100 #define ALGO_TRACE_SW_DETAIL BIT8
/linux-6.1.9/drivers/staging/rtl8723bs/hal/
DHal8723BReg.h395 #define IMR_CPWM_8723B BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */
424 #define IMR_RXFOVW_8723B BIT8 /* Receive FIFO Overflow */
Drtl8723b_phycfg.c133 RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1|MaskforPhySet, BIT8); in phy_RFSerialRead_8723B()
135 RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1|MaskforPhySet, BIT8); in phy_RFSerialRead_8723B()
Dodm.h373 ODM_BB_PWR_TRAIN = BIT8,
399 ODM_RTL8723B = BIT8,
Dodm_DIG.c22 …PHY_SetBBReg(pDM_Odm->Adapter, ODM_REG_NHM_TH9_TH10_11N, BIT10|BIT9|BIT8, 0x7); /* 0x890[9:8]=3 … in odm_NHMCounterStatisticsInit()
/linux-6.1.9/drivers/staging/rtl8192e/
Drtl819x_Qos.h18 #define BIT8 0x00000100 macro
/linux-6.1.9/include/uapi/linux/
Dsynclink.h27 #define BIT8 0x0100 macro
/linux-6.1.9/drivers/scsi/
Ddc395x.h68 #define BIT8 0x00000100 macro
/linux-6.1.9/drivers/tty/
Dsynclink_gt.c389 #define IRQ_RXOVER BIT8
2284 if (gsr & (BIT8 << i)) in slgt_interrupt()
4051 val |= BIT8; in async_mode()
4091 val |= BIT8; in async_mode()
4140 if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate && in async_mode()
4213 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; in sync_mode()
4286 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; in sync_mode()
4929 if (!(*(src+1) & (BIT9 + BIT8))) { in loopback_test_rx()
/linux-6.1.9/drivers/net/wireless/realtek/rtlwifi/rtl8192de/
Dreg.h366 #define RRSR_24M BIT8
/linux-6.1.9/drivers/scsi/lpfc/
Dlpfc_hw4.h777 #define LPFC_SLI4_INTR8 BIT8
/linux-6.1.9/drivers/char/pcmcia/
Dsynclink_cs.c297 #define IRQ_TXFIFO BIT8 // transmit pool ready