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Searched refs:BIT5 (Results 1 – 25 of 35) sorted by relevance

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/linux-6.1.9/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_hw.h100 #define EPROM_CMD_RESERVED_MASK BIT5
130 #define RCR_FILTER_MASK (BIT0 | BIT1 | BIT2 | BIT3 | BIT5 | BIT12 | \
145 #define RCR_ACRC32 BIT5
182 #define CAM_USEDK BIT5
206 #define SCR_NoSKMC BIT5
223 #define IMR_HCCADOK BIT5
236 #define TPPoll_CQ BIT5
276 #define AcmHw_ViqStatus BIT5
366 #define RRSR_9M BIT5
/linux-6.1.9/drivers/scsi/
Ddc395x.h71 #define BIT5 0x00000020 macro
134 #define SRB_ERROR BIT5
139 #define RESIDUAL_VALID BIT5
170 #define EN_TAG_QUEUEING BIT5
597 #define LUN_CHECK BIT5
/linux-6.1.9/drivers/staging/rtl8723bs/include/
Dhal_pwr_seq.h47 …MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b…
76 …, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b…
151 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK …
182 …, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*reset dual TS…
Drtl8723b_spec.h170 #define BIT_BCN_PORT_SEL BIT5
209 #define IMR_BKDOK_8723B BIT5 /* AC_BK DMA OK */
Dhal_com_reg.h525 #define HSISR_SPS_OCP_INT BIT5
552 #define RRSR_9M BIT5
646 #define CAM_USEDK BIT5
710 #define IMR_TBDER BIT5 /* For 92C, Transmit Beacon Error Interrupt */
758 #define RCR_APWRMGT BIT5 /* Accept power management packet */
1283 #define SDIO_HIMR_RXFOVW_MSK BIT5
1305 #define SDIO_HISR_RXFOVW BIT5
Dosdep_service.h22 #define BIT5 0x00000020 macro
/linux-6.1.9/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
Dpwrseq.h262 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
383 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0 \
416 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT5|BIT4), (BIT5|BIT4) \
466 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
619 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
/linux-6.1.9/drivers/video/fbdev/via/
Ddvi.c62 BIT5 + BIT6 + BIT7); in viafb_tmds_trasmitter_identify()
66 viafb_write_reg_mask(SR3E, VIASR, 0x0, BIT5); in viafb_tmds_trasmitter_identify()
396 viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + BIT5); in viafb_dvi_enable()
408 viafb_write_reg_mask(CR93, VIACR, 0x21, BIT0 + BIT5); in viafb_dvi_enable()
Dhw.c1696 viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5); in device_screen_off()
1702 viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5); in device_screen_on()
1713 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5); in set_display_channel()
1717 viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5); in set_display_channel()
1720 viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5); in set_display_channel()
1725 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5); in set_display_channel()
1728 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5); in set_display_channel()
2065 p_gfx_dpa_setting->DVP0DataDri_S1, BIT5); in viafb_set_dpa_gfx()
Dshare.h19 #define BIT5 0x20 macro
/linux-6.1.9/drivers/net/wireless/realtek/rtlwifi/btcoexist/
Dhalbt_precomp.h36 #define BIT5 0x00000020 macro
Dhalbtc8821a1ant.h10 #define BT_INFO_8821A_1ANT_B_HID BIT5
Dhalbtc8821a2ant.h10 #define BT_INFO_8821A_2ANT_B_HID BIT5
Dhalbtc8192e2ant.h9 #define BT_INFO_8192E_2ANT_B_HID BIT5
Dhalbtc8723b2ant.h12 #define BT_INFO_8723B_2ANT_B_HID BIT5
Dhalbtc8723b1ant.h9 #define BT_INFO_8723B_1ANT_B_HID BIT5
/linux-6.1.9/drivers/staging/rtl8192e/
Drtl819x_Qos.h15 #define BIT5 0x00000020 macro
/linux-6.1.9/drivers/staging/rtl8723bs/hal/
DHalBtc8723b2Ant.h10 #define BT_INFO_8723B_2ANT_B_HID BIT5
DHalBtc8723b1Ant.h10 #define BT_INFO_8723B_1ANT_B_HID BIT5
DHal8723BReg.h398 #define IMR_BKDOK_8723B BIT5 /* AC_BK DMA OK */
Dodm.h370 ODM_BB_CCK_PD = BIT5,
447 ODM_WM_AUTO = BIT5,
/linux-6.1.9/drivers/tty/
Dsynclink_gt.c392 #define IRQ_DCD BIT5
2134 if (status & (BIT5 + BIT4)) { in isr_rdma()
2159 if (status & (BIT5 + BIT4 + BIT3)) { in isr_tdma()
4057 case 7: val |= BIT5; break; in async_mode()
4058 case 8: val |= BIT5 + BIT4; break; in async_mode()
4097 case 7: val |= BIT5; break; in async_mode()
4098 case 8: val |= BIT5 + BIT4; break; in async_mode()
4221 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break; in sync_mode()
4223 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break; in sync_mode()
4309 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */ in sync_mode()
[all …]
/linux-6.1.9/include/uapi/linux/
Dsynclink.h24 #define BIT5 0x0020 macro
/linux-6.1.9/drivers/char/pcmcia/
Dsynclink_cs.c678 #define CMD_RXFIFO_READ BIT5
906 if (!fifo_count && (read_reg(info,CHA+STAR) & BIT5)) in rx_ready_async()
2994 val = read_reg(info, CHA + CCR2) | (BIT4 | BIT5); in loopback_enable()
3121 val |= BIT5; in hdlc_mode()
3146 val |= BIT5; in hdlc_mode()
3209 val |= BIT5; in hdlc_mode()
3483 val |= BIT5; in async_mode()
3526 val |= BIT5; in async_mode()
3651 else if (!(status & BIT5)) { in rx_get_frame()
3682 if (status & BIT5) in rx_get_frame()
[all …]
/linux-6.1.9/lib/zstd/common/
Dzstd_internal.h142 #define BIT5 32 macro

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