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Searched refs:BIT3 (Results 1 – 25 of 46) sorted by relevance

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/linux-6.1.9/drivers/staging/rtl8723bs/include/
Dhal_pwr_seq.h48 …PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0},/* disabl…
54 …PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disable WL …
63 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3},/*For GPIO9 int…
83 …AB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:…
84 …PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:1…
87 … PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04…
94 …{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3…
98 …{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3…
104 …PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:1…
114 …{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3…
[all …]
Drtw_ht.h67 #define LDPC_HT_CAP_TX BIT3
72 #define STBC_HT_CAP_TX BIT3
Dhal_com_reg.h550 #define RRSR_11M BIT3
575 #define HAL92C_WOL_DEAUTH_EVENT BIT3
673 #define WOW_UWF BIT3 /* Unicast Wakeup frame. */
712 #define IMR_BEDOK BIT3 /* AC_BE DMA OK Interrupt */
760 #define RCR_AB BIT3 /* Accept broadcast packet */
1281 #define SDIO_HIMR_RXERR_MSK BIT3
1303 #define SDIO_HISR_RXERR BIT3
1376 #define WL_HWROF_EN BIT3 /* Enable GPIO[9] as WiFi RF HW PDn source */
Drtl8723b_spec.h211 #define IMR_VIDOK_8723B BIT3 /* AC_VI DMA OK */
Dosdep_service.h20 #define BIT3 0x00000008 macro
/linux-6.1.9/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
Dpwrseq.h35 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \
105 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3 \
110 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \
176 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3 \
202 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \
386 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0 \
404 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3), 0 \
475 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3) \
479 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3 \
488 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4 \
[all …]
/linux-6.1.9/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_hw.h130 #define RCR_FILTER_MASK (BIT0 | BIT1 | BIT2 | BIT3 | BIT5 | BIT12 | \
146 #define RCR_AB BIT3
204 #define SCR_RxDecEnable BIT3
225 #define IMR_BEDOK BIT3
234 #define TPPoll_VOQ BIT3
274 #define AcmHw_VoqEn BIT3
364 #define RRSR_11M BIT3
/linux-6.1.9/drivers/scsi/
Ddc395x.h73 #define BIT3 0x00000008 macro
82 #define UNIT_RETRY BIT3
132 #define UNDER_RUN BIT3
168 #define WIDE_NEGO_DONE BIT3
595 #define ACTIVE_NEGATION BIT3
/linux-6.1.9/drivers/staging/rtl8723bs/hal/
Dodm_DynamicBBPowerSaving.c38 pDM_PSTable->RegC70 = (PHY_QueryBBReg(pDM_Odm->Adapter, 0xc70, bMaskDWord)&BIT3)>>3; in ODM_RF_Saving()
66 PHY_SetBBReg(pDM_Odm->Adapter, 0xc70, BIT3, 0); /* RegC70[3]= 1'b0 */ in ODM_RF_Saving()
74 PHY_SetBBReg(pDM_Odm->Adapter, 0xc70, BIT3, pDM_PSTable->RegC70); in ODM_RF_Saving()
DHalHWImg8723B_MAC.c17 ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA */ in CheckPositive()
62 if ((cond1 & BIT3) != 0) /* APA */ in CheckPositive()
DHalHWImg8723B_RF.c17 ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA */ in CheckPositive()
68 if ((cond1 & BIT3) != 0) /* APA */ in CheckPositive()
DHalHWImg8723B_BB.c17 ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA */ in CheckPositive()
63 if ((cond1 & BIT3) != 0) /* APA */ in CheckPositive()
DHalBtc8723b2Ant.h12 #define BT_INFO_8723B_2ANT_B_ACL_BUSY BIT3
DHalBtc8723b1Ant.h12 #define BT_INFO_8723B_1ANT_B_ACL_BUSY BIT3
/linux-6.1.9/drivers/video/fbdev/via/
Ddvi.c345 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp0()
370 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
377 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
456 viafb_write_reg_mask(CRD2, VIACR, 0, BIT3); in viafb_dvi_enable()
Dlcd.c420 viafb_write_reg_mask(CRA2, VIACR, 0x08, BIT3); in load_lcd_scaling()
432 viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT3); in load_lcd_scaling()
520 BIT0 + BIT1 + BIT2 + BIT3); in lcd_patch_skew()
615 viafb_write_reg_mask(CR6A, VIACR, 0, BIT3); in integrated_lvds_disable()
663 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3); in integrated_lvds_enable()
758 viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3); in viafb_lcd_enable()
759 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3); in viafb_lcd_enable()
Dshare.h17 #define BIT3 0x08 macro
/linux-6.1.9/drivers/net/wireless/realtek/rtlwifi/btcoexist/
Dhalbt_precomp.h34 #define BIT3 0x00000008 macro
Dhalbtc8821a1ant.h12 #define BT_INFO_8821A_1ANT_B_ACL_BUSY BIT3
Dhalbtc8821a2ant.h12 #define BT_INFO_8821A_2ANT_B_ACL_BUSY BIT3
Dhalbtc8192e2ant.h11 #define BT_INFO_8192E_2ANT_B_ACL_BUSY BIT3
Dhalbtc8723b2ant.h14 #define BT_INFO_8723B_2ANT_B_ACL_BUSY BIT3
Dhalbtc8723b1ant.h11 #define BT_INFO_8723B_1ANT_B_ACL_BUSY BIT3
/linux-6.1.9/drivers/staging/rtl8192e/
Drtl819x_Qos.h13 #define BIT3 0x00000008 macro
/linux-6.1.9/drivers/char/pcmcia/
Dsynclink_cs.c314 #define PVR_AUTOCTS BIT3
680 #define CMD_TXFIFO BIT3 // release current tx FIFO
1190 if (gis & (BIT3 | BIT2)) in mgslpc_isr()
3078 val |= BIT3; in hdlc_mode()
3087 val |= BIT4 | BIT3; in hdlc_mode()
3218 set_reg_bits(info, CHA + PVR, BIT3); in hdlc_mode()
3220 clear_reg_bits(info, CHA + PVR, BIT3); in hdlc_mode()
3255 clear_reg_bits(info, CHA + MODE, BIT3); in rx_stop()
3272 set_reg_bits(info, CHA + MODE, BIT3); in rx_start()
3488 val |= BIT3; in async_mode()
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