Searched refs:BAR0 (Results 1 – 16 of 16) sorted by relevance
| /linux-6.1.9/sound/pci/lola/ |
| D | lola.c | 93 lola_writew(chip, BAR0, CORBWP, wp); in corb_send_verb()
114 wp = lola_readw(chip, BAR0, RIRBWP); in lola_update_rirb()
264 rbsts = lola_readb(chip, BAR0, RIRBSTS); in lola_interrupt()
267 lola_writeb(chip, BAR0, RIRBSTS, rbsts); in lola_interrupt()
268 rbsts = lola_readb(chip, BAR0, CORBSTS); in lola_interrupt()
271 lola_writeb(chip, BAR0, CORBSTS, rbsts); in lola_interrupt()
297 unsigned int gctl = lola_readl(chip, BAR0, GCTL); in reset_controller()
307 lola_writel(chip, BAR0, GCTL, LOLA_GCTL_RESET); in reset_controller()
311 gctl = lola_readl(chip, BAR0, GCTL); in reset_controller()
361 lola_writeb(chip, BAR0, RIRBCTL, 0); in setup_corb_rirb()
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| D | lola_proc.c | 167 readl(chip->bar[BAR0].remap_addr + i)); in lola_proc_regs_read()
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| D | lola.h | 373 #define BAR0 0 macro
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| /linux-6.1.9/Documentation/scsi/ |
| D | hptiop.rst | 11 For RR44xx Intel IOP based adapters, the controller IOP is accessed via PCI BAR0 and BAR2
14 BAR0 offset Register
36 For Intel IOP based adapters, the controller IOP is accessed via PCI BAR0:
39 BAR0 offset Register
54 For Marvell not Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1:
57 BAR0 offset Register
78 For Marvell Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1:
81 BAR0 offset Register
119 relative to the IOP BAR0.
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| D | ChangeLog.lpfc | 1085 CONFIG_PORT uses HBA's view of its BAR0.
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| /linux-6.1.9/Documentation/PCI/endpoint/ |
| D | pci-vntb-function.rst | 108 BAR0 Config Region
121 BAR0 Config Region + Scratchpad
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| D | pci-test-function.rst | 33 This register will be used to test BAR0. A known pattern will be written
34 and read back from MAGIC register to verify BAR0.
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| D | pci-ntb-function.rst | 239 BAR0 Config Region
261 BAR0 Config Region + Self Scratchpad
277 | BAR0 | | CONFIG REGION | | BAR0 |
293 region and scratchpad region (self scratchpad) using BAR0 of EP controller 1.
305 | BAR0 | | | Doorbell 1 +-----------> MSI-X ADDRESS 1 |
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| D | pci-test-howto.rst | 147 BAR0: OKAY
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| /linux-6.1.9/Documentation/misc-devices/ |
| D | spear-pcie-gadget.rst | 98 program BAR0 size as 1MB::
106 Program BAR0 Address as DDR (0x2100000). This is the physical address of
109 as BAR0 address then when this device will be connected to a host, it will be
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| /linux-6.1.9/drivers/ntb/hw/idt/ |
| D | Kconfig | 21 accepted by a BAR. Note that BAR0 must map PCI configuration space
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| /linux-6.1.9/drivers/net/ethernet/cavium/liquidio/ |
| D | cn23xx_pf_device.c | 1312 u64 BAR0, BAR1; in setup_cn23xx_octeon_pf_device() local
1315 BAR0 = (u64)(data32 & ~0xf); in setup_cn23xx_octeon_pf_device()
1317 BAR0 |= ((u64)data32 << 32); in setup_cn23xx_octeon_pf_device()
1323 if (!BAR0 || !BAR1) { in setup_cn23xx_octeon_pf_device()
1324 if (!BAR0) in setup_cn23xx_octeon_pf_device()
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| /linux-6.1.9/Documentation/networking/device_drivers/ethernet/huawei/ |
| D | hinic.rst | 50 configuration and status BAR0. (hinic_hw_csr.h)
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| /linux-6.1.9/arch/arm64/boot/dts/freescale/ |
| D | fsl-ls1028a.dtsi | 1069 /* PF0-6 BAR0 - non-prefetchable memory */
1073 /* PF0: VF0-1 BAR0 - non-prefetchable memory */
1077 /* PF1: VF0-1 BAR0 - non-prefetchable memory */
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| /linux-6.1.9/Documentation/powerpc/ |
| D | pci_iov_resource_on_powernv.rst | 180 1MB VF BAR0, the address in that VF BAR sets the base of an 8MB region.
182 is a BAR0 for one of the VFs. Note that even though the VF BAR
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| /linux-6.1.9/Documentation/driver-api/media/drivers/ |
| D | cx2341x-devel.rst | 31 The cx2341x exposes its entire 64M memory space to the PCI host via the PCI BAR0
33 address held in BAR0.
54 The registers occupy the 64k space starting at the 0x02000000 offset from BAR0.
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