Searched refs:AR_PHY_GC_DYN2040_PRI_CH (Results 1 – 2 of 2) sorted by relevance
260 AR_PHY_GC_DYN2040_PRI_CH) == 0) in ar9003_hw_spur_mitigate_mrc_cck()482 AR_PHY_GC_DYN2040_PRI_CH) == 0x0) in ar9003_hw_spur_ofdm_work()491 AR_PHY_GC_DYN2040_PRI_CH) == 0x0) in ar9003_hw_spur_ofdm_work()535 AR_PHY_GC_DYN2040_PRI_CH) == 0x0) in ar9003_hw_spur_mitigate_ofdm()630 phymode |= AR_PHY_GC_DYN2040_PRI_CH; in ar9003_hw_set_channel_regs()
777 #define AR_PHY_GC_DYN2040_PRI_CH 0x00000010 /* dyn 20/40 - primary ch offset (0=+10MHz, 1=-10MHz… macro