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Searched refs:AR934X_PLL_DDR_CONFIG_REG (Results 1 – 2 of 2) sorted by relevance

/linux-6.1.9/arch/mips/ath79/
Dclock.c292 pll = __raw_readl(pll_base + AR934X_PLL_DDR_CONFIG_REG); in ar934x_clocks_init()
/linux-6.1.9/arch/mips/include/asm/mach-ath79/
Dar71xx_regs.h314 #define AR934X_PLL_DDR_CONFIG_REG 0x04 macro