Searched refs:AR71XX_RESET_REG_MISC_INT_ENABLE (Results 1 – 3 of 3) sorted by relevance
19 #define AR71XX_RESET_REG_MISC_INT_ENABLE 4 macro42 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ath79_misc_irq_handler()66 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_unmask()67 __raw_writel(t | BIT(irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_unmask()70 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_unmask()79 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_mask()80 __raw_writel(t & ~BIT(irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_mask()83 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_mask()125 __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ath79_misc_intc_domain_init()
532 misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE); in qca956x_clocks_init()534 ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc); in qca956x_clocks_init()
517 #define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 macro