Searched refs:AR5K_DCU_GBL_IFS_MISC (Results 1 – 4 of 4) sorted by relevance
669 AR5K_REG_WRITE_BITS(ah, AR5K_DCU_GBL_IFS_MISC, in ath5k_hw_set_ifs_intervals()717 AR5K_REG_ENABLE_BITS(ah, AR5K_DCU_GBL_IFS_MISC, in ath5k_hw_init_queues()
425 { AR5K_DCU_GBL_IFS_MISC,707 { AR5K_DCU_GBL_IFS_MISC,
181 AR5K_REG_WRITE_BITS(ah, AR5K_DCU_GBL_IFS_MISC, in ath5k_hw_init_core_clock()
800 #define AR5K_DCU_GBL_IFS_MISC 0x10f0 /* Register Address */ macro