1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 3 /* This file is autogenerated by cml-utils 2021-10-10 13:25:08 +0200. 4 * Commit ID: 26db2002924973d36a30b369c94f025a678fe9ea (dirty) 5 */ 6 7 #ifndef _LAN966X_REGS_H_ 8 #define _LAN966X_REGS_H_ 9 10 #include <linux/bitfield.h> 11 #include <linux/types.h> 12 #include <linux/bug.h> 13 14 enum lan966x_target { 15 TARGET_AFI = 2, 16 TARGET_ANA = 3, 17 TARGET_CHIP_TOP = 5, 18 TARGET_CPU = 6, 19 TARGET_DEV = 13, 20 TARGET_FDMA = 21, 21 TARGET_GCB = 27, 22 TARGET_ORG = 36, 23 TARGET_PTP = 41, 24 TARGET_QS = 42, 25 TARGET_QSYS = 46, 26 TARGET_REW = 47, 27 TARGET_SYS = 52, 28 NUM_TARGETS = 66 29 }; 30 31 #define __REG(...) __VA_ARGS__ 32 33 /* AFI:PORT_TBL:PORT_FRM_OUT */ 34 #define AFI_PORT_FRM_OUT(g) __REG(TARGET_AFI, 0, 1, 98816, g, 10, 8, 0, 0, 1, 4) 35 36 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT GENMASK(26, 16) 37 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT_SET(x)\ 38 FIELD_PREP(AFI_PORT_FRM_OUT_FRM_OUT_CNT, x) 39 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT_GET(x)\ 40 FIELD_GET(AFI_PORT_FRM_OUT_FRM_OUT_CNT, x) 41 42 /* AFI:PORT_TBL:PORT_CFG */ 43 #define AFI_PORT_CFG(g) __REG(TARGET_AFI, 0, 1, 98816, g, 10, 8, 4, 0, 1, 4) 44 45 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ BIT(16) 46 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ_SET(x)\ 47 FIELD_PREP(AFI_PORT_CFG_FC_SKIP_TTI_INJ, x) 48 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ_GET(x)\ 49 FIELD_GET(AFI_PORT_CFG_FC_SKIP_TTI_INJ, x) 50 51 #define AFI_PORT_CFG_FRM_OUT_MAX GENMASK(9, 0) 52 #define AFI_PORT_CFG_FRM_OUT_MAX_SET(x)\ 53 FIELD_PREP(AFI_PORT_CFG_FRM_OUT_MAX, x) 54 #define AFI_PORT_CFG_FRM_OUT_MAX_GET(x)\ 55 FIELD_GET(AFI_PORT_CFG_FRM_OUT_MAX, x) 56 57 /* ANA:ANA:ADVLEARN */ 58 #define ANA_ADVLEARN __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 0, 0, 1, 4) 59 60 #define ANA_ADVLEARN_VLAN_CHK BIT(0) 61 #define ANA_ADVLEARN_VLAN_CHK_SET(x)\ 62 FIELD_PREP(ANA_ADVLEARN_VLAN_CHK, x) 63 #define ANA_ADVLEARN_VLAN_CHK_GET(x)\ 64 FIELD_GET(ANA_ADVLEARN_VLAN_CHK, x) 65 66 /* ANA:ANA:VLANMASK */ 67 #define ANA_VLANMASK __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 8, 0, 1, 4) 68 69 /* ANA:ANA:ANAINTR */ 70 #define ANA_ANAINTR __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 16, 0, 1, 4) 71 72 #define ANA_ANAINTR_INTR BIT(1) 73 #define ANA_ANAINTR_INTR_SET(x)\ 74 FIELD_PREP(ANA_ANAINTR_INTR, x) 75 #define ANA_ANAINTR_INTR_GET(x)\ 76 FIELD_GET(ANA_ANAINTR_INTR, x) 77 78 #define ANA_ANAINTR_INTR_ENA BIT(0) 79 #define ANA_ANAINTR_INTR_ENA_SET(x)\ 80 FIELD_PREP(ANA_ANAINTR_INTR_ENA, x) 81 #define ANA_ANAINTR_INTR_ENA_GET(x)\ 82 FIELD_GET(ANA_ANAINTR_INTR_ENA, x) 83 84 /* ANA:ANA:AUTOAGE */ 85 #define ANA_AUTOAGE __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 44, 0, 1, 4) 86 87 #define ANA_AUTOAGE_AGE_PERIOD GENMASK(20, 1) 88 #define ANA_AUTOAGE_AGE_PERIOD_SET(x)\ 89 FIELD_PREP(ANA_AUTOAGE_AGE_PERIOD, x) 90 #define ANA_AUTOAGE_AGE_PERIOD_GET(x)\ 91 FIELD_GET(ANA_AUTOAGE_AGE_PERIOD, x) 92 93 /* ANA:ANA:MIRRORPORTS */ 94 #define ANA_MIRRORPORTS __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 60, 0, 1, 4) 95 96 #define ANA_MIRRORPORTS_MIRRORPORTS GENMASK(8, 0) 97 #define ANA_MIRRORPORTS_MIRRORPORTS_SET(x)\ 98 FIELD_PREP(ANA_MIRRORPORTS_MIRRORPORTS, x) 99 #define ANA_MIRRORPORTS_MIRRORPORTS_GET(x)\ 100 FIELD_GET(ANA_MIRRORPORTS_MIRRORPORTS, x) 101 102 /* ANA:ANA:EMIRRORPORTS */ 103 #define ANA_EMIRRORPORTS __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 64, 0, 1, 4) 104 105 #define ANA_EMIRRORPORTS_EMIRRORPORTS GENMASK(8, 0) 106 #define ANA_EMIRRORPORTS_EMIRRORPORTS_SET(x)\ 107 FIELD_PREP(ANA_EMIRRORPORTS_EMIRRORPORTS, x) 108 #define ANA_EMIRRORPORTS_EMIRRORPORTS_GET(x)\ 109 FIELD_GET(ANA_EMIRRORPORTS_EMIRRORPORTS, x) 110 111 /* ANA:ANA:FLOODING */ 112 #define ANA_FLOODING(r) __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 68, r, 8, 4) 113 114 #define ANA_FLOODING_FLD_UNICAST GENMASK(17, 12) 115 #define ANA_FLOODING_FLD_UNICAST_SET(x)\ 116 FIELD_PREP(ANA_FLOODING_FLD_UNICAST, x) 117 #define ANA_FLOODING_FLD_UNICAST_GET(x)\ 118 FIELD_GET(ANA_FLOODING_FLD_UNICAST, x) 119 120 #define ANA_FLOODING_FLD_BROADCAST GENMASK(11, 6) 121 #define ANA_FLOODING_FLD_BROADCAST_SET(x)\ 122 FIELD_PREP(ANA_FLOODING_FLD_BROADCAST, x) 123 #define ANA_FLOODING_FLD_BROADCAST_GET(x)\ 124 FIELD_GET(ANA_FLOODING_FLD_BROADCAST, x) 125 126 #define ANA_FLOODING_FLD_MULTICAST GENMASK(5, 0) 127 #define ANA_FLOODING_FLD_MULTICAST_SET(x)\ 128 FIELD_PREP(ANA_FLOODING_FLD_MULTICAST, x) 129 #define ANA_FLOODING_FLD_MULTICAST_GET(x)\ 130 FIELD_GET(ANA_FLOODING_FLD_MULTICAST, x) 131 132 /* ANA:ANA:FLOODING_IPMC */ 133 #define ANA_FLOODING_IPMC __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 100, 0, 1, 4) 134 135 #define ANA_FLOODING_IPMC_FLD_MC4_CTRL GENMASK(23, 18) 136 #define ANA_FLOODING_IPMC_FLD_MC4_CTRL_SET(x)\ 137 FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC4_CTRL, x) 138 #define ANA_FLOODING_IPMC_FLD_MC4_CTRL_GET(x)\ 139 FIELD_GET(ANA_FLOODING_IPMC_FLD_MC4_CTRL, x) 140 141 #define ANA_FLOODING_IPMC_FLD_MC4_DATA GENMASK(17, 12) 142 #define ANA_FLOODING_IPMC_FLD_MC4_DATA_SET(x)\ 143 FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC4_DATA, x) 144 #define ANA_FLOODING_IPMC_FLD_MC4_DATA_GET(x)\ 145 FIELD_GET(ANA_FLOODING_IPMC_FLD_MC4_DATA, x) 146 147 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL GENMASK(11, 6) 148 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_SET(x)\ 149 FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC6_CTRL, x) 150 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_GET(x)\ 151 FIELD_GET(ANA_FLOODING_IPMC_FLD_MC6_CTRL, x) 152 153 #define ANA_FLOODING_IPMC_FLD_MC6_DATA GENMASK(5, 0) 154 #define ANA_FLOODING_IPMC_FLD_MC6_DATA_SET(x)\ 155 FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC6_DATA, x) 156 #define ANA_FLOODING_IPMC_FLD_MC6_DATA_GET(x)\ 157 FIELD_GET(ANA_FLOODING_IPMC_FLD_MC6_DATA, x) 158 159 /* ANA:PGID:PGID */ 160 #define ANA_PGID(g) __REG(TARGET_ANA, 0, 1, 27648, g, 89, 8, 0, 0, 1, 4) 161 162 #define ANA_PGID_PGID GENMASK(8, 0) 163 #define ANA_PGID_PGID_SET(x)\ 164 FIELD_PREP(ANA_PGID_PGID, x) 165 #define ANA_PGID_PGID_GET(x)\ 166 FIELD_GET(ANA_PGID_PGID, x) 167 168 /* ANA:PGID:PGID_CFG */ 169 #define ANA_PGID_CFG(g) __REG(TARGET_ANA, 0, 1, 27648, g, 89, 8, 4, 0, 1, 4) 170 171 #define ANA_PGID_CFG_OBEY_VLAN BIT(0) 172 #define ANA_PGID_CFG_OBEY_VLAN_SET(x)\ 173 FIELD_PREP(ANA_PGID_CFG_OBEY_VLAN, x) 174 #define ANA_PGID_CFG_OBEY_VLAN_GET(x)\ 175 FIELD_GET(ANA_PGID_CFG_OBEY_VLAN, x) 176 177 /* ANA:ANA_TABLES:MACHDATA */ 178 #define ANA_MACHDATA __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 40, 0, 1, 4) 179 180 /* ANA:ANA_TABLES:MACLDATA */ 181 #define ANA_MACLDATA __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 44, 0, 1, 4) 182 183 /* ANA:ANA_TABLES:MACACCESS */ 184 #define ANA_MACACCESS __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 48, 0, 1, 4) 185 186 #define ANA_MACACCESS_CHANGE2SW BIT(17) 187 #define ANA_MACACCESS_CHANGE2SW_SET(x)\ 188 FIELD_PREP(ANA_MACACCESS_CHANGE2SW, x) 189 #define ANA_MACACCESS_CHANGE2SW_GET(x)\ 190 FIELD_GET(ANA_MACACCESS_CHANGE2SW, x) 191 192 #define ANA_MACACCESS_MAC_CPU_COPY BIT(16) 193 #define ANA_MACACCESS_MAC_CPU_COPY_SET(x)\ 194 FIELD_PREP(ANA_MACACCESS_MAC_CPU_COPY, x) 195 #define ANA_MACACCESS_MAC_CPU_COPY_GET(x)\ 196 FIELD_GET(ANA_MACACCESS_MAC_CPU_COPY, x) 197 198 #define ANA_MACACCESS_VALID BIT(12) 199 #define ANA_MACACCESS_VALID_SET(x)\ 200 FIELD_PREP(ANA_MACACCESS_VALID, x) 201 #define ANA_MACACCESS_VALID_GET(x)\ 202 FIELD_GET(ANA_MACACCESS_VALID, x) 203 204 #define ANA_MACACCESS_ENTRYTYPE GENMASK(11, 10) 205 #define ANA_MACACCESS_ENTRYTYPE_SET(x)\ 206 FIELD_PREP(ANA_MACACCESS_ENTRYTYPE, x) 207 #define ANA_MACACCESS_ENTRYTYPE_GET(x)\ 208 FIELD_GET(ANA_MACACCESS_ENTRYTYPE, x) 209 210 #define ANA_MACACCESS_DEST_IDX GENMASK(9, 4) 211 #define ANA_MACACCESS_DEST_IDX_SET(x)\ 212 FIELD_PREP(ANA_MACACCESS_DEST_IDX, x) 213 #define ANA_MACACCESS_DEST_IDX_GET(x)\ 214 FIELD_GET(ANA_MACACCESS_DEST_IDX, x) 215 216 #define ANA_MACACCESS_MAC_TABLE_CMD GENMASK(3, 0) 217 #define ANA_MACACCESS_MAC_TABLE_CMD_SET(x)\ 218 FIELD_PREP(ANA_MACACCESS_MAC_TABLE_CMD, x) 219 #define ANA_MACACCESS_MAC_TABLE_CMD_GET(x)\ 220 FIELD_GET(ANA_MACACCESS_MAC_TABLE_CMD, x) 221 222 /* ANA:ANA_TABLES:MACTINDX */ 223 #define ANA_MACTINDX __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 52, 0, 1, 4) 224 225 #define ANA_MACTINDX_BUCKET GENMASK(12, 11) 226 #define ANA_MACTINDX_BUCKET_SET(x)\ 227 FIELD_PREP(ANA_MACTINDX_BUCKET, x) 228 #define ANA_MACTINDX_BUCKET_GET(x)\ 229 FIELD_GET(ANA_MACTINDX_BUCKET, x) 230 231 #define ANA_MACTINDX_M_INDEX GENMASK(10, 0) 232 #define ANA_MACTINDX_M_INDEX_SET(x)\ 233 FIELD_PREP(ANA_MACTINDX_M_INDEX, x) 234 #define ANA_MACTINDX_M_INDEX_GET(x)\ 235 FIELD_GET(ANA_MACTINDX_M_INDEX, x) 236 237 /* ANA:ANA_TABLES:VLAN_PORT_MASK */ 238 #define ANA_VLAN_PORT_MASK __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 56, 0, 1, 4) 239 240 #define ANA_VLAN_PORT_MASK_VLAN_PORT_MASK GENMASK(8, 0) 241 #define ANA_VLAN_PORT_MASK_VLAN_PORT_MASK_SET(x)\ 242 FIELD_PREP(ANA_VLAN_PORT_MASK_VLAN_PORT_MASK, x) 243 #define ANA_VLAN_PORT_MASK_VLAN_PORT_MASK_GET(x)\ 244 FIELD_GET(ANA_VLAN_PORT_MASK_VLAN_PORT_MASK, x) 245 246 /* ANA:ANA_TABLES:VLANACCESS */ 247 #define ANA_VLANACCESS __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 60, 0, 1, 4) 248 249 #define ANA_VLANACCESS_VLAN_TBL_CMD GENMASK(1, 0) 250 #define ANA_VLANACCESS_VLAN_TBL_CMD_SET(x)\ 251 FIELD_PREP(ANA_VLANACCESS_VLAN_TBL_CMD, x) 252 #define ANA_VLANACCESS_VLAN_TBL_CMD_GET(x)\ 253 FIELD_GET(ANA_VLANACCESS_VLAN_TBL_CMD, x) 254 255 /* ANA:ANA_TABLES:VLANTIDX */ 256 #define ANA_VLANTIDX __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 64, 0, 1, 4) 257 258 #define ANA_VLANTIDX_VLAN_PGID_CPU_DIS BIT(18) 259 #define ANA_VLANTIDX_VLAN_PGID_CPU_DIS_SET(x)\ 260 FIELD_PREP(ANA_VLANTIDX_VLAN_PGID_CPU_DIS, x) 261 #define ANA_VLANTIDX_VLAN_PGID_CPU_DIS_GET(x)\ 262 FIELD_GET(ANA_VLANTIDX_VLAN_PGID_CPU_DIS, x) 263 264 #define ANA_VLANTIDX_V_INDEX GENMASK(11, 0) 265 #define ANA_VLANTIDX_V_INDEX_SET(x)\ 266 FIELD_PREP(ANA_VLANTIDX_V_INDEX, x) 267 #define ANA_VLANTIDX_V_INDEX_GET(x)\ 268 FIELD_GET(ANA_VLANTIDX_V_INDEX, x) 269 270 /* ANA:PORT:VLAN_CFG */ 271 #define ANA_VLAN_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 0, 0, 1, 4) 272 273 #define ANA_VLAN_CFG_VLAN_AWARE_ENA BIT(20) 274 #define ANA_VLAN_CFG_VLAN_AWARE_ENA_SET(x)\ 275 FIELD_PREP(ANA_VLAN_CFG_VLAN_AWARE_ENA, x) 276 #define ANA_VLAN_CFG_VLAN_AWARE_ENA_GET(x)\ 277 FIELD_GET(ANA_VLAN_CFG_VLAN_AWARE_ENA, x) 278 279 #define ANA_VLAN_CFG_VLAN_POP_CNT GENMASK(19, 18) 280 #define ANA_VLAN_CFG_VLAN_POP_CNT_SET(x)\ 281 FIELD_PREP(ANA_VLAN_CFG_VLAN_POP_CNT, x) 282 #define ANA_VLAN_CFG_VLAN_POP_CNT_GET(x)\ 283 FIELD_GET(ANA_VLAN_CFG_VLAN_POP_CNT, x) 284 285 #define ANA_VLAN_CFG_VLAN_VID GENMASK(11, 0) 286 #define ANA_VLAN_CFG_VLAN_VID_SET(x)\ 287 FIELD_PREP(ANA_VLAN_CFG_VLAN_VID, x) 288 #define ANA_VLAN_CFG_VLAN_VID_GET(x)\ 289 FIELD_GET(ANA_VLAN_CFG_VLAN_VID, x) 290 291 /* ANA:PORT:DROP_CFG */ 292 #define ANA_DROP_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 4, 0, 1, 4) 293 294 #define ANA_DROP_CFG_DROP_UNTAGGED_ENA BIT(6) 295 #define ANA_DROP_CFG_DROP_UNTAGGED_ENA_SET(x)\ 296 FIELD_PREP(ANA_DROP_CFG_DROP_UNTAGGED_ENA, x) 297 #define ANA_DROP_CFG_DROP_UNTAGGED_ENA_GET(x)\ 298 FIELD_GET(ANA_DROP_CFG_DROP_UNTAGGED_ENA, x) 299 300 #define ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA BIT(3) 301 #define ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA_SET(x)\ 302 FIELD_PREP(ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA, x) 303 #define ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA_GET(x)\ 304 FIELD_GET(ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA, x) 305 306 #define ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA BIT(2) 307 #define ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA_SET(x)\ 308 FIELD_PREP(ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, x) 309 #define ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA_GET(x)\ 310 FIELD_GET(ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, x) 311 312 #define ANA_DROP_CFG_DROP_MC_SMAC_ENA BIT(0) 313 #define ANA_DROP_CFG_DROP_MC_SMAC_ENA_SET(x)\ 314 FIELD_PREP(ANA_DROP_CFG_DROP_MC_SMAC_ENA, x) 315 #define ANA_DROP_CFG_DROP_MC_SMAC_ENA_GET(x)\ 316 FIELD_GET(ANA_DROP_CFG_DROP_MC_SMAC_ENA, x) 317 318 /* ANA:PORT:CPU_FWD_CFG */ 319 #define ANA_CPU_FWD_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 96, 0, 1, 4) 320 321 #define ANA_CPU_FWD_CFG_MLD_REDIR_ENA BIT(6) 322 #define ANA_CPU_FWD_CFG_MLD_REDIR_ENA_SET(x)\ 323 FIELD_PREP(ANA_CPU_FWD_CFG_MLD_REDIR_ENA, x) 324 #define ANA_CPU_FWD_CFG_MLD_REDIR_ENA_GET(x)\ 325 FIELD_GET(ANA_CPU_FWD_CFG_MLD_REDIR_ENA, x) 326 327 #define ANA_CPU_FWD_CFG_IGMP_REDIR_ENA BIT(5) 328 #define ANA_CPU_FWD_CFG_IGMP_REDIR_ENA_SET(x)\ 329 FIELD_PREP(ANA_CPU_FWD_CFG_IGMP_REDIR_ENA, x) 330 #define ANA_CPU_FWD_CFG_IGMP_REDIR_ENA_GET(x)\ 331 FIELD_GET(ANA_CPU_FWD_CFG_IGMP_REDIR_ENA, x) 332 333 #define ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA BIT(4) 334 #define ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA_SET(x)\ 335 FIELD_PREP(ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA, x) 336 #define ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA_GET(x)\ 337 FIELD_GET(ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA, x) 338 339 #define ANA_CPU_FWD_CFG_SRC_COPY_ENA BIT(3) 340 #define ANA_CPU_FWD_CFG_SRC_COPY_ENA_SET(x)\ 341 FIELD_PREP(ANA_CPU_FWD_CFG_SRC_COPY_ENA, x) 342 #define ANA_CPU_FWD_CFG_SRC_COPY_ENA_GET(x)\ 343 FIELD_GET(ANA_CPU_FWD_CFG_SRC_COPY_ENA, x) 344 345 /* ANA:PORT:CPU_FWD_BPDU_CFG */ 346 #define ANA_CPU_FWD_BPDU_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 100, 0, 1, 4) 347 348 /* ANA:PORT:PORT_CFG */ 349 #define ANA_PORT_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 112, 0, 1, 4) 350 351 #define ANA_PORT_CFG_SRC_MIRROR_ENA BIT(13) 352 #define ANA_PORT_CFG_SRC_MIRROR_ENA_SET(x)\ 353 FIELD_PREP(ANA_PORT_CFG_SRC_MIRROR_ENA, x) 354 #define ANA_PORT_CFG_SRC_MIRROR_ENA_GET(x)\ 355 FIELD_GET(ANA_PORT_CFG_SRC_MIRROR_ENA, x) 356 357 #define ANA_PORT_CFG_LEARNAUTO BIT(6) 358 #define ANA_PORT_CFG_LEARNAUTO_SET(x)\ 359 FIELD_PREP(ANA_PORT_CFG_LEARNAUTO, x) 360 #define ANA_PORT_CFG_LEARNAUTO_GET(x)\ 361 FIELD_GET(ANA_PORT_CFG_LEARNAUTO, x) 362 363 #define ANA_PORT_CFG_LEARN_ENA BIT(5) 364 #define ANA_PORT_CFG_LEARN_ENA_SET(x)\ 365 FIELD_PREP(ANA_PORT_CFG_LEARN_ENA, x) 366 #define ANA_PORT_CFG_LEARN_ENA_GET(x)\ 367 FIELD_GET(ANA_PORT_CFG_LEARN_ENA, x) 368 369 #define ANA_PORT_CFG_RECV_ENA BIT(4) 370 #define ANA_PORT_CFG_RECV_ENA_SET(x)\ 371 FIELD_PREP(ANA_PORT_CFG_RECV_ENA, x) 372 #define ANA_PORT_CFG_RECV_ENA_GET(x)\ 373 FIELD_GET(ANA_PORT_CFG_RECV_ENA, x) 374 375 #define ANA_PORT_CFG_PORTID_VAL GENMASK(3, 0) 376 #define ANA_PORT_CFG_PORTID_VAL_SET(x)\ 377 FIELD_PREP(ANA_PORT_CFG_PORTID_VAL, x) 378 #define ANA_PORT_CFG_PORTID_VAL_GET(x)\ 379 FIELD_GET(ANA_PORT_CFG_PORTID_VAL, x) 380 381 /* ANA:PORT:POL_CFG */ 382 #define ANA_POL_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 116, 0, 1, 4) 383 384 #define ANA_POL_CFG_PORT_POL_ENA BIT(17) 385 #define ANA_POL_CFG_PORT_POL_ENA_SET(x)\ 386 FIELD_PREP(ANA_POL_CFG_PORT_POL_ENA, x) 387 #define ANA_POL_CFG_PORT_POL_ENA_GET(x)\ 388 FIELD_GET(ANA_POL_CFG_PORT_POL_ENA, x) 389 390 #define ANA_POL_CFG_POL_ORDER GENMASK(8, 0) 391 #define ANA_POL_CFG_POL_ORDER_SET(x)\ 392 FIELD_PREP(ANA_POL_CFG_POL_ORDER, x) 393 #define ANA_POL_CFG_POL_ORDER_GET(x)\ 394 FIELD_GET(ANA_POL_CFG_POL_ORDER, x) 395 396 /* ANA:PFC:PFC_CFG */ 397 #define ANA_PFC_CFG(g) __REG(TARGET_ANA, 0, 1, 30720, g, 8, 64, 0, 0, 1, 4) 398 399 #define ANA_PFC_CFG_FC_LINK_SPEED GENMASK(1, 0) 400 #define ANA_PFC_CFG_FC_LINK_SPEED_SET(x)\ 401 FIELD_PREP(ANA_PFC_CFG_FC_LINK_SPEED, x) 402 #define ANA_PFC_CFG_FC_LINK_SPEED_GET(x)\ 403 FIELD_GET(ANA_PFC_CFG_FC_LINK_SPEED, x) 404 405 /* ANA:COMMON:AGGR_CFG */ 406 #define ANA_AGGR_CFG __REG(TARGET_ANA, 0, 1, 31232, 0, 1, 552, 0, 0, 1, 4) 407 408 #define ANA_AGGR_CFG_AC_RND_ENA BIT(6) 409 #define ANA_AGGR_CFG_AC_RND_ENA_SET(x)\ 410 FIELD_PREP(ANA_AGGR_CFG_AC_RND_ENA, x) 411 #define ANA_AGGR_CFG_AC_RND_ENA_GET(x)\ 412 FIELD_GET(ANA_AGGR_CFG_AC_RND_ENA, x) 413 414 #define ANA_AGGR_CFG_AC_DMAC_ENA BIT(5) 415 #define ANA_AGGR_CFG_AC_DMAC_ENA_SET(x)\ 416 FIELD_PREP(ANA_AGGR_CFG_AC_DMAC_ENA, x) 417 #define ANA_AGGR_CFG_AC_DMAC_ENA_GET(x)\ 418 FIELD_GET(ANA_AGGR_CFG_AC_DMAC_ENA, x) 419 420 #define ANA_AGGR_CFG_AC_SMAC_ENA BIT(4) 421 #define ANA_AGGR_CFG_AC_SMAC_ENA_SET(x)\ 422 FIELD_PREP(ANA_AGGR_CFG_AC_SMAC_ENA, x) 423 #define ANA_AGGR_CFG_AC_SMAC_ENA_GET(x)\ 424 FIELD_GET(ANA_AGGR_CFG_AC_SMAC_ENA, x) 425 426 #define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA BIT(3) 427 #define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA_SET(x)\ 428 FIELD_PREP(ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA, x) 429 #define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA_GET(x)\ 430 FIELD_GET(ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA, x) 431 432 #define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA BIT(2) 433 #define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA_SET(x)\ 434 FIELD_PREP(ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA, x) 435 #define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA_GET(x)\ 436 FIELD_GET(ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA, x) 437 438 #define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA BIT(1) 439 #define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA_SET(x)\ 440 FIELD_PREP(ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA, x) 441 #define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA_GET(x)\ 442 FIELD_GET(ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA, x) 443 444 #define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA BIT(0) 445 #define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA_SET(x)\ 446 FIELD_PREP(ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, x) 447 #define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA_GET(x)\ 448 FIELD_GET(ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, x) 449 450 /* ANA:POL:POL_PIR_CFG */ 451 #define ANA_POL_PIR_CFG(g) __REG(TARGET_ANA, 0, 1, 16384, g, 345, 32, 0, 0, 1, 4) 452 453 #define ANA_POL_PIR_CFG_PIR_RATE GENMASK(20, 6) 454 #define ANA_POL_PIR_CFG_PIR_RATE_SET(x)\ 455 FIELD_PREP(ANA_POL_PIR_CFG_PIR_RATE, x) 456 #define ANA_POL_PIR_CFG_PIR_RATE_GET(x)\ 457 FIELD_GET(ANA_POL_PIR_CFG_PIR_RATE, x) 458 459 #define ANA_POL_PIR_CFG_PIR_BURST GENMASK(5, 0) 460 #define ANA_POL_PIR_CFG_PIR_BURST_SET(x)\ 461 FIELD_PREP(ANA_POL_PIR_CFG_PIR_BURST, x) 462 #define ANA_POL_PIR_CFG_PIR_BURST_GET(x)\ 463 FIELD_GET(ANA_POL_PIR_CFG_PIR_BURST, x) 464 465 /* ANA:POL:POL_MODE_CFG */ 466 #define ANA_POL_MODE(g) __REG(TARGET_ANA, 0, 1, 16384, g, 345, 32, 8, 0, 1, 4) 467 468 #define ANA_POL_MODE_DROP_ON_YELLOW_ENA BIT(11) 469 #define ANA_POL_MODE_DROP_ON_YELLOW_ENA_SET(x)\ 470 FIELD_PREP(ANA_POL_MODE_DROP_ON_YELLOW_ENA, x) 471 #define ANA_POL_MODE_DROP_ON_YELLOW_ENA_GET(x)\ 472 FIELD_GET(ANA_POL_MODE_DROP_ON_YELLOW_ENA, x) 473 474 #define ANA_POL_MODE_MARK_ALL_FRMS_RED_ENA BIT(10) 475 #define ANA_POL_MODE_MARK_ALL_FRMS_RED_ENA_SET(x)\ 476 FIELD_PREP(ANA_POL_MODE_MARK_ALL_FRMS_RED_ENA, x) 477 #define ANA_POL_MODE_MARK_ALL_FRMS_RED_ENA_GET(x)\ 478 FIELD_GET(ANA_POL_MODE_MARK_ALL_FRMS_RED_ENA, x) 479 480 #define ANA_POL_MODE_IPG_SIZE GENMASK(9, 5) 481 #define ANA_POL_MODE_IPG_SIZE_SET(x)\ 482 FIELD_PREP(ANA_POL_MODE_IPG_SIZE, x) 483 #define ANA_POL_MODE_IPG_SIZE_GET(x)\ 484 FIELD_GET(ANA_POL_MODE_IPG_SIZE, x) 485 486 #define ANA_POL_MODE_FRM_MODE GENMASK(4, 3) 487 #define ANA_POL_MODE_FRM_MODE_SET(x)\ 488 FIELD_PREP(ANA_POL_MODE_FRM_MODE, x) 489 #define ANA_POL_MODE_FRM_MODE_GET(x)\ 490 FIELD_GET(ANA_POL_MODE_FRM_MODE, x) 491 492 #define ANA_POL_MODE_OVERSHOOT_ENA BIT(0) 493 #define ANA_POL_MODE_OVERSHOOT_ENA_SET(x)\ 494 FIELD_PREP(ANA_POL_MODE_OVERSHOOT_ENA, x) 495 #define ANA_POL_MODE_OVERSHOOT_ENA_GET(x)\ 496 FIELD_GET(ANA_POL_MODE_OVERSHOOT_ENA, x) 497 498 /* ANA:POL:POL_PIR_STATE */ 499 #define ANA_POL_PIR_STATE(g) __REG(TARGET_ANA, 0, 1, 16384, g, 345, 32, 12, 0, 1, 4) 500 501 #define ANA_POL_PIR_STATE_PIR_LVL GENMASK(21, 0) 502 #define ANA_POL_PIR_STATE_PIR_LVL_SET(x)\ 503 FIELD_PREP(ANA_POL_PIR_STATE_PIR_LVL, x) 504 #define ANA_POL_PIR_STATE_PIR_LVL_GET(x)\ 505 FIELD_GET(ANA_POL_PIR_STATE_PIR_LVL, x) 506 507 /* CHIP_TOP:CUPHY_CFG:CUPHY_PORT_CFG */ 508 #define CHIP_TOP_CUPHY_PORT_CFG(r) __REG(TARGET_CHIP_TOP, 0, 1, 16, 0, 1, 20, 8, r, 2, 4) 509 510 #define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA BIT(0) 511 #define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA_SET(x)\ 512 FIELD_PREP(CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA, x) 513 #define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA_GET(x)\ 514 FIELD_GET(CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA, x) 515 516 /* DEV:PORT_MODE:CLOCK_CFG */ 517 #define DEV_CLOCK_CFG(t) __REG(TARGET_DEV, t, 8, 0, 0, 1, 28, 0, 0, 1, 4) 518 519 #define DEV_CLOCK_CFG_MAC_TX_RST BIT(7) 520 #define DEV_CLOCK_CFG_MAC_TX_RST_SET(x)\ 521 FIELD_PREP(DEV_CLOCK_CFG_MAC_TX_RST, x) 522 #define DEV_CLOCK_CFG_MAC_TX_RST_GET(x)\ 523 FIELD_GET(DEV_CLOCK_CFG_MAC_TX_RST, x) 524 525 #define DEV_CLOCK_CFG_MAC_RX_RST BIT(6) 526 #define DEV_CLOCK_CFG_MAC_RX_RST_SET(x)\ 527 FIELD_PREP(DEV_CLOCK_CFG_MAC_RX_RST, x) 528 #define DEV_CLOCK_CFG_MAC_RX_RST_GET(x)\ 529 FIELD_GET(DEV_CLOCK_CFG_MAC_RX_RST, x) 530 531 #define DEV_CLOCK_CFG_PCS_TX_RST BIT(5) 532 #define DEV_CLOCK_CFG_PCS_TX_RST_SET(x)\ 533 FIELD_PREP(DEV_CLOCK_CFG_PCS_TX_RST, x) 534 #define DEV_CLOCK_CFG_PCS_TX_RST_GET(x)\ 535 FIELD_GET(DEV_CLOCK_CFG_PCS_TX_RST, x) 536 537 #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4) 538 #define DEV_CLOCK_CFG_PCS_RX_RST_SET(x)\ 539 FIELD_PREP(DEV_CLOCK_CFG_PCS_RX_RST, x) 540 #define DEV_CLOCK_CFG_PCS_RX_RST_GET(x)\ 541 FIELD_GET(DEV_CLOCK_CFG_PCS_RX_RST, x) 542 543 #define DEV_CLOCK_CFG_PORT_RST BIT(3) 544 #define DEV_CLOCK_CFG_PORT_RST_SET(x)\ 545 FIELD_PREP(DEV_CLOCK_CFG_PORT_RST, x) 546 #define DEV_CLOCK_CFG_PORT_RST_GET(x)\ 547 FIELD_GET(DEV_CLOCK_CFG_PORT_RST, x) 548 549 #define DEV_CLOCK_CFG_LINK_SPEED GENMASK(1, 0) 550 #define DEV_CLOCK_CFG_LINK_SPEED_SET(x)\ 551 FIELD_PREP(DEV_CLOCK_CFG_LINK_SPEED, x) 552 #define DEV_CLOCK_CFG_LINK_SPEED_GET(x)\ 553 FIELD_GET(DEV_CLOCK_CFG_LINK_SPEED, x) 554 555 /* DEV:MAC_CFG_STATUS:MAC_ENA_CFG */ 556 #define DEV_MAC_ENA_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 0, 0, 1, 4) 557 558 #define DEV_MAC_ENA_CFG_RX_ENA BIT(4) 559 #define DEV_MAC_ENA_CFG_RX_ENA_SET(x)\ 560 FIELD_PREP(DEV_MAC_ENA_CFG_RX_ENA, x) 561 #define DEV_MAC_ENA_CFG_RX_ENA_GET(x)\ 562 FIELD_GET(DEV_MAC_ENA_CFG_RX_ENA, x) 563 564 #define DEV_MAC_ENA_CFG_TX_ENA BIT(0) 565 #define DEV_MAC_ENA_CFG_TX_ENA_SET(x)\ 566 FIELD_PREP(DEV_MAC_ENA_CFG_TX_ENA, x) 567 #define DEV_MAC_ENA_CFG_TX_ENA_GET(x)\ 568 FIELD_GET(DEV_MAC_ENA_CFG_TX_ENA, x) 569 570 /* DEV:MAC_CFG_STATUS:MAC_MODE_CFG */ 571 #define DEV_MAC_MODE_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 4, 0, 1, 4) 572 573 #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA BIT(4) 574 #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA_SET(x)\ 575 FIELD_PREP(DEV_MAC_MODE_CFG_GIGA_MODE_ENA, x) 576 #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA_GET(x)\ 577 FIELD_GET(DEV_MAC_MODE_CFG_GIGA_MODE_ENA, x) 578 579 /* DEV:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ 580 #define DEV_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 8, 0, 1, 4) 581 582 #define DEV_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0) 583 #define DEV_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ 584 FIELD_PREP(DEV_MAC_MAXLEN_CFG_MAX_LEN, x) 585 #define DEV_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ 586 FIELD_GET(DEV_MAC_MAXLEN_CFG_MAX_LEN, x) 587 588 /* DEV:MAC_CFG_STATUS:MAC_TAGS_CFG */ 589 #define DEV_MAC_TAGS_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 12, 0, 1, 4) 590 591 #define DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA BIT(1) 592 #define DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA_SET(x)\ 593 FIELD_PREP(DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA, x) 594 #define DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA_GET(x)\ 595 FIELD_GET(DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA, x) 596 597 #define DEV_MAC_TAGS_CFG_VLAN_AWR_ENA BIT(0) 598 #define DEV_MAC_TAGS_CFG_VLAN_AWR_ENA_SET(x)\ 599 FIELD_PREP(DEV_MAC_TAGS_CFG_VLAN_AWR_ENA, x) 600 #define DEV_MAC_TAGS_CFG_VLAN_AWR_ENA_GET(x)\ 601 FIELD_GET(DEV_MAC_TAGS_CFG_VLAN_AWR_ENA, x) 602 603 /* DEV:MAC_CFG_STATUS:MAC_IFG_CFG */ 604 #define DEV_MAC_IFG_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 20, 0, 1, 4) 605 606 #define DEV_MAC_IFG_CFG_TX_IFG GENMASK(12, 8) 607 #define DEV_MAC_IFG_CFG_TX_IFG_SET(x)\ 608 FIELD_PREP(DEV_MAC_IFG_CFG_TX_IFG, x) 609 #define DEV_MAC_IFG_CFG_TX_IFG_GET(x)\ 610 FIELD_GET(DEV_MAC_IFG_CFG_TX_IFG, x) 611 612 #define DEV_MAC_IFG_CFG_RX_IFG2 GENMASK(7, 4) 613 #define DEV_MAC_IFG_CFG_RX_IFG2_SET(x)\ 614 FIELD_PREP(DEV_MAC_IFG_CFG_RX_IFG2, x) 615 #define DEV_MAC_IFG_CFG_RX_IFG2_GET(x)\ 616 FIELD_GET(DEV_MAC_IFG_CFG_RX_IFG2, x) 617 618 #define DEV_MAC_IFG_CFG_RX_IFG1 GENMASK(3, 0) 619 #define DEV_MAC_IFG_CFG_RX_IFG1_SET(x)\ 620 FIELD_PREP(DEV_MAC_IFG_CFG_RX_IFG1, x) 621 #define DEV_MAC_IFG_CFG_RX_IFG1_GET(x)\ 622 FIELD_GET(DEV_MAC_IFG_CFG_RX_IFG1, x) 623 624 /* DEV:MAC_CFG_STATUS:MAC_HDX_CFG */ 625 #define DEV_MAC_HDX_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 24, 0, 1, 4) 626 627 #define DEV_MAC_HDX_CFG_SEED GENMASK(23, 16) 628 #define DEV_MAC_HDX_CFG_SEED_SET(x)\ 629 FIELD_PREP(DEV_MAC_HDX_CFG_SEED, x) 630 #define DEV_MAC_HDX_CFG_SEED_GET(x)\ 631 FIELD_GET(DEV_MAC_HDX_CFG_SEED, x) 632 633 #define DEV_MAC_HDX_CFG_SEED_LOAD BIT(12) 634 #define DEV_MAC_HDX_CFG_SEED_LOAD_SET(x)\ 635 FIELD_PREP(DEV_MAC_HDX_CFG_SEED_LOAD, x) 636 #define DEV_MAC_HDX_CFG_SEED_LOAD_GET(x)\ 637 FIELD_GET(DEV_MAC_HDX_CFG_SEED_LOAD, x) 638 639 /* DEV:MAC_CFG_STATUS:MAC_FC_MAC_LOW_CFG */ 640 #define DEV_FC_MAC_LOW_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 32, 0, 1, 4) 641 642 /* DEV:MAC_CFG_STATUS:MAC_FC_MAC_HIGH_CFG */ 643 #define DEV_FC_MAC_HIGH_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 36, 0, 1, 4) 644 645 /* DEV:PCS1G_CFG_STATUS:PCS1G_CFG */ 646 #define DEV_PCS1G_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 0, 0, 1, 4) 647 648 #define DEV_PCS1G_CFG_PCS_ENA BIT(0) 649 #define DEV_PCS1G_CFG_PCS_ENA_SET(x)\ 650 FIELD_PREP(DEV_PCS1G_CFG_PCS_ENA, x) 651 #define DEV_PCS1G_CFG_PCS_ENA_GET(x)\ 652 FIELD_GET(DEV_PCS1G_CFG_PCS_ENA, x) 653 654 /* DEV:PCS1G_CFG_STATUS:PCS1G_MODE_CFG */ 655 #define DEV_PCS1G_MODE_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 4, 0, 1, 4) 656 657 #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0) 658 #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(x)\ 659 FIELD_PREP(DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA, x) 660 #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_GET(x)\ 661 FIELD_GET(DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA, x) 662 663 #define DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA BIT(1) 664 #define DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_SET(x)\ 665 FIELD_PREP(DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x) 666 #define DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_GET(x)\ 667 FIELD_GET(DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x) 668 669 /* DEV:PCS1G_CFG_STATUS:PCS1G_SD_CFG */ 670 #define DEV_PCS1G_SD_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 8, 0, 1, 4) 671 672 #define DEV_PCS1G_SD_CFG_SD_ENA BIT(0) 673 #define DEV_PCS1G_SD_CFG_SD_ENA_SET(x)\ 674 FIELD_PREP(DEV_PCS1G_SD_CFG_SD_ENA, x) 675 #define DEV_PCS1G_SD_CFG_SD_ENA_GET(x)\ 676 FIELD_GET(DEV_PCS1G_SD_CFG_SD_ENA, x) 677 678 /* DEV:PCS1G_CFG_STATUS:PCS1G_ANEG_CFG */ 679 #define DEV_PCS1G_ANEG_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 12, 0, 1, 4) 680 681 #define DEV_PCS1G_ANEG_CFG_ADV_ABILITY GENMASK(31, 16) 682 #define DEV_PCS1G_ANEG_CFG_ADV_ABILITY_SET(x)\ 683 FIELD_PREP(DEV_PCS1G_ANEG_CFG_ADV_ABILITY, x) 684 #define DEV_PCS1G_ANEG_CFG_ADV_ABILITY_GET(x)\ 685 FIELD_GET(DEV_PCS1G_ANEG_CFG_ADV_ABILITY, x) 686 687 #define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA BIT(8) 688 #define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_SET(x)\ 689 FIELD_PREP(DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x) 690 #define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_GET(x)\ 691 FIELD_GET(DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x) 692 693 #define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT BIT(1) 694 #define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT_SET(x)\ 695 FIELD_PREP(DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT, x) 696 #define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT_GET(x)\ 697 FIELD_GET(DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT, x) 698 699 #define DEV_PCS1G_ANEG_CFG_ENA BIT(0) 700 #define DEV_PCS1G_ANEG_CFG_ENA_SET(x)\ 701 FIELD_PREP(DEV_PCS1G_ANEG_CFG_ENA, x) 702 #define DEV_PCS1G_ANEG_CFG_ENA_GET(x)\ 703 FIELD_GET(DEV_PCS1G_ANEG_CFG_ENA, x) 704 705 /* DEV:PCS1G_CFG_STATUS:PCS1G_ANEG_STATUS */ 706 #define DEV_PCS1G_ANEG_STATUS(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 32, 0, 1, 4) 707 708 #define DEV_PCS1G_ANEG_STATUS_LP_ADV GENMASK(31, 16) 709 #define DEV_PCS1G_ANEG_STATUS_LP_ADV_SET(x)\ 710 FIELD_PREP(DEV_PCS1G_ANEG_STATUS_LP_ADV, x) 711 #define DEV_PCS1G_ANEG_STATUS_LP_ADV_GET(x)\ 712 FIELD_GET(DEV_PCS1G_ANEG_STATUS_LP_ADV, x) 713 714 #define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE BIT(0) 715 #define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE_SET(x)\ 716 FIELD_PREP(DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x) 717 #define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(x)\ 718 FIELD_GET(DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x) 719 720 /* DEV:PCS1G_CFG_STATUS:PCS1G_LINK_STATUS */ 721 #define DEV_PCS1G_LINK_STATUS(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 40, 0, 1, 4) 722 723 #define DEV_PCS1G_LINK_STATUS_LINK_STATUS BIT(4) 724 #define DEV_PCS1G_LINK_STATUS_LINK_STATUS_SET(x)\ 725 FIELD_PREP(DEV_PCS1G_LINK_STATUS_LINK_STATUS, x) 726 #define DEV_PCS1G_LINK_STATUS_LINK_STATUS_GET(x)\ 727 FIELD_GET(DEV_PCS1G_LINK_STATUS_LINK_STATUS, x) 728 729 #define DEV_PCS1G_LINK_STATUS_SYNC_STATUS BIT(0) 730 #define DEV_PCS1G_LINK_STATUS_SYNC_STATUS_SET(x)\ 731 FIELD_PREP(DEV_PCS1G_LINK_STATUS_SYNC_STATUS, x) 732 #define DEV_PCS1G_LINK_STATUS_SYNC_STATUS_GET(x)\ 733 FIELD_GET(DEV_PCS1G_LINK_STATUS_SYNC_STATUS, x) 734 735 /* DEV:PCS1G_CFG_STATUS:PCS1G_STICKY */ 736 #define DEV_PCS1G_STICKY(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 48, 0, 1, 4) 737 738 #define DEV_PCS1G_STICKY_LINK_DOWN_STICKY BIT(4) 739 #define DEV_PCS1G_STICKY_LINK_DOWN_STICKY_SET(x)\ 740 FIELD_PREP(DEV_PCS1G_STICKY_LINK_DOWN_STICKY, x) 741 #define DEV_PCS1G_STICKY_LINK_DOWN_STICKY_GET(x)\ 742 FIELD_GET(DEV_PCS1G_STICKY_LINK_DOWN_STICKY, x) 743 744 /* FDMA:FDMA:FDMA_CH_ACTIVATE */ 745 #define FDMA_CH_ACTIVATE __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 0, 0, 1, 4) 746 747 #define FDMA_CH_ACTIVATE_CH_ACTIVATE GENMASK(7, 0) 748 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_SET(x)\ 749 FIELD_PREP(FDMA_CH_ACTIVATE_CH_ACTIVATE, x) 750 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_GET(x)\ 751 FIELD_GET(FDMA_CH_ACTIVATE_CH_ACTIVATE, x) 752 753 /* FDMA:FDMA:FDMA_CH_RELOAD */ 754 #define FDMA_CH_RELOAD __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 4, 0, 1, 4) 755 756 #define FDMA_CH_RELOAD_CH_RELOAD GENMASK(7, 0) 757 #define FDMA_CH_RELOAD_CH_RELOAD_SET(x)\ 758 FIELD_PREP(FDMA_CH_RELOAD_CH_RELOAD, x) 759 #define FDMA_CH_RELOAD_CH_RELOAD_GET(x)\ 760 FIELD_GET(FDMA_CH_RELOAD_CH_RELOAD, x) 761 762 /* FDMA:FDMA:FDMA_CH_DISABLE */ 763 #define FDMA_CH_DISABLE __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 8, 0, 1, 4) 764 765 #define FDMA_CH_DISABLE_CH_DISABLE GENMASK(7, 0) 766 #define FDMA_CH_DISABLE_CH_DISABLE_SET(x)\ 767 FIELD_PREP(FDMA_CH_DISABLE_CH_DISABLE, x) 768 #define FDMA_CH_DISABLE_CH_DISABLE_GET(x)\ 769 FIELD_GET(FDMA_CH_DISABLE_CH_DISABLE, x) 770 771 /* FDMA:FDMA:FDMA_CH_DB_DISCARD */ 772 #define FDMA_CH_DB_DISCARD __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 16, 0, 1, 4) 773 774 #define FDMA_CH_DB_DISCARD_DB_DISCARD GENMASK(7, 0) 775 #define FDMA_CH_DB_DISCARD_DB_DISCARD_SET(x)\ 776 FIELD_PREP(FDMA_CH_DB_DISCARD_DB_DISCARD, x) 777 #define FDMA_CH_DB_DISCARD_DB_DISCARD_GET(x)\ 778 FIELD_GET(FDMA_CH_DB_DISCARD_DB_DISCARD, x) 779 780 /* FDMA:FDMA:FDMA_DCB_LLP */ 781 #define FDMA_DCB_LLP(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 52, r, 8, 4) 782 783 /* FDMA:FDMA:FDMA_DCB_LLP1 */ 784 #define FDMA_DCB_LLP1(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 84, r, 8, 4) 785 786 /* FDMA:FDMA:FDMA_CH_ACTIVE */ 787 #define FDMA_CH_ACTIVE __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 180, 0, 1, 4) 788 789 /* FDMA:FDMA:FDMA_CH_CFG */ 790 #define FDMA_CH_CFG(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 224, r, 8, 4) 791 792 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY BIT(4) 793 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(x)\ 794 FIELD_PREP(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x) 795 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_GET(x)\ 796 FIELD_GET(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x) 797 798 #define FDMA_CH_CFG_CH_INJ_PORT BIT(3) 799 #define FDMA_CH_CFG_CH_INJ_PORT_SET(x)\ 800 FIELD_PREP(FDMA_CH_CFG_CH_INJ_PORT, x) 801 #define FDMA_CH_CFG_CH_INJ_PORT_GET(x)\ 802 FIELD_GET(FDMA_CH_CFG_CH_INJ_PORT, x) 803 804 #define FDMA_CH_CFG_CH_DCB_DB_CNT GENMASK(2, 1) 805 #define FDMA_CH_CFG_CH_DCB_DB_CNT_SET(x)\ 806 FIELD_PREP(FDMA_CH_CFG_CH_DCB_DB_CNT, x) 807 #define FDMA_CH_CFG_CH_DCB_DB_CNT_GET(x)\ 808 FIELD_GET(FDMA_CH_CFG_CH_DCB_DB_CNT, x) 809 810 #define FDMA_CH_CFG_CH_MEM BIT(0) 811 #define FDMA_CH_CFG_CH_MEM_SET(x)\ 812 FIELD_PREP(FDMA_CH_CFG_CH_MEM, x) 813 #define FDMA_CH_CFG_CH_MEM_GET(x)\ 814 FIELD_GET(FDMA_CH_CFG_CH_MEM, x) 815 816 /* FDMA:FDMA:FDMA_PORT_CTRL */ 817 #define FDMA_PORT_CTRL(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 376, r, 2, 4) 818 819 #define FDMA_PORT_CTRL_INJ_STOP BIT(4) 820 #define FDMA_PORT_CTRL_INJ_STOP_SET(x)\ 821 FIELD_PREP(FDMA_PORT_CTRL_INJ_STOP, x) 822 #define FDMA_PORT_CTRL_INJ_STOP_GET(x)\ 823 FIELD_GET(FDMA_PORT_CTRL_INJ_STOP, x) 824 825 #define FDMA_PORT_CTRL_XTR_STOP BIT(2) 826 #define FDMA_PORT_CTRL_XTR_STOP_SET(x)\ 827 FIELD_PREP(FDMA_PORT_CTRL_XTR_STOP, x) 828 #define FDMA_PORT_CTRL_XTR_STOP_GET(x)\ 829 FIELD_GET(FDMA_PORT_CTRL_XTR_STOP, x) 830 831 /* FDMA:FDMA:FDMA_INTR_DB */ 832 #define FDMA_INTR_DB __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 392, 0, 1, 4) 833 834 /* FDMA:FDMA:FDMA_INTR_DB_ENA */ 835 #define FDMA_INTR_DB_ENA __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 396, 0, 1, 4) 836 837 #define FDMA_INTR_DB_ENA_INTR_DB_ENA GENMASK(7, 0) 838 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_SET(x)\ 839 FIELD_PREP(FDMA_INTR_DB_ENA_INTR_DB_ENA, x) 840 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_GET(x)\ 841 FIELD_GET(FDMA_INTR_DB_ENA_INTR_DB_ENA, x) 842 843 /* FDMA:FDMA:FDMA_INTR_ERR */ 844 #define FDMA_INTR_ERR __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 400, 0, 1, 4) 845 846 /* FDMA:FDMA:FDMA_ERRORS */ 847 #define FDMA_ERRORS __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 412, 0, 1, 4) 848 849 /* PTP:PTP_CFG:PTP_PIN_INTR */ 850 #define PTP_PIN_INTR __REG(TARGET_PTP, 0, 1, 512, 0, 1, 16, 0, 0, 1, 4) 851 852 #define PTP_PIN_INTR_INTR_PTP GENMASK(7, 0) 853 #define PTP_PIN_INTR_INTR_PTP_SET(x)\ 854 FIELD_PREP(PTP_PIN_INTR_INTR_PTP, x) 855 #define PTP_PIN_INTR_INTR_PTP_GET(x)\ 856 FIELD_GET(PTP_PIN_INTR_INTR_PTP, x) 857 858 /* PTP:PTP_CFG:PTP_PIN_INTR_ENA */ 859 #define PTP_PIN_INTR_ENA __REG(TARGET_PTP, 0, 1, 512, 0, 1, 16, 4, 0, 1, 4) 860 861 #define PTP_PIN_INTR_ENA_INTR_ENA GENMASK(7, 0) 862 #define PTP_PIN_INTR_ENA_INTR_ENA_SET(x)\ 863 FIELD_PREP(PTP_PIN_INTR_ENA_INTR_ENA, x) 864 #define PTP_PIN_INTR_ENA_INTR_ENA_GET(x)\ 865 FIELD_GET(PTP_PIN_INTR_ENA_INTR_ENA, x) 866 867 /* PTP:PTP_CFG:PTP_DOM_CFG */ 868 #define PTP_DOM_CFG __REG(TARGET_PTP, 0, 1, 512, 0, 1, 16, 12, 0, 1, 4) 869 870 #define PTP_DOM_CFG_ENA GENMASK(11, 9) 871 #define PTP_DOM_CFG_ENA_SET(x)\ 872 FIELD_PREP(PTP_DOM_CFG_ENA, x) 873 #define PTP_DOM_CFG_ENA_GET(x)\ 874 FIELD_GET(PTP_DOM_CFG_ENA, x) 875 876 #define PTP_DOM_CFG_CLKCFG_DIS GENMASK(2, 0) 877 #define PTP_DOM_CFG_CLKCFG_DIS_SET(x)\ 878 FIELD_PREP(PTP_DOM_CFG_CLKCFG_DIS, x) 879 #define PTP_DOM_CFG_CLKCFG_DIS_GET(x)\ 880 FIELD_GET(PTP_DOM_CFG_CLKCFG_DIS, x) 881 882 /* PTP:PTP_TOD_DOMAINS:CLK_PER_CFG */ 883 #define PTP_CLK_PER_CFG(g, r) __REG(TARGET_PTP, 0, 1, 528, g, 3, 28, 0, r, 2, 4) 884 885 /* PTP:PTP_PINS:PTP_PIN_CFG */ 886 #define PTP_PIN_CFG(g) __REG(TARGET_PTP, 0, 1, 0, g, 8, 64, 0, 0, 1, 4) 887 888 #define PTP_PIN_CFG_PIN_ACTION GENMASK(29, 27) 889 #define PTP_PIN_CFG_PIN_ACTION_SET(x)\ 890 FIELD_PREP(PTP_PIN_CFG_PIN_ACTION, x) 891 #define PTP_PIN_CFG_PIN_ACTION_GET(x)\ 892 FIELD_GET(PTP_PIN_CFG_PIN_ACTION, x) 893 894 #define PTP_PIN_CFG_PIN_SYNC GENMASK(26, 25) 895 #define PTP_PIN_CFG_PIN_SYNC_SET(x)\ 896 FIELD_PREP(PTP_PIN_CFG_PIN_SYNC, x) 897 #define PTP_PIN_CFG_PIN_SYNC_GET(x)\ 898 FIELD_GET(PTP_PIN_CFG_PIN_SYNC, x) 899 900 #define PTP_PIN_CFG_PIN_SELECT GENMASK(23, 21) 901 #define PTP_PIN_CFG_PIN_SELECT_SET(x)\ 902 FIELD_PREP(PTP_PIN_CFG_PIN_SELECT, x) 903 #define PTP_PIN_CFG_PIN_SELECT_GET(x)\ 904 FIELD_GET(PTP_PIN_CFG_PIN_SELECT, x) 905 906 #define PTP_PIN_CFG_PIN_DOM GENMASK(17, 16) 907 #define PTP_PIN_CFG_PIN_DOM_SET(x)\ 908 FIELD_PREP(PTP_PIN_CFG_PIN_DOM, x) 909 #define PTP_PIN_CFG_PIN_DOM_GET(x)\ 910 FIELD_GET(PTP_PIN_CFG_PIN_DOM, x) 911 912 /* PTP:PTP_PINS:PTP_TOD_SEC_MSB */ 913 #define PTP_TOD_SEC_MSB(g) __REG(TARGET_PTP, 0, 1, 0, g, 8, 64, 4, 0, 1, 4) 914 915 #define PTP_TOD_SEC_MSB_TOD_SEC_MSB GENMASK(15, 0) 916 #define PTP_TOD_SEC_MSB_TOD_SEC_MSB_SET(x)\ 917 FIELD_PREP(PTP_TOD_SEC_MSB_TOD_SEC_MSB, x) 918 #define PTP_TOD_SEC_MSB_TOD_SEC_MSB_GET(x)\ 919 FIELD_GET(PTP_TOD_SEC_MSB_TOD_SEC_MSB, x) 920 921 /* PTP:PTP_PINS:PTP_TOD_SEC_LSB */ 922 #define PTP_TOD_SEC_LSB(g) __REG(TARGET_PTP, 0, 1, 0, g, 8, 64, 8, 0, 1, 4) 923 924 /* PTP:PTP_PINS:PTP_TOD_NSEC */ 925 #define PTP_TOD_NSEC(g) __REG(TARGET_PTP, 0, 1, 0, g, 8, 64, 12, 0, 1, 4) 926 927 #define PTP_TOD_NSEC_TOD_NSEC GENMASK(29, 0) 928 #define PTP_TOD_NSEC_TOD_NSEC_SET(x)\ 929 FIELD_PREP(PTP_TOD_NSEC_TOD_NSEC, x) 930 #define PTP_TOD_NSEC_TOD_NSEC_GET(x)\ 931 FIELD_GET(PTP_TOD_NSEC_TOD_NSEC, x) 932 933 /* PTP:PTP_PINS:WF_HIGH_PERIOD */ 934 #define PTP_WF_HIGH_PERIOD(g) __REG(TARGET_PTP,\ 935 0, 1, 0, g, 8, 64, 24, 0, 1, 4) 936 937 #define PTP_WF_HIGH_PERIOD_PIN_WFH(x) ((x) & GENMASK(29, 0)) 938 #define PTP_WF_HIGH_PERIOD_PIN_WFH_M GENMASK(29, 0) 939 #define PTP_WF_HIGH_PERIOD_PIN_WFH_X(x) ((x) & GENMASK(29, 0)) 940 941 /* PTP:PTP_PINS:WF_LOW_PERIOD */ 942 #define PTP_WF_LOW_PERIOD(g) __REG(TARGET_PTP,\ 943 0, 1, 0, g, 8, 64, 28, 0, 1, 4) 944 945 #define PTP_WF_LOW_PERIOD_PIN_WFL(x) ((x) & GENMASK(29, 0)) 946 #define PTP_WF_LOW_PERIOD_PIN_WFL_M GENMASK(29, 0) 947 #define PTP_WF_LOW_PERIOD_PIN_WFL_X(x) ((x) & GENMASK(29, 0)) 948 949 /* PTP:PTP_TS_FIFO:PTP_TWOSTEP_CTRL */ 950 #define PTP_TWOSTEP_CTRL __REG(TARGET_PTP, 0, 1, 612, 0, 1, 12, 0, 0, 1, 4) 951 952 #define PTP_TWOSTEP_CTRL_NXT BIT(11) 953 #define PTP_TWOSTEP_CTRL_NXT_SET(x)\ 954 FIELD_PREP(PTP_TWOSTEP_CTRL_NXT, x) 955 #define PTP_TWOSTEP_CTRL_NXT_GET(x)\ 956 FIELD_GET(PTP_TWOSTEP_CTRL_NXT, x) 957 958 #define PTP_TWOSTEP_CTRL_VLD BIT(10) 959 #define PTP_TWOSTEP_CTRL_VLD_SET(x)\ 960 FIELD_PREP(PTP_TWOSTEP_CTRL_VLD, x) 961 #define PTP_TWOSTEP_CTRL_VLD_GET(x)\ 962 FIELD_GET(PTP_TWOSTEP_CTRL_VLD, x) 963 964 #define PTP_TWOSTEP_CTRL_STAMP_TX BIT(9) 965 #define PTP_TWOSTEP_CTRL_STAMP_TX_SET(x)\ 966 FIELD_PREP(PTP_TWOSTEP_CTRL_STAMP_TX, x) 967 #define PTP_TWOSTEP_CTRL_STAMP_TX_GET(x)\ 968 FIELD_GET(PTP_TWOSTEP_CTRL_STAMP_TX, x) 969 970 #define PTP_TWOSTEP_CTRL_STAMP_PORT GENMASK(8, 1) 971 #define PTP_TWOSTEP_CTRL_STAMP_PORT_SET(x)\ 972 FIELD_PREP(PTP_TWOSTEP_CTRL_STAMP_PORT, x) 973 #define PTP_TWOSTEP_CTRL_STAMP_PORT_GET(x)\ 974 FIELD_GET(PTP_TWOSTEP_CTRL_STAMP_PORT, x) 975 976 #define PTP_TWOSTEP_CTRL_OVFL BIT(0) 977 #define PTP_TWOSTEP_CTRL_OVFL_SET(x)\ 978 FIELD_PREP(PTP_TWOSTEP_CTRL_OVFL, x) 979 #define PTP_TWOSTEP_CTRL_OVFL_GET(x)\ 980 FIELD_GET(PTP_TWOSTEP_CTRL_OVFL, x) 981 982 /* PTP:PTP_TS_FIFO:PTP_TWOSTEP_STAMP */ 983 #define PTP_TWOSTEP_STAMP __REG(TARGET_PTP, 0, 1, 612, 0, 1, 12, 4, 0, 1, 4) 984 985 #define PTP_TWOSTEP_STAMP_STAMP_NSEC GENMASK(31, 2) 986 #define PTP_TWOSTEP_STAMP_STAMP_NSEC_SET(x)\ 987 FIELD_PREP(PTP_TWOSTEP_STAMP_STAMP_NSEC, x) 988 #define PTP_TWOSTEP_STAMP_STAMP_NSEC_GET(x)\ 989 FIELD_GET(PTP_TWOSTEP_STAMP_STAMP_NSEC, x) 990 991 /* DEVCPU_QS:XTR:XTR_GRP_CFG */ 992 #define QS_XTR_GRP_CFG(r) __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 0, r, 2, 4) 993 994 #define QS_XTR_GRP_CFG_MODE GENMASK(3, 2) 995 #define QS_XTR_GRP_CFG_MODE_SET(x)\ 996 FIELD_PREP(QS_XTR_GRP_CFG_MODE, x) 997 #define QS_XTR_GRP_CFG_MODE_GET(x)\ 998 FIELD_GET(QS_XTR_GRP_CFG_MODE, x) 999 1000 #define QS_XTR_GRP_CFG_BYTE_SWAP BIT(0) 1001 #define QS_XTR_GRP_CFG_BYTE_SWAP_SET(x)\ 1002 FIELD_PREP(QS_XTR_GRP_CFG_BYTE_SWAP, x) 1003 #define QS_XTR_GRP_CFG_BYTE_SWAP_GET(x)\ 1004 FIELD_GET(QS_XTR_GRP_CFG_BYTE_SWAP, x) 1005 1006 /* DEVCPU_QS:XTR:XTR_RD */ 1007 #define QS_XTR_RD(r) __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 8, r, 2, 4) 1008 1009 /* DEVCPU_QS:XTR:XTR_FLUSH */ 1010 #define QS_XTR_FLUSH __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 24, 0, 1, 4) 1011 1012 /* DEVCPU_QS:XTR:XTR_DATA_PRESENT */ 1013 #define QS_XTR_DATA_PRESENT __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 28, 0, 1, 4) 1014 1015 /* DEVCPU_QS:INJ:INJ_GRP_CFG */ 1016 #define QS_INJ_GRP_CFG(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 0, r, 2, 4) 1017 1018 #define QS_INJ_GRP_CFG_MODE GENMASK(3, 2) 1019 #define QS_INJ_GRP_CFG_MODE_SET(x)\ 1020 FIELD_PREP(QS_INJ_GRP_CFG_MODE, x) 1021 #define QS_INJ_GRP_CFG_MODE_GET(x)\ 1022 FIELD_GET(QS_INJ_GRP_CFG_MODE, x) 1023 1024 #define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0) 1025 #define QS_INJ_GRP_CFG_BYTE_SWAP_SET(x)\ 1026 FIELD_PREP(QS_INJ_GRP_CFG_BYTE_SWAP, x) 1027 #define QS_INJ_GRP_CFG_BYTE_SWAP_GET(x)\ 1028 FIELD_GET(QS_INJ_GRP_CFG_BYTE_SWAP, x) 1029 1030 /* DEVCPU_QS:INJ:INJ_WR */ 1031 #define QS_INJ_WR(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 8, r, 2, 4) 1032 1033 /* DEVCPU_QS:INJ:INJ_CTRL */ 1034 #define QS_INJ_CTRL(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 16, r, 2, 4) 1035 1036 #define QS_INJ_CTRL_GAP_SIZE GENMASK(24, 21) 1037 #define QS_INJ_CTRL_GAP_SIZE_SET(x)\ 1038 FIELD_PREP(QS_INJ_CTRL_GAP_SIZE, x) 1039 #define QS_INJ_CTRL_GAP_SIZE_GET(x)\ 1040 FIELD_GET(QS_INJ_CTRL_GAP_SIZE, x) 1041 1042 #define QS_INJ_CTRL_EOF BIT(19) 1043 #define QS_INJ_CTRL_EOF_SET(x)\ 1044 FIELD_PREP(QS_INJ_CTRL_EOF, x) 1045 #define QS_INJ_CTRL_EOF_GET(x)\ 1046 FIELD_GET(QS_INJ_CTRL_EOF, x) 1047 1048 #define QS_INJ_CTRL_SOF BIT(18) 1049 #define QS_INJ_CTRL_SOF_SET(x)\ 1050 FIELD_PREP(QS_INJ_CTRL_SOF, x) 1051 #define QS_INJ_CTRL_SOF_GET(x)\ 1052 FIELD_GET(QS_INJ_CTRL_SOF, x) 1053 1054 #define QS_INJ_CTRL_VLD_BYTES GENMASK(17, 16) 1055 #define QS_INJ_CTRL_VLD_BYTES_SET(x)\ 1056 FIELD_PREP(QS_INJ_CTRL_VLD_BYTES, x) 1057 #define QS_INJ_CTRL_VLD_BYTES_GET(x)\ 1058 FIELD_GET(QS_INJ_CTRL_VLD_BYTES, x) 1059 1060 /* DEVCPU_QS:INJ:INJ_STATUS */ 1061 #define QS_INJ_STATUS __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 24, 0, 1, 4) 1062 1063 #define QS_INJ_STATUS_WMARK_REACHED GENMASK(5, 4) 1064 #define QS_INJ_STATUS_WMARK_REACHED_SET(x)\ 1065 FIELD_PREP(QS_INJ_STATUS_WMARK_REACHED, x) 1066 #define QS_INJ_STATUS_WMARK_REACHED_GET(x)\ 1067 FIELD_GET(QS_INJ_STATUS_WMARK_REACHED, x) 1068 1069 #define QS_INJ_STATUS_FIFO_RDY GENMASK(3, 2) 1070 #define QS_INJ_STATUS_FIFO_RDY_SET(x)\ 1071 FIELD_PREP(QS_INJ_STATUS_FIFO_RDY, x) 1072 #define QS_INJ_STATUS_FIFO_RDY_GET(x)\ 1073 FIELD_GET(QS_INJ_STATUS_FIFO_RDY, x) 1074 1075 /* QSYS:SYSTEM:PORT_MODE */ 1076 #define QSYS_PORT_MODE(r) __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 0, r, 10, 4) 1077 1078 #define QSYS_PORT_MODE_DEQUEUE_DIS BIT(1) 1079 #define QSYS_PORT_MODE_DEQUEUE_DIS_SET(x)\ 1080 FIELD_PREP(QSYS_PORT_MODE_DEQUEUE_DIS, x) 1081 #define QSYS_PORT_MODE_DEQUEUE_DIS_GET(x)\ 1082 FIELD_GET(QSYS_PORT_MODE_DEQUEUE_DIS, x) 1083 1084 /* QSYS:SYSTEM:SWITCH_PORT_MODE */ 1085 #define QSYS_SW_PORT_MODE(r) __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 80, r, 9, 4) 1086 1087 #define QSYS_SW_PORT_MODE_PORT_ENA BIT(18) 1088 #define QSYS_SW_PORT_MODE_PORT_ENA_SET(x)\ 1089 FIELD_PREP(QSYS_SW_PORT_MODE_PORT_ENA, x) 1090 #define QSYS_SW_PORT_MODE_PORT_ENA_GET(x)\ 1091 FIELD_GET(QSYS_SW_PORT_MODE_PORT_ENA, x) 1092 1093 #define QSYS_SW_PORT_MODE_SCH_NEXT_CFG GENMASK(16, 14) 1094 #define QSYS_SW_PORT_MODE_SCH_NEXT_CFG_SET(x)\ 1095 FIELD_PREP(QSYS_SW_PORT_MODE_SCH_NEXT_CFG, x) 1096 #define QSYS_SW_PORT_MODE_SCH_NEXT_CFG_GET(x)\ 1097 FIELD_GET(QSYS_SW_PORT_MODE_SCH_NEXT_CFG, x) 1098 1099 #define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE BIT(12) 1100 #define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE_SET(x)\ 1101 FIELD_PREP(QSYS_SW_PORT_MODE_INGRESS_DROP_MODE, x) 1102 #define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE_GET(x)\ 1103 FIELD_GET(QSYS_SW_PORT_MODE_INGRESS_DROP_MODE, x) 1104 1105 #define QSYS_SW_PORT_MODE_TX_PFC_ENA GENMASK(11, 4) 1106 #define QSYS_SW_PORT_MODE_TX_PFC_ENA_SET(x)\ 1107 FIELD_PREP(QSYS_SW_PORT_MODE_TX_PFC_ENA, x) 1108 #define QSYS_SW_PORT_MODE_TX_PFC_ENA_GET(x)\ 1109 FIELD_GET(QSYS_SW_PORT_MODE_TX_PFC_ENA, x) 1110 1111 #define QSYS_SW_PORT_MODE_AGING_MODE GENMASK(1, 0) 1112 #define QSYS_SW_PORT_MODE_AGING_MODE_SET(x)\ 1113 FIELD_PREP(QSYS_SW_PORT_MODE_AGING_MODE, x) 1114 #define QSYS_SW_PORT_MODE_AGING_MODE_GET(x)\ 1115 FIELD_GET(QSYS_SW_PORT_MODE_AGING_MODE, x) 1116 1117 /* QSYS:SYSTEM:SW_STATUS */ 1118 #define QSYS_SW_STATUS(r) __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 164, r, 9, 4) 1119 1120 #define QSYS_SW_STATUS_EQ_AVAIL GENMASK(7, 0) 1121 #define QSYS_SW_STATUS_EQ_AVAIL_SET(x)\ 1122 FIELD_PREP(QSYS_SW_STATUS_EQ_AVAIL, x) 1123 #define QSYS_SW_STATUS_EQ_AVAIL_GET(x)\ 1124 FIELD_GET(QSYS_SW_STATUS_EQ_AVAIL, x) 1125 1126 /* QSYS:SYSTEM:CPU_GROUP_MAP */ 1127 #define QSYS_CPU_GROUP_MAP __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 204, 0, 1, 4) 1128 1129 /* QSYS:RES_CTRL:RES_CFG */ 1130 #define QSYS_RES_CFG(g) __REG(TARGET_QSYS, 0, 1, 32768, g, 1024, 8, 0, 0, 1, 4) 1131 1132 /* QSYS:HSCH:CIR_CFG */ 1133 #define QSYS_CIR_CFG(g) __REG(TARGET_QSYS, 0, 1, 16384, g, 90, 128, 0, 0, 1, 4) 1134 1135 #define QSYS_CIR_CFG_CIR_RATE GENMASK(20, 6) 1136 #define QSYS_CIR_CFG_CIR_RATE_SET(x)\ 1137 FIELD_PREP(QSYS_CIR_CFG_CIR_RATE, x) 1138 #define QSYS_CIR_CFG_CIR_RATE_GET(x)\ 1139 FIELD_GET(QSYS_CIR_CFG_CIR_RATE, x) 1140 1141 #define QSYS_CIR_CFG_CIR_BURST GENMASK(5, 0) 1142 #define QSYS_CIR_CFG_CIR_BURST_SET(x)\ 1143 FIELD_PREP(QSYS_CIR_CFG_CIR_BURST, x) 1144 #define QSYS_CIR_CFG_CIR_BURST_GET(x)\ 1145 FIELD_GET(QSYS_CIR_CFG_CIR_BURST, x) 1146 1147 /* QSYS:HSCH:SE_CFG */ 1148 #define QSYS_SE_CFG(g) __REG(TARGET_QSYS, 0, 1, 16384, g, 90, 128, 8, 0, 1, 4) 1149 1150 #define QSYS_SE_CFG_SE_DWRR_CNT GENMASK(9, 6) 1151 #define QSYS_SE_CFG_SE_DWRR_CNT_SET(x)\ 1152 FIELD_PREP(QSYS_SE_CFG_SE_DWRR_CNT, x) 1153 #define QSYS_SE_CFG_SE_DWRR_CNT_GET(x)\ 1154 FIELD_GET(QSYS_SE_CFG_SE_DWRR_CNT, x) 1155 1156 #define QSYS_SE_CFG_SE_RR_ENA BIT(5) 1157 #define QSYS_SE_CFG_SE_RR_ENA_SET(x)\ 1158 FIELD_PREP(QSYS_SE_CFG_SE_RR_ENA, x) 1159 #define QSYS_SE_CFG_SE_RR_ENA_GET(x)\ 1160 FIELD_GET(QSYS_SE_CFG_SE_RR_ENA, x) 1161 1162 #define QSYS_SE_CFG_SE_AVB_ENA BIT(4) 1163 #define QSYS_SE_CFG_SE_AVB_ENA_SET(x)\ 1164 FIELD_PREP(QSYS_SE_CFG_SE_AVB_ENA, x) 1165 #define QSYS_SE_CFG_SE_AVB_ENA_GET(x)\ 1166 FIELD_GET(QSYS_SE_CFG_SE_AVB_ENA, x) 1167 1168 #define QSYS_SE_CFG_SE_FRM_MODE GENMASK(3, 2) 1169 #define QSYS_SE_CFG_SE_FRM_MODE_SET(x)\ 1170 FIELD_PREP(QSYS_SE_CFG_SE_FRM_MODE, x) 1171 #define QSYS_SE_CFG_SE_FRM_MODE_GET(x)\ 1172 FIELD_GET(QSYS_SE_CFG_SE_FRM_MODE, x) 1173 1174 #define QSYS_SE_DWRR_CFG(g, r) __REG(TARGET_QSYS, 0, 1, 16384, g, 90, 128, 12, r, 12, 4) 1175 1176 #define QSYS_SE_DWRR_CFG_DWRR_COST GENMASK(4, 0) 1177 #define QSYS_SE_DWRR_CFG_DWRR_COST_SET(x)\ 1178 FIELD_PREP(QSYS_SE_DWRR_CFG_DWRR_COST, x) 1179 #define QSYS_SE_DWRR_CFG_DWRR_COST_GET(x)\ 1180 FIELD_GET(QSYS_SE_DWRR_CFG_DWRR_COST, x) 1181 1182 /* QSYS:TAS_CONFIG:TAS_CFG_CTRL */ 1183 #define QSYS_TAS_CFG_CTRL __REG(TARGET_QSYS, 0, 1, 57372, 0, 1, 12, 0, 0, 1, 4) 1184 1185 #define QSYS_TAS_CFG_CTRL_LIST_NUM_MAX GENMASK(27, 23) 1186 #define QSYS_TAS_CFG_CTRL_LIST_NUM_MAX_SET(x)\ 1187 FIELD_PREP(QSYS_TAS_CFG_CTRL_LIST_NUM_MAX, x) 1188 #define QSYS_TAS_CFG_CTRL_LIST_NUM_MAX_GET(x)\ 1189 FIELD_GET(QSYS_TAS_CFG_CTRL_LIST_NUM_MAX, x) 1190 1191 #define QSYS_TAS_CFG_CTRL_LIST_NUM GENMASK(22, 18) 1192 #define QSYS_TAS_CFG_CTRL_LIST_NUM_SET(x)\ 1193 FIELD_PREP(QSYS_TAS_CFG_CTRL_LIST_NUM, x) 1194 #define QSYS_TAS_CFG_CTRL_LIST_NUM_GET(x)\ 1195 FIELD_GET(QSYS_TAS_CFG_CTRL_LIST_NUM, x) 1196 1197 #define QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q BIT(17) 1198 #define QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q_SET(x)\ 1199 FIELD_PREP(QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q, x) 1200 #define QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q_GET(x)\ 1201 FIELD_GET(QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q, x) 1202 1203 #define QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM GENMASK(16, 5) 1204 #define QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM_SET(x)\ 1205 FIELD_PREP(QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM, x) 1206 #define QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM_GET(x)\ 1207 FIELD_GET(QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM, x) 1208 1209 /* QSYS:TAS_CONFIG:TAS_GATE_STATE_CTRL */ 1210 #define QSYS_TAS_GS_CTRL __REG(TARGET_QSYS, 0, 1, 57372, 0, 1, 12, 4, 0, 1, 4) 1211 1212 #define QSYS_TAS_GS_CTRL_HSCH_POS GENMASK(2, 0) 1213 #define QSYS_TAS_GS_CTRL_HSCH_POS_SET(x)\ 1214 FIELD_PREP(QSYS_TAS_GS_CTRL_HSCH_POS, x) 1215 #define QSYS_TAS_GS_CTRL_HSCH_POS_GET(x)\ 1216 FIELD_GET(QSYS_TAS_GS_CTRL_HSCH_POS, x) 1217 1218 /* QSYS:TAS_CONFIG:TAS_STATEMACHINE_CFG */ 1219 #define QSYS_TAS_STM_CFG __REG(TARGET_QSYS, 0, 1, 57372, 0, 1, 12, 8, 0, 1, 4) 1220 1221 #define QSYS_TAS_STM_CFG_REVISIT_DLY GENMASK(7, 0) 1222 #define QSYS_TAS_STM_CFG_REVISIT_DLY_SET(x)\ 1223 FIELD_PREP(QSYS_TAS_STM_CFG_REVISIT_DLY, x) 1224 #define QSYS_TAS_STM_CFG_REVISIT_DLY_GET(x)\ 1225 FIELD_GET(QSYS_TAS_STM_CFG_REVISIT_DLY, x) 1226 1227 /* QSYS:TAS_PROFILE_CFG:TAS_PROFILE_CONFIG */ 1228 #define QSYS_TAS_PROFILE_CFG(g) __REG(TARGET_QSYS, 0, 1, 30720, g, 16, 64, 32, 0, 1, 4) 1229 1230 #define QSYS_TAS_PROFILE_CFG_PORT_NUM GENMASK(21, 19) 1231 #define QSYS_TAS_PROFILE_CFG_PORT_NUM_SET(x)\ 1232 FIELD_PREP(QSYS_TAS_PROFILE_CFG_PORT_NUM, x) 1233 #define QSYS_TAS_PROFILE_CFG_PORT_NUM_GET(x)\ 1234 FIELD_GET(QSYS_TAS_PROFILE_CFG_PORT_NUM, x) 1235 1236 #define QSYS_TAS_PROFILE_CFG_LINK_SPEED GENMASK(18, 16) 1237 #define QSYS_TAS_PROFILE_CFG_LINK_SPEED_SET(x)\ 1238 FIELD_PREP(QSYS_TAS_PROFILE_CFG_LINK_SPEED, x) 1239 #define QSYS_TAS_PROFILE_CFG_LINK_SPEED_GET(x)\ 1240 FIELD_GET(QSYS_TAS_PROFILE_CFG_LINK_SPEED, x) 1241 1242 /* QSYS:TAS_LIST_CFG:TAS_BASE_TIME_NSEC */ 1243 #define QSYS_TAS_BT_NSEC __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 0, 0, 1, 4) 1244 1245 #define QSYS_TAS_BT_NSEC_NSEC GENMASK(29, 0) 1246 #define QSYS_TAS_BT_NSEC_NSEC_SET(x)\ 1247 FIELD_PREP(QSYS_TAS_BT_NSEC_NSEC, x) 1248 #define QSYS_TAS_BT_NSEC_NSEC_GET(x)\ 1249 FIELD_GET(QSYS_TAS_BT_NSEC_NSEC, x) 1250 1251 /* QSYS:TAS_LIST_CFG:TAS_BASE_TIME_SEC_LSB */ 1252 #define QSYS_TAS_BT_SEC_LSB __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 4, 0, 1, 4) 1253 1254 /* QSYS:TAS_LIST_CFG:TAS_BASE_TIME_SEC_MSB */ 1255 #define QSYS_TAS_BT_SEC_MSB __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 8, 0, 1, 4) 1256 1257 #define QSYS_TAS_BT_SEC_MSB_SEC_MSB GENMASK(15, 0) 1258 #define QSYS_TAS_BT_SEC_MSB_SEC_MSB_SET(x)\ 1259 FIELD_PREP(QSYS_TAS_BT_SEC_MSB_SEC_MSB, x) 1260 #define QSYS_TAS_BT_SEC_MSB_SEC_MSB_GET(x)\ 1261 FIELD_GET(QSYS_TAS_BT_SEC_MSB_SEC_MSB, x) 1262 1263 /* QSYS:TAS_LIST_CFG:TAS_CYCLE_TIME_CFG */ 1264 #define QSYS_TAS_CT_CFG __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 24, 0, 1, 4) 1265 1266 /* QSYS:TAS_LIST_CFG:TAS_STARTUP_CFG */ 1267 #define QSYS_TAS_STARTUP_CFG __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 28, 0, 1, 4) 1268 1269 #define QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX GENMASK(27, 23) 1270 #define QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX_SET(x)\ 1271 FIELD_PREP(QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX, x) 1272 #define QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX_GET(x)\ 1273 FIELD_GET(QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX, x) 1274 1275 /* QSYS:TAS_LIST_CFG:TAS_LIST_CFG */ 1276 #define QSYS_TAS_LIST_CFG __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 32, 0, 1, 4) 1277 1278 #define QSYS_TAS_LIST_CFG_LIST_BASE_ADDR GENMASK(11, 0) 1279 #define QSYS_TAS_LIST_CFG_LIST_BASE_ADDR_SET(x)\ 1280 FIELD_PREP(QSYS_TAS_LIST_CFG_LIST_BASE_ADDR, x) 1281 #define QSYS_TAS_LIST_CFG_LIST_BASE_ADDR_GET(x)\ 1282 FIELD_GET(QSYS_TAS_LIST_CFG_LIST_BASE_ADDR, x) 1283 1284 /* QSYS:TAS_LIST_CFG:TAS_LIST_STATE */ 1285 #define QSYS_TAS_LST __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 36, 0, 1, 4) 1286 1287 #define QSYS_TAS_LST_LIST_STATE GENMASK(2, 0) 1288 #define QSYS_TAS_LST_LIST_STATE_SET(x)\ 1289 FIELD_PREP(QSYS_TAS_LST_LIST_STATE, x) 1290 #define QSYS_TAS_LST_LIST_STATE_GET(x)\ 1291 FIELD_GET(QSYS_TAS_LST_LIST_STATE, x) 1292 1293 /* QSYS:TAS_GCL_CFG:TAS_GCL_CTRL_CFG */ 1294 #define QSYS_TAS_GCL_CT_CFG __REG(TARGET_QSYS, 0, 1, 27968, 0, 1, 16, 0, 0, 1, 4) 1295 1296 #define QSYS_TAS_GCL_CT_CFG_HSCH_POS GENMASK(12, 10) 1297 #define QSYS_TAS_GCL_CT_CFG_HSCH_POS_SET(x)\ 1298 FIELD_PREP(QSYS_TAS_GCL_CT_CFG_HSCH_POS, x) 1299 #define QSYS_TAS_GCL_CT_CFG_HSCH_POS_GET(x)\ 1300 FIELD_GET(QSYS_TAS_GCL_CT_CFG_HSCH_POS, x) 1301 1302 #define QSYS_TAS_GCL_CT_CFG_GATE_STATE GENMASK(9, 2) 1303 #define QSYS_TAS_GCL_CT_CFG_GATE_STATE_SET(x)\ 1304 FIELD_PREP(QSYS_TAS_GCL_CT_CFG_GATE_STATE, x) 1305 #define QSYS_TAS_GCL_CT_CFG_GATE_STATE_GET(x)\ 1306 FIELD_GET(QSYS_TAS_GCL_CT_CFG_GATE_STATE, x) 1307 1308 #define QSYS_TAS_GCL_CT_CFG_OP_TYPE GENMASK(1, 0) 1309 #define QSYS_TAS_GCL_CT_CFG_OP_TYPE_SET(x)\ 1310 FIELD_PREP(QSYS_TAS_GCL_CT_CFG_OP_TYPE, x) 1311 #define QSYS_TAS_GCL_CT_CFG_OP_TYPE_GET(x)\ 1312 FIELD_GET(QSYS_TAS_GCL_CT_CFG_OP_TYPE, x) 1313 1314 /* QSYS:TAS_GCL_CFG:TAS_GCL_CTRL_CFG2 */ 1315 #define QSYS_TAS_GCL_CT_CFG2 __REG(TARGET_QSYS, 0, 1, 27968, 0, 1, 16, 4, 0, 1, 4) 1316 1317 #define QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE GENMASK(15, 12) 1318 #define QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE_SET(x)\ 1319 FIELD_PREP(QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE, x) 1320 #define QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE_GET(x)\ 1321 FIELD_GET(QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE, x) 1322 1323 #define QSYS_TAS_GCL_CT_CFG2_NEXT_GCL GENMASK(11, 0) 1324 #define QSYS_TAS_GCL_CT_CFG2_NEXT_GCL_SET(x)\ 1325 FIELD_PREP(QSYS_TAS_GCL_CT_CFG2_NEXT_GCL, x) 1326 #define QSYS_TAS_GCL_CT_CFG2_NEXT_GCL_GET(x)\ 1327 FIELD_GET(QSYS_TAS_GCL_CT_CFG2_NEXT_GCL, x) 1328 1329 /* QSYS:TAS_GCL_CFG:TAS_GCL_TIME_CFG */ 1330 #define QSYS_TAS_GCL_TM_CFG __REG(TARGET_QSYS, 0, 1, 27968, 0, 1, 16, 8, 0, 1, 4) 1331 1332 /* QSYS:HSCH_TAS_STATE:TAS_GATE_STATE */ 1333 #define QSYS_TAS_GATE_STATE __REG(TARGET_QSYS, 0, 1, 28004, 0, 1, 4, 0, 0, 1, 4) 1334 1335 #define QSYS_TAS_GATE_STATE_TAS_GATE_STATE GENMASK(7, 0) 1336 #define QSYS_TAS_GATE_STATE_TAS_GATE_STATE_SET(x)\ 1337 FIELD_PREP(QSYS_TAS_GATE_STATE_TAS_GATE_STATE, x) 1338 #define QSYS_TAS_GATE_STATE_TAS_GATE_STATE_GET(x)\ 1339 FIELD_GET(QSYS_TAS_GATE_STATE_TAS_GATE_STATE, x) 1340 1341 /* REW:PORT:PORT_VLAN_CFG */ 1342 #define REW_PORT_VLAN_CFG(g) __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 0, 0, 1, 4) 1343 1344 #define REW_PORT_VLAN_CFG_PORT_TPID GENMASK(31, 16) 1345 #define REW_PORT_VLAN_CFG_PORT_TPID_SET(x)\ 1346 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_TPID, x) 1347 #define REW_PORT_VLAN_CFG_PORT_TPID_GET(x)\ 1348 FIELD_GET(REW_PORT_VLAN_CFG_PORT_TPID, x) 1349 1350 #define REW_PORT_VLAN_CFG_PORT_VID GENMASK(11, 0) 1351 #define REW_PORT_VLAN_CFG_PORT_VID_SET(x)\ 1352 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_VID, x) 1353 #define REW_PORT_VLAN_CFG_PORT_VID_GET(x)\ 1354 FIELD_GET(REW_PORT_VLAN_CFG_PORT_VID, x) 1355 1356 /* REW:PORT:TAG_CFG */ 1357 #define REW_TAG_CFG(g) __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 4, 0, 1, 4) 1358 1359 #define REW_TAG_CFG_TAG_CFG GENMASK(8, 7) 1360 #define REW_TAG_CFG_TAG_CFG_SET(x)\ 1361 FIELD_PREP(REW_TAG_CFG_TAG_CFG, x) 1362 #define REW_TAG_CFG_TAG_CFG_GET(x)\ 1363 FIELD_GET(REW_TAG_CFG_TAG_CFG, x) 1364 1365 #define REW_TAG_CFG_TAG_TPID_CFG GENMASK(6, 5) 1366 #define REW_TAG_CFG_TAG_TPID_CFG_SET(x)\ 1367 FIELD_PREP(REW_TAG_CFG_TAG_TPID_CFG, x) 1368 #define REW_TAG_CFG_TAG_TPID_CFG_GET(x)\ 1369 FIELD_GET(REW_TAG_CFG_TAG_TPID_CFG, x) 1370 1371 /* REW:PORT:PORT_CFG */ 1372 #define REW_PORT_CFG(g) __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 8, 0, 1, 4) 1373 1374 #define REW_PORT_CFG_NO_REWRITE BIT(0) 1375 #define REW_PORT_CFG_NO_REWRITE_SET(x)\ 1376 FIELD_PREP(REW_PORT_CFG_NO_REWRITE, x) 1377 #define REW_PORT_CFG_NO_REWRITE_GET(x)\ 1378 FIELD_GET(REW_PORT_CFG_NO_REWRITE, x) 1379 1380 /* SYS:SYSTEM:RESET_CFG */ 1381 #define SYS_RESET_CFG __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 0, 0, 1, 4) 1382 1383 #define SYS_RESET_CFG_CORE_ENA BIT(0) 1384 #define SYS_RESET_CFG_CORE_ENA_SET(x)\ 1385 FIELD_PREP(SYS_RESET_CFG_CORE_ENA, x) 1386 #define SYS_RESET_CFG_CORE_ENA_GET(x)\ 1387 FIELD_GET(SYS_RESET_CFG_CORE_ENA, x) 1388 1389 /* SYS:SYSTEM:PORT_MODE */ 1390 #define SYS_PORT_MODE(r) __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 44, r, 10, 4) 1391 1392 #define SYS_PORT_MODE_INCL_INJ_HDR GENMASK(5, 4) 1393 #define SYS_PORT_MODE_INCL_INJ_HDR_SET(x)\ 1394 FIELD_PREP(SYS_PORT_MODE_INCL_INJ_HDR, x) 1395 #define SYS_PORT_MODE_INCL_INJ_HDR_GET(x)\ 1396 FIELD_GET(SYS_PORT_MODE_INCL_INJ_HDR, x) 1397 1398 #define SYS_PORT_MODE_INCL_XTR_HDR GENMASK(3, 2) 1399 #define SYS_PORT_MODE_INCL_XTR_HDR_SET(x)\ 1400 FIELD_PREP(SYS_PORT_MODE_INCL_XTR_HDR, x) 1401 #define SYS_PORT_MODE_INCL_XTR_HDR_GET(x)\ 1402 FIELD_GET(SYS_PORT_MODE_INCL_XTR_HDR, x) 1403 1404 /* SYS:SYSTEM:FRONT_PORT_MODE */ 1405 #define SYS_FRONT_PORT_MODE(r) __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 84, r, 8, 4) 1406 1407 #define SYS_FRONT_PORT_MODE_HDX_MODE BIT(1) 1408 #define SYS_FRONT_PORT_MODE_HDX_MODE_SET(x)\ 1409 FIELD_PREP(SYS_FRONT_PORT_MODE_HDX_MODE, x) 1410 #define SYS_FRONT_PORT_MODE_HDX_MODE_GET(x)\ 1411 FIELD_GET(SYS_FRONT_PORT_MODE_HDX_MODE, x) 1412 1413 /* SYS:SYSTEM:FRM_AGING */ 1414 #define SYS_FRM_AGING __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 116, 0, 1, 4) 1415 1416 #define SYS_FRM_AGING_AGE_TX_ENA BIT(20) 1417 #define SYS_FRM_AGING_AGE_TX_ENA_SET(x)\ 1418 FIELD_PREP(SYS_FRM_AGING_AGE_TX_ENA, x) 1419 #define SYS_FRM_AGING_AGE_TX_ENA_GET(x)\ 1420 FIELD_GET(SYS_FRM_AGING_AGE_TX_ENA, x) 1421 1422 /* SYS:SYSTEM:STAT_CFG */ 1423 #define SYS_STAT_CFG __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 120, 0, 1, 4) 1424 1425 #define SYS_STAT_CFG_STAT_VIEW GENMASK(9, 0) 1426 #define SYS_STAT_CFG_STAT_VIEW_SET(x)\ 1427 FIELD_PREP(SYS_STAT_CFG_STAT_VIEW, x) 1428 #define SYS_STAT_CFG_STAT_VIEW_GET(x)\ 1429 FIELD_GET(SYS_STAT_CFG_STAT_VIEW, x) 1430 1431 /* SYS:PAUSE_CFG:PAUSE_CFG */ 1432 #define SYS_PAUSE_CFG(r) __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 0, r, 9, 4) 1433 1434 #define SYS_PAUSE_CFG_PAUSE_START GENMASK(18, 10) 1435 #define SYS_PAUSE_CFG_PAUSE_START_SET(x)\ 1436 FIELD_PREP(SYS_PAUSE_CFG_PAUSE_START, x) 1437 #define SYS_PAUSE_CFG_PAUSE_START_GET(x)\ 1438 FIELD_GET(SYS_PAUSE_CFG_PAUSE_START, x) 1439 1440 #define SYS_PAUSE_CFG_PAUSE_STOP GENMASK(9, 1) 1441 #define SYS_PAUSE_CFG_PAUSE_STOP_SET(x)\ 1442 FIELD_PREP(SYS_PAUSE_CFG_PAUSE_STOP, x) 1443 #define SYS_PAUSE_CFG_PAUSE_STOP_GET(x)\ 1444 FIELD_GET(SYS_PAUSE_CFG_PAUSE_STOP, x) 1445 1446 #define SYS_PAUSE_CFG_PAUSE_ENA BIT(0) 1447 #define SYS_PAUSE_CFG_PAUSE_ENA_SET(x)\ 1448 FIELD_PREP(SYS_PAUSE_CFG_PAUSE_ENA, x) 1449 #define SYS_PAUSE_CFG_PAUSE_ENA_GET(x)\ 1450 FIELD_GET(SYS_PAUSE_CFG_PAUSE_ENA, x) 1451 1452 /* SYS:PAUSE_CFG:ATOP */ 1453 #define SYS_ATOP(r) __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 40, r, 9, 4) 1454 1455 /* SYS:PAUSE_CFG:ATOP_TOT_CFG */ 1456 #define SYS_ATOP_TOT_CFG __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 76, 0, 1, 4) 1457 1458 /* SYS:PAUSE_CFG:MAC_FC_CFG */ 1459 #define SYS_MAC_FC_CFG(r) __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 80, r, 8, 4) 1460 1461 #define SYS_MAC_FC_CFG_FC_LINK_SPEED GENMASK(27, 26) 1462 #define SYS_MAC_FC_CFG_FC_LINK_SPEED_SET(x)\ 1463 FIELD_PREP(SYS_MAC_FC_CFG_FC_LINK_SPEED, x) 1464 #define SYS_MAC_FC_CFG_FC_LINK_SPEED_GET(x)\ 1465 FIELD_GET(SYS_MAC_FC_CFG_FC_LINK_SPEED, x) 1466 1467 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG GENMASK(25, 20) 1468 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_SET(x)\ 1469 FIELD_PREP(SYS_MAC_FC_CFG_FC_LATENCY_CFG, x) 1470 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_GET(x)\ 1471 FIELD_GET(SYS_MAC_FC_CFG_FC_LATENCY_CFG, x) 1472 1473 #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA BIT(18) 1474 #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA_SET(x)\ 1475 FIELD_PREP(SYS_MAC_FC_CFG_ZERO_PAUSE_ENA, x) 1476 #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA_GET(x)\ 1477 FIELD_GET(SYS_MAC_FC_CFG_ZERO_PAUSE_ENA, x) 1478 1479 #define SYS_MAC_FC_CFG_TX_FC_ENA BIT(17) 1480 #define SYS_MAC_FC_CFG_TX_FC_ENA_SET(x)\ 1481 FIELD_PREP(SYS_MAC_FC_CFG_TX_FC_ENA, x) 1482 #define SYS_MAC_FC_CFG_TX_FC_ENA_GET(x)\ 1483 FIELD_GET(SYS_MAC_FC_CFG_TX_FC_ENA, x) 1484 1485 #define SYS_MAC_FC_CFG_RX_FC_ENA BIT(16) 1486 #define SYS_MAC_FC_CFG_RX_FC_ENA_SET(x)\ 1487 FIELD_PREP(SYS_MAC_FC_CFG_RX_FC_ENA, x) 1488 #define SYS_MAC_FC_CFG_RX_FC_ENA_GET(x)\ 1489 FIELD_GET(SYS_MAC_FC_CFG_RX_FC_ENA, x) 1490 1491 #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG GENMASK(15, 0) 1492 #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_SET(x)\ 1493 FIELD_PREP(SYS_MAC_FC_CFG_PAUSE_VAL_CFG, x) 1494 #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_GET(x)\ 1495 FIELD_GET(SYS_MAC_FC_CFG_PAUSE_VAL_CFG, x) 1496 1497 /* SYS:STAT:CNT */ 1498 #define SYS_CNT(g) __REG(TARGET_SYS, 0, 1, 0, g, 896, 4, 0, 0, 1, 4) 1499 1500 /* SYS:RAM_CTRL:RAM_INIT */ 1501 #define SYS_RAM_INIT __REG(TARGET_SYS, 0, 1, 4432, 0, 1, 4, 0, 0, 1, 4) 1502 1503 #define SYS_RAM_INIT_RAM_INIT BIT(1) 1504 #define SYS_RAM_INIT_RAM_INIT_SET(x)\ 1505 FIELD_PREP(SYS_RAM_INIT_RAM_INIT, x) 1506 #define SYS_RAM_INIT_RAM_INIT_GET(x)\ 1507 FIELD_GET(SYS_RAM_INIT_RAM_INIT, x) 1508 1509 #endif /* _LAN966X_REGS_H_ */ 1510