1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * ADRF6780 driver
4  *
5  * Copyright 2021 Analog Devices Inc.
6  */
7 
8 #include <linux/bitfield.h>
9 #include <linux/bits.h>
10 #include <linux/clk.h>
11 #include <linux/clkdev.h>
12 #include <linux/clk-provider.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/iio/iio.h>
16 #include <linux/module.h>
17 #include <linux/mod_devicetable.h>
18 #include <linux/spi/spi.h>
19 
20 #include <asm/unaligned.h>
21 
22 /* ADRF6780 Register Map */
23 #define ADRF6780_REG_CONTROL			0x00
24 #define ADRF6780_REG_ALARM_READBACK		0x01
25 #define ADRF6780_REG_ALARM_MASKS		0x02
26 #define ADRF6780_REG_ENABLE			0x03
27 #define ADRF6780_REG_LINEARIZE			0x04
28 #define ADRF6780_REG_LO_PATH			0x05
29 #define ADRF6780_REG_ADC_CONTROL		0x06
30 #define ADRF6780_REG_ADC_OUTPUT			0x0C
31 
32 /* ADRF6780_REG_CONTROL Map */
33 #define ADRF6780_PARITY_EN_MSK			BIT(15)
34 #define ADRF6780_SOFT_RESET_MSK			BIT(14)
35 #define ADRF6780_CHIP_ID_MSK			GENMASK(11, 4)
36 #define ADRF6780_CHIP_ID			0xA
37 #define ADRF6780_CHIP_REVISION_MSK		GENMASK(3, 0)
38 
39 /* ADRF6780_REG_ALARM_READBACK Map */
40 #define ADRF6780_PARITY_ERROR_MSK		BIT(15)
41 #define ADRF6780_TOO_FEW_ERRORS_MSK		BIT(14)
42 #define ADRF6780_TOO_MANY_ERRORS_MSK		BIT(13)
43 #define ADRF6780_ADDRESS_RANGE_ERROR_MSK	BIT(12)
44 
45 /* ADRF6780_REG_ENABLE Map */
46 #define ADRF6780_VGA_BUFFER_EN_MSK		BIT(8)
47 #define ADRF6780_DETECTOR_EN_MSK		BIT(7)
48 #define ADRF6780_LO_BUFFER_EN_MSK		BIT(6)
49 #define ADRF6780_IF_MODE_EN_MSK			BIT(5)
50 #define ADRF6780_IQ_MODE_EN_MSK			BIT(4)
51 #define ADRF6780_LO_X2_EN_MSK			BIT(3)
52 #define ADRF6780_LO_PPF_EN_MSK			BIT(2)
53 #define ADRF6780_LO_EN_MSK			BIT(1)
54 #define ADRF6780_UC_BIAS_EN_MSK			BIT(0)
55 
56 /* ADRF6780_REG_LINEARIZE Map */
57 #define ADRF6780_RDAC_LINEARIZE_MSK		GENMASK(7, 0)
58 
59 /* ADRF6780_REG_LO_PATH Map */
60 #define ADRF6780_LO_SIDEBAND_MSK		BIT(10)
61 #define ADRF6780_Q_PATH_PHASE_ACCURACY_MSK	GENMASK(7, 4)
62 #define ADRF6780_I_PATH_PHASE_ACCURACY_MSK	GENMASK(3, 0)
63 
64 /* ADRF6780_REG_ADC_CONTROL Map */
65 #define ADRF6780_VDET_OUTPUT_SELECT_MSK		BIT(3)
66 #define ADRF6780_ADC_START_MSK			BIT(2)
67 #define ADRF6780_ADC_EN_MSK			BIT(1)
68 #define ADRF6780_ADC_CLOCK_EN_MSK		BIT(0)
69 
70 /* ADRF6780_REG_ADC_OUTPUT Map */
71 #define ADRF6780_ADC_STATUS_MSK			BIT(8)
72 #define ADRF6780_ADC_VALUE_MSK			GENMASK(7, 0)
73 
74 struct adrf6780_state {
75 	struct spi_device	*spi;
76 	struct clk		*clkin;
77 	/* Protect against concurrent accesses to the device */
78 	struct mutex		lock;
79 	bool			vga_buff_en;
80 	bool			lo_buff_en;
81 	bool			if_mode_en;
82 	bool			iq_mode_en;
83 	bool			lo_x2_en;
84 	bool			lo_ppf_en;
85 	bool			lo_en;
86 	bool			uc_bias_en;
87 	bool			lo_sideband;
88 	bool			vdet_out_en;
89 	u8			data[3] __aligned(IIO_DMA_MINALIGN);
90 };
91 
__adrf6780_spi_read(struct adrf6780_state * st,unsigned int reg,unsigned int * val)92 static int __adrf6780_spi_read(struct adrf6780_state *st, unsigned int reg,
93 			       unsigned int *val)
94 {
95 	int ret;
96 	struct spi_transfer t = {0};
97 
98 	st->data[0] = 0x80 | (reg << 1);
99 	st->data[1] = 0x0;
100 	st->data[2] = 0x0;
101 
102 	t.rx_buf = &st->data[0];
103 	t.tx_buf = &st->data[0];
104 	t.len = 3;
105 
106 	ret = spi_sync_transfer(st->spi, &t, 1);
107 	if (ret)
108 		return ret;
109 
110 	*val = (get_unaligned_be24(&st->data[0]) >> 1) & GENMASK(15, 0);
111 
112 	return ret;
113 }
114 
adrf6780_spi_read(struct adrf6780_state * st,unsigned int reg,unsigned int * val)115 static int adrf6780_spi_read(struct adrf6780_state *st, unsigned int reg,
116 			     unsigned int *val)
117 {
118 	int ret;
119 
120 	mutex_lock(&st->lock);
121 	ret = __adrf6780_spi_read(st, reg, val);
122 	mutex_unlock(&st->lock);
123 
124 	return ret;
125 }
126 
__adrf6780_spi_write(struct adrf6780_state * st,unsigned int reg,unsigned int val)127 static int __adrf6780_spi_write(struct adrf6780_state *st,
128 				unsigned int reg,
129 				unsigned int val)
130 {
131 	put_unaligned_be24((val << 1) | (reg << 17), &st->data[0]);
132 
133 	return spi_write(st->spi, &st->data[0], 3);
134 }
135 
adrf6780_spi_write(struct adrf6780_state * st,unsigned int reg,unsigned int val)136 static int adrf6780_spi_write(struct adrf6780_state *st, unsigned int reg,
137 			      unsigned int val)
138 {
139 	int ret;
140 
141 	mutex_lock(&st->lock);
142 	ret = __adrf6780_spi_write(st, reg, val);
143 	mutex_unlock(&st->lock);
144 
145 	return ret;
146 }
147 
__adrf6780_spi_update_bits(struct adrf6780_state * st,unsigned int reg,unsigned int mask,unsigned int val)148 static int __adrf6780_spi_update_bits(struct adrf6780_state *st,
149 				      unsigned int reg, unsigned int mask,
150 				      unsigned int val)
151 {
152 	int ret;
153 	unsigned int data, temp;
154 
155 	ret = __adrf6780_spi_read(st, reg, &data);
156 	if (ret)
157 		return ret;
158 
159 	temp = (data & ~mask) | (val & mask);
160 
161 	return __adrf6780_spi_write(st, reg, temp);
162 }
163 
adrf6780_spi_update_bits(struct adrf6780_state * st,unsigned int reg,unsigned int mask,unsigned int val)164 static int adrf6780_spi_update_bits(struct adrf6780_state *st, unsigned int reg,
165 				    unsigned int mask, unsigned int val)
166 {
167 	int ret;
168 
169 	mutex_lock(&st->lock);
170 	ret = __adrf6780_spi_update_bits(st, reg, mask, val);
171 	mutex_unlock(&st->lock);
172 
173 	return ret;
174 }
175 
adrf6780_read_adc_raw(struct adrf6780_state * st,unsigned int * read_val)176 static int adrf6780_read_adc_raw(struct adrf6780_state *st, unsigned int *read_val)
177 {
178 	int ret;
179 
180 	mutex_lock(&st->lock);
181 
182 	ret = __adrf6780_spi_update_bits(st, ADRF6780_REG_ADC_CONTROL,
183 					 ADRF6780_ADC_EN_MSK |
184 					 ADRF6780_ADC_CLOCK_EN_MSK |
185 					 ADRF6780_ADC_START_MSK,
186 					 FIELD_PREP(ADRF6780_ADC_EN_MSK, 1) |
187 					 FIELD_PREP(ADRF6780_ADC_CLOCK_EN_MSK, 1) |
188 					 FIELD_PREP(ADRF6780_ADC_START_MSK, 1));
189 	if (ret)
190 		goto exit;
191 
192 	/* Recommended delay for the ADC to be ready*/
193 	usleep_range(200, 250);
194 
195 	ret = __adrf6780_spi_read(st, ADRF6780_REG_ADC_OUTPUT, read_val);
196 	if (ret)
197 		goto exit;
198 
199 	if (!(*read_val & ADRF6780_ADC_STATUS_MSK)) {
200 		ret = -EINVAL;
201 		goto exit;
202 	}
203 
204 	ret = __adrf6780_spi_update_bits(st, ADRF6780_REG_ADC_CONTROL,
205 					 ADRF6780_ADC_START_MSK,
206 					 FIELD_PREP(ADRF6780_ADC_START_MSK, 0));
207 	if (ret)
208 		goto exit;
209 
210 	ret = __adrf6780_spi_read(st, ADRF6780_REG_ADC_OUTPUT, read_val);
211 
212 exit:
213 	mutex_unlock(&st->lock);
214 	return ret;
215 }
216 
adrf6780_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)217 static int adrf6780_read_raw(struct iio_dev *indio_dev,
218 			     struct iio_chan_spec const *chan,
219 			     int *val, int *val2, long info)
220 {
221 	struct adrf6780_state *dev = iio_priv(indio_dev);
222 	unsigned int data;
223 	int ret;
224 
225 	switch (info) {
226 	case IIO_CHAN_INFO_RAW:
227 		ret = adrf6780_read_adc_raw(dev, &data);
228 		if (ret)
229 			return ret;
230 
231 		*val = data & ADRF6780_ADC_VALUE_MSK;
232 
233 		return IIO_VAL_INT;
234 
235 	case IIO_CHAN_INFO_SCALE:
236 		ret = adrf6780_spi_read(dev, ADRF6780_REG_LINEARIZE, &data);
237 		if (ret)
238 			return ret;
239 
240 		*val = data & ADRF6780_RDAC_LINEARIZE_MSK;
241 
242 		return IIO_VAL_INT;
243 	case IIO_CHAN_INFO_PHASE:
244 		ret = adrf6780_spi_read(dev, ADRF6780_REG_LO_PATH, &data);
245 		if (ret)
246 			return ret;
247 
248 		switch (chan->channel2) {
249 		case IIO_MOD_I:
250 			*val = data & ADRF6780_I_PATH_PHASE_ACCURACY_MSK;
251 
252 			return IIO_VAL_INT;
253 		case IIO_MOD_Q:
254 			*val = FIELD_GET(ADRF6780_Q_PATH_PHASE_ACCURACY_MSK,
255 					 data);
256 
257 			return IIO_VAL_INT;
258 		default:
259 			return -EINVAL;
260 		}
261 	default:
262 		return -EINVAL;
263 	}
264 }
265 
adrf6780_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)266 static int adrf6780_write_raw(struct iio_dev *indio_dev,
267 			      struct iio_chan_spec const *chan,
268 			      int val, int val2, long info)
269 {
270 	struct adrf6780_state *st = iio_priv(indio_dev);
271 
272 	switch (info) {
273 	case IIO_CHAN_INFO_SCALE:
274 		return adrf6780_spi_write(st, ADRF6780_REG_LINEARIZE, val);
275 	case IIO_CHAN_INFO_PHASE:
276 		switch (chan->channel2) {
277 		case IIO_MOD_I:
278 			return adrf6780_spi_update_bits(st,
279 				ADRF6780_REG_LO_PATH,
280 				ADRF6780_I_PATH_PHASE_ACCURACY_MSK,
281 				FIELD_PREP(ADRF6780_I_PATH_PHASE_ACCURACY_MSK, val));
282 		case IIO_MOD_Q:
283 			return adrf6780_spi_update_bits(st,
284 				ADRF6780_REG_LO_PATH,
285 				ADRF6780_Q_PATH_PHASE_ACCURACY_MSK,
286 				FIELD_PREP(ADRF6780_Q_PATH_PHASE_ACCURACY_MSK, val));
287 		default:
288 			return -EINVAL;
289 		}
290 	default:
291 		return -EINVAL;
292 	}
293 }
294 
adrf6780_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int write_val,unsigned int * read_val)295 static int adrf6780_reg_access(struct iio_dev *indio_dev,
296 			       unsigned int reg,
297 			       unsigned int write_val,
298 			       unsigned int *read_val)
299 {
300 	struct adrf6780_state *st = iio_priv(indio_dev);
301 
302 	if (read_val)
303 		return adrf6780_spi_read(st, reg, read_val);
304 	else
305 		return adrf6780_spi_write(st, reg, write_val);
306 }
307 
308 static const struct iio_info adrf6780_info = {
309 	.read_raw = adrf6780_read_raw,
310 	.write_raw = adrf6780_write_raw,
311 	.debugfs_reg_access = &adrf6780_reg_access,
312 };
313 
314 #define ADRF6780_CHAN_ADC(_channel) {			\
315 	.type = IIO_ALTVOLTAGE,				\
316 	.output = 0,					\
317 	.indexed = 1,					\
318 	.channel = _channel,				\
319 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW)	\
320 }
321 
322 #define ADRF6780_CHAN_RDAC(_channel) {			\
323 	.type = IIO_ALTVOLTAGE,				\
324 	.output = 1,					\
325 	.indexed = 1,					\
326 	.channel = _channel,				\
327 	.info_mask_separate = BIT(IIO_CHAN_INFO_SCALE)	\
328 }
329 
330 #define ADRF6780_CHAN_IQ_PHASE(_channel, rf_comp) {		\
331 	.type = IIO_ALTVOLTAGE,					\
332 	.modified = 1,						\
333 	.output = 1,						\
334 	.indexed = 1,						\
335 	.channel2 = IIO_MOD_##rf_comp,				\
336 	.channel = _channel,					\
337 	.info_mask_separate = BIT(IIO_CHAN_INFO_PHASE)		\
338 }
339 
340 static const struct iio_chan_spec adrf6780_channels[] = {
341 	ADRF6780_CHAN_ADC(0),
342 	ADRF6780_CHAN_RDAC(0),
343 	ADRF6780_CHAN_IQ_PHASE(0, I),
344 	ADRF6780_CHAN_IQ_PHASE(0, Q),
345 };
346 
adrf6780_reset(struct adrf6780_state * st)347 static int adrf6780_reset(struct adrf6780_state *st)
348 {
349 	int ret;
350 	struct spi_device *spi = st->spi;
351 
352 	ret = __adrf6780_spi_update_bits(st, ADRF6780_REG_CONTROL,
353 					 ADRF6780_SOFT_RESET_MSK,
354 					 FIELD_PREP(ADRF6780_SOFT_RESET_MSK, 1));
355 	if (ret) {
356 		dev_err(&spi->dev, "ADRF6780 SPI software reset failed.\n");
357 		return ret;
358 	}
359 
360 	ret = __adrf6780_spi_update_bits(st, ADRF6780_REG_CONTROL,
361 					 ADRF6780_SOFT_RESET_MSK,
362 					 FIELD_PREP(ADRF6780_SOFT_RESET_MSK, 0));
363 	if (ret) {
364 		dev_err(&spi->dev, "ADRF6780 SPI software reset disable failed.\n");
365 		return ret;
366 	}
367 
368 	return 0;
369 }
370 
adrf6780_init(struct adrf6780_state * st)371 static int adrf6780_init(struct adrf6780_state *st)
372 {
373 	int ret;
374 	unsigned int chip_id, enable_reg, enable_reg_msk;
375 	struct spi_device *spi = st->spi;
376 
377 	/* Perform a software reset */
378 	ret = adrf6780_reset(st);
379 	if (ret)
380 		return ret;
381 
382 	ret = __adrf6780_spi_read(st, ADRF6780_REG_CONTROL, &chip_id);
383 	if (ret)
384 		return ret;
385 
386 	chip_id = FIELD_GET(ADRF6780_CHIP_ID_MSK, chip_id);
387 	if (chip_id != ADRF6780_CHIP_ID) {
388 		dev_err(&spi->dev, "ADRF6780 Invalid Chip ID.\n");
389 		return -EINVAL;
390 	}
391 
392 	enable_reg_msk = ADRF6780_VGA_BUFFER_EN_MSK |
393 			ADRF6780_DETECTOR_EN_MSK |
394 			ADRF6780_LO_BUFFER_EN_MSK |
395 			ADRF6780_IF_MODE_EN_MSK |
396 			ADRF6780_IQ_MODE_EN_MSK |
397 			ADRF6780_LO_X2_EN_MSK |
398 			ADRF6780_LO_PPF_EN_MSK |
399 			ADRF6780_LO_EN_MSK |
400 			ADRF6780_UC_BIAS_EN_MSK;
401 
402 	enable_reg = FIELD_PREP(ADRF6780_VGA_BUFFER_EN_MSK, st->vga_buff_en) |
403 			FIELD_PREP(ADRF6780_DETECTOR_EN_MSK, 1) |
404 			FIELD_PREP(ADRF6780_LO_BUFFER_EN_MSK, st->lo_buff_en) |
405 			FIELD_PREP(ADRF6780_IF_MODE_EN_MSK, st->if_mode_en) |
406 			FIELD_PREP(ADRF6780_IQ_MODE_EN_MSK, st->iq_mode_en) |
407 			FIELD_PREP(ADRF6780_LO_X2_EN_MSK, st->lo_x2_en) |
408 			FIELD_PREP(ADRF6780_LO_PPF_EN_MSK, st->lo_ppf_en) |
409 			FIELD_PREP(ADRF6780_LO_EN_MSK, st->lo_en) |
410 			FIELD_PREP(ADRF6780_UC_BIAS_EN_MSK, st->uc_bias_en);
411 
412 	ret = __adrf6780_spi_update_bits(st, ADRF6780_REG_ENABLE,
413 					 enable_reg_msk, enable_reg);
414 	if (ret)
415 		return ret;
416 
417 	ret = __adrf6780_spi_update_bits(st, ADRF6780_REG_LO_PATH,
418 					 ADRF6780_LO_SIDEBAND_MSK,
419 					 FIELD_PREP(ADRF6780_LO_SIDEBAND_MSK, st->lo_sideband));
420 	if (ret)
421 		return ret;
422 
423 	return __adrf6780_spi_update_bits(st, ADRF6780_REG_ADC_CONTROL,
424 		ADRF6780_VDET_OUTPUT_SELECT_MSK,
425 		FIELD_PREP(ADRF6780_VDET_OUTPUT_SELECT_MSK, st->vdet_out_en));
426 }
427 
adrf6780_properties_parse(struct adrf6780_state * st)428 static void adrf6780_properties_parse(struct adrf6780_state *st)
429 {
430 	struct spi_device *spi = st->spi;
431 
432 	st->vga_buff_en = device_property_read_bool(&spi->dev, "adi,vga-buff-en");
433 	st->lo_buff_en = device_property_read_bool(&spi->dev, "adi,lo-buff-en");
434 	st->if_mode_en = device_property_read_bool(&spi->dev, "adi,if-mode-en");
435 	st->iq_mode_en = device_property_read_bool(&spi->dev, "adi,iq-mode-en");
436 	st->lo_x2_en = device_property_read_bool(&spi->dev, "adi,lo-x2-en");
437 	st->lo_ppf_en = device_property_read_bool(&spi->dev, "adi,lo-ppf-en");
438 	st->lo_en = device_property_read_bool(&spi->dev, "adi,lo-en");
439 	st->uc_bias_en = device_property_read_bool(&spi->dev, "adi,uc-bias-en");
440 	st->lo_sideband = device_property_read_bool(&spi->dev, "adi,lo-sideband");
441 	st->vdet_out_en = device_property_read_bool(&spi->dev, "adi,vdet-out-en");
442 }
443 
adrf6780_powerdown(void * data)444 static void adrf6780_powerdown(void *data)
445 {
446 	/* Disable all components in the Enable Register */
447 	adrf6780_spi_write(data, ADRF6780_REG_ENABLE, 0x0);
448 }
449 
adrf6780_probe(struct spi_device * spi)450 static int adrf6780_probe(struct spi_device *spi)
451 {
452 	struct iio_dev *indio_dev;
453 	struct adrf6780_state *st;
454 	int ret;
455 
456 	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
457 	if (!indio_dev)
458 		return -ENOMEM;
459 
460 	st = iio_priv(indio_dev);
461 
462 	indio_dev->info = &adrf6780_info;
463 	indio_dev->name = "adrf6780";
464 	indio_dev->channels = adrf6780_channels;
465 	indio_dev->num_channels = ARRAY_SIZE(adrf6780_channels);
466 
467 	st->spi = spi;
468 
469 	adrf6780_properties_parse(st);
470 
471 	st->clkin = devm_clk_get_enabled(&spi->dev, "lo_in");
472 	if (IS_ERR(st->clkin))
473 		return dev_err_probe(&spi->dev, PTR_ERR(st->clkin),
474 				     "failed to get the LO input clock\n");
475 
476 	mutex_init(&st->lock);
477 
478 	ret = adrf6780_init(st);
479 	if (ret)
480 		return ret;
481 
482 	ret = devm_add_action_or_reset(&spi->dev, adrf6780_powerdown, st);
483 	if (ret)
484 		return ret;
485 
486 	return devm_iio_device_register(&spi->dev, indio_dev);
487 }
488 
489 static const struct spi_device_id adrf6780_id[] = {
490 	{ "adrf6780", 0 },
491 	{}
492 };
493 MODULE_DEVICE_TABLE(spi, adrf6780_id);
494 
495 static const struct of_device_id adrf6780_of_match[] = {
496 	{ .compatible = "adi,adrf6780" },
497 	{}
498 };
499 MODULE_DEVICE_TABLE(of, adrf6780_of_match);
500 
501 static struct spi_driver adrf6780_driver = {
502 	.driver = {
503 		.name = "adrf6780",
504 		.of_match_table = adrf6780_of_match,
505 	},
506 	.probe = adrf6780_probe,
507 	.id_table = adrf6780_id,
508 };
509 module_spi_driver(adrf6780_driver);
510 
511 MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com");
512 MODULE_DESCRIPTION("Analog Devices ADRF6780");
513 MODULE_LICENSE("GPL v2");
514