1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
2 /* Copyright(c) 2014 - 2020 Intel Corporation */
3 #ifndef ADF_ACCEL_DEVICES_H_
4 #define ADF_ACCEL_DEVICES_H_
5 #include <linux/interrupt.h>
6 #include <linux/module.h>
7 #include <linux/list.h>
8 #include <linux/io.h>
9 #include <linux/ratelimit.h>
10 #include "adf_cfg_common.h"
11 #include "adf_pfvf_msg.h"
12
13 #define ADF_DH895XCC_DEVICE_NAME "dh895xcc"
14 #define ADF_DH895XCCVF_DEVICE_NAME "dh895xccvf"
15 #define ADF_C62X_DEVICE_NAME "c6xx"
16 #define ADF_C62XVF_DEVICE_NAME "c6xxvf"
17 #define ADF_C3XXX_DEVICE_NAME "c3xxx"
18 #define ADF_C3XXXVF_DEVICE_NAME "c3xxxvf"
19 #define ADF_4XXX_DEVICE_NAME "4xxx"
20 #define ADF_4XXX_PCI_DEVICE_ID 0x4940
21 #define ADF_4XXXIOV_PCI_DEVICE_ID 0x4941
22 #define ADF_401XX_PCI_DEVICE_ID 0x4942
23 #define ADF_401XXIOV_PCI_DEVICE_ID 0x4943
24 #define ADF_DEVICE_FUSECTL_OFFSET 0x40
25 #define ADF_DEVICE_LEGFUSE_OFFSET 0x4C
26 #define ADF_DEVICE_FUSECTL_MASK 0x80000000
27 #define ADF_PCI_MAX_BARS 3
28 #define ADF_DEVICE_NAME_LENGTH 32
29 #define ADF_ETR_MAX_RINGS_PER_BANK 16
30 #define ADF_MAX_MSIX_VECTOR_NAME 16
31 #define ADF_DEVICE_NAME_PREFIX "qat_"
32
33 enum adf_accel_capabilities {
34 ADF_ACCEL_CAPABILITIES_NULL = 0,
35 ADF_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC = 1,
36 ADF_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC = 2,
37 ADF_ACCEL_CAPABILITIES_CIPHER = 4,
38 ADF_ACCEL_CAPABILITIES_AUTHENTICATION = 8,
39 ADF_ACCEL_CAPABILITIES_COMPRESSION = 32,
40 ADF_ACCEL_CAPABILITIES_LZS_COMPRESSION = 64,
41 ADF_ACCEL_CAPABILITIES_RANDOM_NUMBER = 128
42 };
43
44 struct adf_bar {
45 resource_size_t base_addr;
46 void __iomem *virt_addr;
47 resource_size_t size;
48 };
49
50 struct adf_irq {
51 bool enabled;
52 char name[ADF_MAX_MSIX_VECTOR_NAME];
53 };
54
55 struct adf_accel_msix {
56 struct adf_irq *irqs;
57 u32 num_entries;
58 };
59
60 struct adf_accel_pci {
61 struct pci_dev *pci_dev;
62 struct adf_accel_msix msix_entries;
63 struct adf_bar pci_bars[ADF_PCI_MAX_BARS];
64 u8 revid;
65 u8 sku;
66 };
67
68 enum dev_state {
69 DEV_DOWN = 0,
70 DEV_UP
71 };
72
73 enum dev_sku_info {
74 DEV_SKU_1 = 0,
75 DEV_SKU_2,
76 DEV_SKU_3,
77 DEV_SKU_4,
78 DEV_SKU_VF,
79 DEV_SKU_UNKNOWN,
80 };
81
get_sku_info(enum dev_sku_info info)82 static inline const char *get_sku_info(enum dev_sku_info info)
83 {
84 switch (info) {
85 case DEV_SKU_1:
86 return "SKU1";
87 case DEV_SKU_2:
88 return "SKU2";
89 case DEV_SKU_3:
90 return "SKU3";
91 case DEV_SKU_4:
92 return "SKU4";
93 case DEV_SKU_VF:
94 return "SKUVF";
95 case DEV_SKU_UNKNOWN:
96 default:
97 break;
98 }
99 return "Unknown SKU";
100 }
101
102 struct adf_hw_device_class {
103 const char *name;
104 const enum adf_device_type type;
105 u32 instances;
106 };
107
108 struct arb_info {
109 u32 arb_cfg;
110 u32 arb_offset;
111 u32 wt2sam_offset;
112 };
113
114 struct admin_info {
115 u32 admin_msg_ur;
116 u32 admin_msg_lr;
117 u32 mailbox_offset;
118 };
119
120 struct adf_hw_csr_ops {
121 u64 (*build_csr_ring_base_addr)(dma_addr_t addr, u32 size);
122 u32 (*read_csr_ring_head)(void __iomem *csr_base_addr, u32 bank,
123 u32 ring);
124 void (*write_csr_ring_head)(void __iomem *csr_base_addr, u32 bank,
125 u32 ring, u32 value);
126 u32 (*read_csr_ring_tail)(void __iomem *csr_base_addr, u32 bank,
127 u32 ring);
128 void (*write_csr_ring_tail)(void __iomem *csr_base_addr, u32 bank,
129 u32 ring, u32 value);
130 u32 (*read_csr_e_stat)(void __iomem *csr_base_addr, u32 bank);
131 void (*write_csr_ring_config)(void __iomem *csr_base_addr, u32 bank,
132 u32 ring, u32 value);
133 void (*write_csr_ring_base)(void __iomem *csr_base_addr, u32 bank,
134 u32 ring, dma_addr_t addr);
135 void (*write_csr_int_flag)(void __iomem *csr_base_addr, u32 bank,
136 u32 value);
137 void (*write_csr_int_srcsel)(void __iomem *csr_base_addr, u32 bank);
138 void (*write_csr_int_col_en)(void __iomem *csr_base_addr, u32 bank,
139 u32 value);
140 void (*write_csr_int_col_ctl)(void __iomem *csr_base_addr, u32 bank,
141 u32 value);
142 void (*write_csr_int_flag_and_col)(void __iomem *csr_base_addr,
143 u32 bank, u32 value);
144 void (*write_csr_ring_srv_arb_en)(void __iomem *csr_base_addr, u32 bank,
145 u32 value);
146 };
147
148 struct adf_cfg_device_data;
149 struct adf_accel_dev;
150 struct adf_etr_data;
151 struct adf_etr_ring_data;
152
153 struct adf_pfvf_ops {
154 int (*enable_comms)(struct adf_accel_dev *accel_dev);
155 u32 (*get_pf2vf_offset)(u32 i);
156 u32 (*get_vf2pf_offset)(u32 i);
157 void (*enable_vf2pf_interrupts)(void __iomem *pmisc_addr, u32 vf_mask);
158 void (*disable_all_vf2pf_interrupts)(void __iomem *pmisc_addr);
159 u32 (*disable_pending_vf2pf_interrupts)(void __iomem *pmisc_addr);
160 int (*send_msg)(struct adf_accel_dev *accel_dev, struct pfvf_message msg,
161 u32 pfvf_offset, struct mutex *csr_lock);
162 struct pfvf_message (*recv_msg)(struct adf_accel_dev *accel_dev,
163 u32 pfvf_offset, u8 compat_ver);
164 };
165
166 struct adf_hw_device_data {
167 struct adf_hw_device_class *dev_class;
168 u32 (*get_accel_mask)(struct adf_hw_device_data *self);
169 u32 (*get_ae_mask)(struct adf_hw_device_data *self);
170 u32 (*get_accel_cap)(struct adf_accel_dev *accel_dev);
171 u32 (*get_sram_bar_id)(struct adf_hw_device_data *self);
172 u32 (*get_misc_bar_id)(struct adf_hw_device_data *self);
173 u32 (*get_etr_bar_id)(struct adf_hw_device_data *self);
174 u32 (*get_num_aes)(struct adf_hw_device_data *self);
175 u32 (*get_num_accels)(struct adf_hw_device_data *self);
176 void (*get_arb_info)(struct arb_info *arb_csrs_info);
177 void (*get_admin_info)(struct admin_info *admin_csrs_info);
178 enum dev_sku_info (*get_sku)(struct adf_hw_device_data *self);
179 int (*alloc_irq)(struct adf_accel_dev *accel_dev);
180 void (*free_irq)(struct adf_accel_dev *accel_dev);
181 void (*enable_error_correction)(struct adf_accel_dev *accel_dev);
182 int (*init_admin_comms)(struct adf_accel_dev *accel_dev);
183 void (*exit_admin_comms)(struct adf_accel_dev *accel_dev);
184 int (*send_admin_init)(struct adf_accel_dev *accel_dev);
185 int (*init_arb)(struct adf_accel_dev *accel_dev);
186 void (*exit_arb)(struct adf_accel_dev *accel_dev);
187 const u32 *(*get_arb_mapping)(void);
188 int (*init_device)(struct adf_accel_dev *accel_dev);
189 int (*enable_pm)(struct adf_accel_dev *accel_dev);
190 bool (*handle_pm_interrupt)(struct adf_accel_dev *accel_dev);
191 void (*disable_iov)(struct adf_accel_dev *accel_dev);
192 void (*configure_iov_threads)(struct adf_accel_dev *accel_dev,
193 bool enable);
194 void (*enable_ints)(struct adf_accel_dev *accel_dev);
195 void (*set_ssm_wdtimer)(struct adf_accel_dev *accel_dev);
196 int (*ring_pair_reset)(struct adf_accel_dev *accel_dev, u32 bank_nr);
197 void (*reset_device)(struct adf_accel_dev *accel_dev);
198 void (*set_msix_rttable)(struct adf_accel_dev *accel_dev);
199 char *(*uof_get_name)(struct adf_accel_dev *accel_dev, u32 obj_num);
200 u32 (*uof_get_num_objs)(void);
201 u32 (*uof_get_ae_mask)(struct adf_accel_dev *accel_dev, u32 obj_num);
202 int (*dev_config)(struct adf_accel_dev *accel_dev);
203 struct adf_pfvf_ops pfvf_ops;
204 struct adf_hw_csr_ops csr_ops;
205 const char *fw_name;
206 const char *fw_mmp_name;
207 u32 fuses;
208 u32 straps;
209 u32 accel_capabilities_mask;
210 u32 extended_dc_capabilities;
211 u32 clock_frequency;
212 u32 instance_id;
213 u16 accel_mask;
214 u32 ae_mask;
215 u32 admin_ae_mask;
216 u16 tx_rings_mask;
217 u16 ring_to_svc_map;
218 u8 tx_rx_gap;
219 u8 num_banks;
220 u16 num_banks_per_vf;
221 u8 num_rings_per_bank;
222 u8 num_accel;
223 u8 num_logical_accel;
224 u8 num_engines;
225 };
226
227 /* CSR write macro */
228 #define ADF_CSR_WR(csr_base, csr_offset, val) \
229 __raw_writel(val, csr_base + csr_offset)
230
231 /* CSR read macro */
232 #define ADF_CSR_RD(csr_base, csr_offset) __raw_readl(csr_base + csr_offset)
233
234 #define ADF_CFG_NUM_SERVICES 4
235 #define ADF_SRV_TYPE_BIT_LEN 3
236 #define ADF_SRV_TYPE_MASK 0x7
237
238 #define GET_DEV(accel_dev) ((accel_dev)->accel_pci_dev.pci_dev->dev)
239 #define GET_BARS(accel_dev) ((accel_dev)->accel_pci_dev.pci_bars)
240 #define GET_HW_DATA(accel_dev) (accel_dev->hw_device)
241 #define GET_MAX_BANKS(accel_dev) (GET_HW_DATA(accel_dev)->num_banks)
242 #define GET_NUM_RINGS_PER_BANK(accel_dev) \
243 GET_HW_DATA(accel_dev)->num_rings_per_bank
244 #define GET_SRV_TYPE(accel_dev, idx) \
245 (((GET_HW_DATA(accel_dev)->ring_to_svc_map) >> (ADF_SRV_TYPE_BIT_LEN * (idx))) \
246 & ADF_SRV_TYPE_MASK)
247 #define GET_MAX_ACCELENGINES(accel_dev) (GET_HW_DATA(accel_dev)->num_engines)
248 #define GET_CSR_OPS(accel_dev) (&(accel_dev)->hw_device->csr_ops)
249 #define GET_PFVF_OPS(accel_dev) (&(accel_dev)->hw_device->pfvf_ops)
250 #define accel_to_pci_dev(accel_ptr) accel_ptr->accel_pci_dev.pci_dev
251
252 struct adf_admin_comms;
253 struct icp_qat_fw_loader_handle;
254 struct adf_fw_loader_data {
255 struct icp_qat_fw_loader_handle *fw_loader;
256 const struct firmware *uof_fw;
257 const struct firmware *mmp_fw;
258 };
259
260 struct adf_accel_vf_info {
261 struct adf_accel_dev *accel_dev;
262 struct mutex pf2vf_lock; /* protect CSR access for PF2VF messages */
263 struct ratelimit_state vf2pf_ratelimit;
264 u32 vf_nr;
265 bool init;
266 u8 vf_compat_ver;
267 };
268
269 struct adf_accel_dev {
270 struct adf_etr_data *transport;
271 struct adf_hw_device_data *hw_device;
272 struct adf_cfg_device_data *cfg;
273 struct adf_fw_loader_data *fw_loader;
274 struct adf_admin_comms *admin;
275 struct list_head crypto_list;
276 unsigned long status;
277 atomic_t ref_count;
278 struct dentry *debugfs_dir;
279 struct list_head list;
280 struct module *owner;
281 struct adf_accel_pci accel_pci_dev;
282 union {
283 struct {
284 /* protects VF2PF interrupts access */
285 spinlock_t vf2pf_ints_lock;
286 /* vf_info is non-zero when SR-IOV is init'ed */
287 struct adf_accel_vf_info *vf_info;
288 } pf;
289 struct {
290 bool irq_enabled;
291 char irq_name[ADF_MAX_MSIX_VECTOR_NAME];
292 struct tasklet_struct pf2vf_bh_tasklet;
293 struct mutex vf2pf_lock; /* protect CSR access */
294 struct completion msg_received;
295 struct pfvf_message response; /* temp field holding pf2vf response */
296 u8 pf_compat_ver;
297 } vf;
298 };
299 bool is_vf;
300 u32 accel_id;
301 };
302 #endif
303