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Searched refs:vclk (Results 1 – 25 of 89) sorted by relevance

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/linux-5.19.10/drivers/video/fbdev/via/
Dvt1636.c186 index = get_clk_range_index(plvds_setting_info->vclk); in viafb_vt1636_patch_skew_on_vt3324()
210 index = get_clk_range_index(plvds_setting_info->vclk); in viafb_vt1636_patch_skew_on_vt3327()
227 index = get_clk_range_index(plvds_setting_info->vclk); in viafb_vt1636_patch_skew_on_vt3364()
Dchip.h141 u32 vclk; /*panel mode clock value */ member
/linux-5.19.10/drivers/gpu/drm/radeon/
Drs780_dpm.c570 if ((new_ps->vclk == old_ps->vclk) && in rs780_set_uvd_clock_before_set_eng_clock()
577 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_before_set_eng_clock()
587 if ((new_ps->vclk == old_ps->vclk) && in rs780_set_uvd_clock_after_set_eng_clock()
594 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_after_set_eng_clock()
727 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in rs780_parse_pplib_non_clock_info()
730 rps->vclk = 0; in rs780_parse_pplib_non_clock_info()
735 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rs780_parse_pplib_non_clock_info()
736 rps->vclk = RS780_DEFAULT_VCLK_FREQ; in rs780_parse_pplib_non_clock_info()
945 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_print_power_state()
994 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_debugfs_print_current_performance_level()
Dtrinity_dpm.c854 if ((rps->vclk == 0) && (rps->dclk == 0)) in trinity_uvd_clocks_zero()
866 if ((rps1->vclk == rps2->vclk) && in trinity_uvd_clocks_equal()
899 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks()
910 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks()
1414 if ((rps->vclk == pi->sys_info.uvd_clock_table_entries[i].vclk) && in trinity_get_uvd_clock_index()
1648 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in trinity_parse_pplib_non_clock_info()
1651 rps->vclk = 0; in trinity_parse_pplib_non_clock_info()
1889 pi->sys_info.uvd_clock_table_entries[i].vclk = in trinity_parse_sys_info_table()
1975 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_print_power_state()
2000 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_debugfs_print_current_performance_level()
Dsumo_dpm.c824 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in sumo_setup_uvd_clocks()
840 if ((new_rps->vclk == old_rps->vclk) && in sumo_set_uvd_clock_before_set_eng_clock()
858 if ((new_rps->vclk == old_rps->vclk) && in sumo_set_uvd_clock_after_set_eng_clock()
1414 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in sumo_parse_pplib_non_clock_info()
1417 rps->vclk = 0; in sumo_parse_pplib_non_clock_info()
1802 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_print_power_state()
1825 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level()
1833 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level()
Dtrinity_dpm.h69 u32 vclk; member
Drv770_dpm.c1440 if ((new_ps->vclk == old_ps->vclk) && in rv770_set_uvd_clock_before_set_eng_clock()
1447 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv770_set_uvd_clock_before_set_eng_clock()
1457 if ((new_ps->vclk == old_ps->vclk) && in rv770_set_uvd_clock_after_set_eng_clock()
1464 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv770_set_uvd_clock_after_set_eng_clock()
2155 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in rv7xx_parse_pplib_non_clock_info()
2158 rps->vclk = 0; in rv7xx_parse_pplib_non_clock_info()
2163 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rv7xx_parse_pplib_non_clock_info()
2164 rps->vclk = RV770_DEFAULT_VCLK_FREQ; in rv7xx_parse_pplib_non_clock_info()
2442 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv770_dpm_print_power_state()
2486 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv770_dpm_debugfs_print_current_performance_level()
Drv6xx_dpm.c1518 if ((new_ps->vclk == old_ps->vclk) && in rv6xx_set_uvd_clock_before_set_eng_clock()
1525 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv6xx_set_uvd_clock_before_set_eng_clock()
1535 if ((new_ps->vclk == old_ps->vclk) && in rv6xx_set_uvd_clock_after_set_eng_clock()
1542 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv6xx_set_uvd_clock_after_set_eng_clock()
1803 rps->vclk = RV6XX_DEFAULT_VCLK_FREQ; in rv6xx_parse_pplib_non_clock_info()
1806 rps->vclk = 0; in rv6xx_parse_pplib_non_clock_info()
2015 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv6xx_dpm_print_power_state()
2047 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv6xx_dpm_debugfs_print_current_performance_level()
Dradeon_uvd.c950 unsigned vclk, unsigned dclk, in radeon_uvd_calc_upll_dividers() argument
965 vco_min = max(max(vco_min, vclk), dclk); in radeon_uvd_calc_upll_dividers()
980 vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk, in radeon_uvd_calc_upll_dividers()
992 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); in radeon_uvd_calc_upll_dividers()
Dradeon_asic.h409 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
476 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
533 int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
534 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
748 int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
786 int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
/linux-5.19.10/Documentation/devicetree/bindings/media/
Daspeed-video.txt13 - clock-names: "vclk" and "eclk"
29 clock-names = "vclk", "eclk";
/linux-5.19.10/drivers/gpu/drm/exynos/
Dexynos7_drm_decon.c50 struct clk *vclk; member
147 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->vclk), ideal_clk); in decon_calc_clkdiv()
723 ctx->vclk = devm_clk_get(dev, "decon0_vclk"); in decon_probe()
724 if (IS_ERR(ctx->vclk)) { in decon_probe()
726 ret = PTR_ERR(ctx->vclk); in decon_probe()
786 clk_disable_unprepare(ctx->vclk); in exynos7_decon_suspend()
820 ret = clk_prepare_enable(ctx->vclk); in exynos7_decon_resume()
/linux-5.19.10/drivers/video/fbdev/aty/
Daty128fb.c425 u32 vclk; member
1366 u32 vclk; /* in .01 MHz */ in aty128_var_to_pll() local
1370 vclk = 100000000 / period_in_ps; /* convert units to 10 kHz */ in aty128_var_to_pll()
1373 if (vclk > c.ppll_max) in aty128_var_to_pll()
1374 vclk = c.ppll_max; in aty128_var_to_pll()
1375 if (vclk * 12 < c.ppll_min) in aty128_var_to_pll()
1376 vclk = c.ppll_min/12; in aty128_var_to_pll()
1380 output_freq = post_dividers[i] * vclk; in aty128_var_to_pll()
1395 pll->vclk = vclk; in aty128_var_to_pll()
1399 pll->feedback_divider, vclk, output_freq, in aty128_var_to_pll()
[all …]
/linux-5.19.10/drivers/gpu/drm/nouveau/dispnv04/
Darb.c252 nouveau_calc_arb(struct drm_device *dev, int vclk, int bpp, int *burst, int *lwm) in nouveau_calc_arb() argument
258 nv04_update_arb(dev, vclk, bpp, burst, lwm); in nouveau_calc_arb()
/linux-5.19.10/drivers/media/platform/aspeed/
Daspeed-video.c267 struct clk *vclk; member
615 clk_disable(video->vclk); in aspeed_video_off()
626 clk_enable(video->vclk); in aspeed_video_on()
1912 video->vclk = devm_clk_get(dev, "vclk"); in aspeed_video_init()
1913 if (IS_ERR(video->vclk)) { in aspeed_video_init()
1915 rc = PTR_ERR(video->vclk); in aspeed_video_init()
1919 rc = clk_prepare(video->vclk); in aspeed_video_init()
1946 clk_unprepare(video->vclk); in aspeed_video_init()
1997 clk_unprepare(video->vclk); in aspeed_video_probe()
2019 clk_unprepare(video->vclk); in aspeed_video_remove()
/linux-5.19.10/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dsmu8_hwmgr.c140 if (clock <= ptable->entries[i].vclk) in smu8_get_uvd_level()
148 if (clock >= ptable->entries[i].vclk) in smu8_get_uvd_level()
513 (i < uvd_table->count) ? uvd_table->entries[i].vclk : 0; in smu8_upload_pptable_to_smu()
597 clock = table->entries[level].vclk; in smu8_init_uvd_limit()
599 clock = table->entries[table->count - 1].vclk; in smu8_init_uvd_limit()
1415 smu8_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK; in smu8_dpm_get_pp_table_entry()
1723 uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent; in smu8_read_sensor() local
1757 vclk = uvd_table->entries[uvd_index].vclk; in smu8_read_sensor()
1758 *((uint32_t *)value) = vclk; in smu8_read_sensor()
1893 ptable->entries[ptable->count - 1].vclk; in smu8_dpm_update_uvd_dpm()
Dhwmgr_ppt.h60 uint32_t vclk; /* UVD V-clock */ member
Dsmu10_hwmgr.h97 uint32_t vclk; member
/linux-5.19.10/Documentation/devicetree/bindings/display/samsung/
Dsamsung,fimd.yaml120 samsung,invert-vclk:
186 samsung,invert-vclk;
/linux-5.19.10/Documentation/devicetree/bindings/display/
Dxylon,logicvc-display.yaml45 # vclk is required and must be provided as first item.
46 - const: vclk
228 clock-names = "vclk", "lvdsclk";
/linux-5.19.10/drivers/gpu/drm/amd/pm/powerplay/inc/
Dpower_state.h183 unsigned long vclk; member
/linux-5.19.10/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
Ddcn301_smu.h38 uint32_t vclk; member
/linux-5.19.10/drivers/gpu/drm/amd/amdgpu/
Dsi.c1714 unsigned vclk, unsigned dclk, in si_calc_upll_dividers() argument
1729 vco_min = max(max(vco_min, vclk), dclk); in si_calc_upll_dividers()
1743 vclk_div = si_uvd_calc_upll_post_div(vco_freq, vclk, in si_calc_upll_dividers()
1755 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); in si_calc_upll_dividers()
1775 static int si_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) in si_set_uvd_clocks() argument
1788 if (!vclk || !dclk) { in si_set_uvd_clocks()
1793 r = si_calc_upll_dividers(adev, vclk, dclk, 125000, 250000, in si_set_uvd_clocks()
/linux-5.19.10/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
Dsmu11_driver_if_vangogh.h120 uint32_t vclk; member
/linux-5.19.10/drivers/gpu/drm/amd/pm/inc/
Damdgpu_dpm.h53 u32 vclk; member
142 u32 vclk; member

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