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Searched refs:uint32_t (Results 1 – 25 of 2518) sorted by relevance

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/linux-5.19.10/drivers/gpu/drm/amd/include/
Dv11_structs.h28 uint32_t reserved_0; // offset: 0 (0x0)
29 uint32_t reserved_1; // offset: 1 (0x1)
30 uint32_t reserved_2; // offset: 2 (0x2)
31 uint32_t reserved_3; // offset: 3 (0x3)
32 uint32_t reserved_4; // offset: 4 (0x4)
33 uint32_t reserved_5; // offset: 5 (0x5)
34 uint32_t reserved_6; // offset: 6 (0x6)
35 uint32_t reserved_7; // offset: 7 (0x7)
36 uint32_t reserved_8; // offset: 8 (0x8)
37 uint32_t reserved_9; // offset: 9 (0x9)
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Dv10_structs.h29 uint32_t reserved_0; // offset: 0 (0x0)
30 uint32_t reserved_1; // offset: 1 (0x1)
31 uint32_t reserved_2; // offset: 2 (0x2)
32 uint32_t reserved_3; // offset: 3 (0x3)
33 uint32_t reserved_4; // offset: 4 (0x4)
34 uint32_t reserved_5; // offset: 5 (0x5)
35 uint32_t reserved_6; // offset: 6 (0x6)
36 uint32_t reserved_7; // offset: 7 (0x7)
37 uint32_t reserved_8; // offset: 8 (0x8)
38 uint32_t reserved_9; // offset: 9 (0x9)
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Dv9_structs.h28 uint32_t sdmax_rlcx_rb_cntl;
29 uint32_t sdmax_rlcx_rb_base;
30 uint32_t sdmax_rlcx_rb_base_hi;
31 uint32_t sdmax_rlcx_rb_rptr;
32 uint32_t sdmax_rlcx_rb_rptr_hi;
33 uint32_t sdmax_rlcx_rb_wptr;
34 uint32_t sdmax_rlcx_rb_wptr_hi;
35 uint32_t sdmax_rlcx_rb_wptr_poll_cntl;
36 uint32_t sdmax_rlcx_rb_rptr_addr_hi;
37 uint32_t sdmax_rlcx_rb_rptr_addr_lo;
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Dvi_structs.h28 uint32_t sdmax_rlcx_rb_cntl;
29 uint32_t sdmax_rlcx_rb_base;
30 uint32_t sdmax_rlcx_rb_base_hi;
31 uint32_t sdmax_rlcx_rb_rptr;
32 uint32_t sdmax_rlcx_rb_wptr;
33 uint32_t sdmax_rlcx_rb_wptr_poll_cntl;
34 uint32_t sdmax_rlcx_rb_wptr_poll_addr_hi;
35 uint32_t sdmax_rlcx_rb_wptr_poll_addr_lo;
36 uint32_t sdmax_rlcx_rb_rptr_addr_hi;
37 uint32_t sdmax_rlcx_rb_rptr_addr_lo;
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Dcik_structs.h28 uint32_t header;
29 uint32_t compute_dispatch_initiator;
30 uint32_t compute_dim_x;
31 uint32_t compute_dim_y;
32 uint32_t compute_dim_z;
33 uint32_t compute_start_x;
34 uint32_t compute_start_y;
35 uint32_t compute_start_z;
36 uint32_t compute_num_thread_x;
37 uint32_t compute_num_thread_y;
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Ddiscovery.h59 uint32_t binary_signature; /* 0x7, 0x14, 0x21, 0x28 */
76 uint32_t signature; /* Table Signature */
79 uint32_t id; /* Table ID */
100 uint32_t base_address[]; /* variable number of Addresses */
118 …uint32_t base_address[1]; /* Base Address list. Corresponds to the num_base_address …
142 uint32_t table_id; /* table ID */
145 uint32_t size; /* size of the entire header+data in bytes */
151 uint32_t gc_num_se;
152 uint32_t gc_num_wgp0_per_sa;
153 uint32_t gc_num_wgp1_per_sa;
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Dmes_api_def.h69 uint32_t type : 4; /* 0 - Invalid; 1 - Scheduling; 2 - TBD */
70 uint32_t opcode : 8;
71 uint32_t dwsize : 8; /* including header */
72 uint32_t reserved : 12;
75 uint32_t u32All;
163 uint32_t first_free_entry_index;
164 uint32_t wraparound_count;
171 uint32_t operation_type; /* operation_type is of MES_LOG_OPERATION type */
172 uint32_t reserved_operation_type_bits;
195 uint32_t vmid_mask_mmhub;
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/linux-5.19.10/arch/mips/include/asm/octeon/
Dcvmx-pciercx-defs.h55 uint32_t u32;
57 __BITFIELD_FIELD(uint32_t dpe:1,
58 __BITFIELD_FIELD(uint32_t sse:1,
59 __BITFIELD_FIELD(uint32_t rma:1,
60 __BITFIELD_FIELD(uint32_t rta:1,
61 __BITFIELD_FIELD(uint32_t sta:1,
62 __BITFIELD_FIELD(uint32_t devt:2,
63 __BITFIELD_FIELD(uint32_t mdpe:1,
64 __BITFIELD_FIELD(uint32_t fbb:1,
65 __BITFIELD_FIELD(uint32_t reserved_22_22:1,
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Dcvmx-pci-defs.h118 uint32_t u32;
121 uint32_t reserved_18_31:14;
122 uint32_t addr_idx:14;
123 uint32_t ca:1;
124 uint32_t end_swp:2;
125 uint32_t addr_v:1;
127 uint32_t addr_v:1;
128 uint32_t end_swp:2;
129 uint32_t ca:1;
130 uint32_t addr_idx:14;
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/linux-5.19.10/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5.xml.h191 static inline uint32_t MDSS_HW_VERSION_STEP(uint32_t val) in MDSS_HW_VERSION_STEP()
197 static inline uint32_t MDSS_HW_VERSION_MINOR(uint32_t val) in MDSS_HW_VERSION_MINOR()
203 static inline uint32_t MDSS_HW_VERSION_MAJOR(uint32_t val) in MDSS_HW_VERSION_MAJOR()
218 static inline uint32_t MDP5_HW_VERSION_STEP(uint32_t val) in MDP5_HW_VERSION_STEP()
224 static inline uint32_t MDP5_HW_VERSION_MINOR(uint32_t val) in MDP5_HW_VERSION_MINOR()
230 static inline uint32_t MDP5_HW_VERSION_MAJOR(uint32_t val) in MDP5_HW_VERSION_MAJOR()
238 static inline uint32_t MDP5_DISP_INTF_SEL_INTF0(enum mdp5_intf_type val) in MDP5_DISP_INTF_SEL_INTF0()
244 static inline uint32_t MDP5_DISP_INTF_SEL_INTF1(enum mdp5_intf_type val) in MDP5_DISP_INTF_SEL_INTF1()
250 static inline uint32_t MDP5_DISP_INTF_SEL_INTF2(enum mdp5_intf_type val) in MDP5_DISP_INTF_SEL_INTF2()
256 static inline uint32_t MDP5_DISP_INTF_SEL_INTF3(enum mdp5_intf_type val) in MDP5_DISP_INTF_SEL_INTF3()
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/linux-5.19.10/drivers/gpu/drm/amd/amdkfd/
Dkfd_pm4_headers_ai.h32 uint32_t reserved1 : 8; /* < reserved */
33 uint32_t opcode : 8; /* < IT opcode */
34 uint32_t count : 14;/* < number of DWORDs - 1 in the
37 uint32_t type : 2; /* < packet identifier.
41 uint32_t u32All;
59 uint32_t ordinal1;
64 uint32_t vmid_mask:16;
65 uint32_t unmap_latency:8;
66 uint32_t reserved1:5;
69 uint32_t ordinal2;
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Dkfd_pm4_headers_vi.h32 uint32_t reserved1 : 8; /* < reserved */
33 uint32_t opcode : 8; /* < IT opcode */
34 uint32_t count : 14;/* < Number of DWORDS - 1 in the
37 uint32_t type : 2; /* < packet identifier
41 uint32_t u32All;
59 uint32_t ordinal1;
64 uint32_t vmid_mask:16;
65 uint32_t unmap_latency:8;
66 uint32_t reserved1:5;
69 uint32_t ordinal2;
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Dkfd_pm4_headers.h33 uint32_t reserved1:8;
35 uint32_t opcode:8;
37 uint32_t count:14;
39 uint32_t type:2;
41 uint32_t u32all;
54 uint32_t ordinal1;
59 uint32_t pasid:16;
60 uint32_t reserved1:8;
61 uint32_t diq_enable:1;
62 uint32_t process_quantum:7;
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/linux-5.19.10/drivers/scsi/arcmsr/
Darcmsr.h99 #define dma_addr_hi32(addr) (uint32_t) ((addr>>16)>>16)
100 #define dma_addr_lo32(addr) (uint32_t) (addr & 0xffffffff)
108 uint32_t HeaderLength;
110 uint32_t Timeout;
111 uint32_t ControlCode;
112 uint32_t ReturnCode;
113 uint32_t Length;
191 uint32_t data_len;
201 uint32_t signature; /*0, 00-03*/
202 uint32_t request_len; /*1, 04-07*/
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/linux-5.19.10/drivers/gpu/drm/amd/display/include/
Dgrph_object_ctrl_defs.h67 uint32_t enum_id:16; /* 1 based enum */
73 uint32_t clk_mask_register_index;
74 uint32_t clk_en_register_index;
75 uint32_t clk_y_register_index;
76 uint32_t clk_a_register_index;
77 uint32_t data_mask_register_index;
78 uint32_t data_en_register_index;
79 uint32_t data_y_register_index;
80 uint32_t data_a_register_index;
82 uint32_t clk_mask_shift;
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/linux-5.19.10/sound/soc/qcom/qdsp6/
Daudioreach.h59 uint32_t property_flag;
63 uint32_t shm_addr_lsw;
64 uint32_t shm_addr_msw;
65 uint32_t mem_size_bytes;
69 uint32_t mem_map_handle;
73 uint32_t mem_map_handle;
82 uint32_t num_modules_list;
88 uint32_t num_modules_prop_cfg;
92 uint32_t instance_id;
93 uint32_t num_props;
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/linux-5.19.10/tools/firewire/
Dnosy-dump.h15 uint32_t timestamp;
18 uint32_t zero:24;
19 uint32_t phy_id:6;
20 uint32_t identifier:2;
24 uint32_t zero:16;
25 uint32_t gap_count:6;
26 uint32_t set_gap_count:1;
27 uint32_t set_root:1;
28 uint32_t root_id:6;
29 uint32_t identifier:2;
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/linux-5.19.10/drivers/gpu/drm/msm/disp/mdp4/
Dmdp4.xml.h120 static inline uint32_t MDP4_VERSION_MINOR(uint32_t val) in MDP4_VERSION_MINOR()
126 static inline uint32_t MDP4_VERSION_MAJOR(uint32_t val) in MDP4_VERSION_MAJOR()
148 static inline uint32_t MDP4_DISP_INTF_SEL_PRIM(enum mdp4_intf val) in MDP4_DISP_INTF_SEL_PRIM()
154 static inline uint32_t MDP4_DISP_INTF_SEL_SEC(enum mdp4_intf val) in MDP4_DISP_INTF_SEL_SEC()
160 static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val) in MDP4_DISP_INTF_SEL_EXT()
190 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER2_IN_CFG_PIPE0()
197 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER2_IN_CFG_PIPE1()
204 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER2_IN_CFG_PIPE2()
211 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER2_IN_CFG_PIPE3()
218 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER2_IN_CFG_PIPE4()
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/linux-5.19.10/drivers/gpu/drm/meson/
Dmeson_drv.h63 uint32_t osd1_ctrl_stat;
64 uint32_t osd1_ctrl_stat2;
65 uint32_t osd1_blk0_cfg[5];
66 uint32_t osd1_blk1_cfg4;
67 uint32_t osd1_blk2_cfg4;
68 uint32_t osd1_addr;
69 uint32_t osd1_stride;
70 uint32_t osd1_height;
71 uint32_t osd1_width;
72 uint32_t osd_sc_ctrl0;
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/linux-5.19.10/drivers/scsi/lpfc/
Dlpfc_hw.h80 uint32_t Revision:8;
81 uint32_t InId:24;
83 uint32_t word;
89 uint32_t CmdRsp:16;
90 uint32_t Size:16;
92 uint32_t word;
127 uint32_t PortID;
155 uint32_t PortId; /* For RNN_ID requests */
164 uint32_t port_id;
167 uint32_t PortId;
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/linux-5.19.10/fs/xfs/
Dxfs_stats.h44 uint32_t xs_allocx;
45 uint32_t xs_allocb;
46 uint32_t xs_freex;
47 uint32_t xs_freeb;
48 uint32_t xs_abt_lookup;
49 uint32_t xs_abt_compare;
50 uint32_t xs_abt_insrec;
51 uint32_t xs_abt_delrec;
52 uint32_t xs_blk_mapr;
53 uint32_t xs_blk_mapw;
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/linux-5.19.10/drivers/gpu/drm/msm/adreno/
Da6xx.xml.h1079 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_RB_LO(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_RB_LO()
1085 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_RB_HI(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_RB_HI()
1091 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB1_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_IB1_START()
1097 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_IB2_START()
1105 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_SDS_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_2_SDS_START()
1111 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE()
1126 static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; } in REG_A6XX_CP_SCRATCH()
1128 static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000883 + 0x1*i0; } in REG_A6XX_CP_SCRATCH_REG()
1130 static inline uint32_t REG_A6XX_CP_PROTECT(uint32_t i0) { return 0x00000850 + 0x1*i0; } in REG_A6XX_CP_PROTECT()
1132 static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000850 + 0x1*i0; } in REG_A6XX_CP_PROTECT_REG()
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Dadreno_pm4.xml.h488 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val) in CP_LOAD_STATE_0_DST_OFF()
494 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val) in CP_LOAD_STATE_0_STATE_SRC()
500 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val) in CP_LOAD_STATE_0_STATE_BLOCK()
506 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val) in CP_LOAD_STATE_0_NUM_UNIT()
514 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val) in CP_LOAD_STATE_1_STATE_TYPE()
520 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val) in CP_LOAD_STATE_1_EXT_SRC_ADDR()
528 static inline uint32_t CP_LOAD_STATE4_0_DST_OFF(uint32_t val) in CP_LOAD_STATE4_0_DST_OFF()
534 static inline uint32_t CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val) in CP_LOAD_STATE4_0_STATE_SRC()
540 static inline uint32_t CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val) in CP_LOAD_STATE4_0_STATE_BLOCK()
546 static inline uint32_t CP_LOAD_STATE4_0_NUM_UNIT(uint32_t val) in CP_LOAD_STATE4_0_NUM_UNIT()
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/linux-5.19.10/drivers/gpu/drm/amd/amdgpu/
Damdgpu_ucode.h29 uint32_t size_bytes; /* size of the entire header+image(s) in bytes */
30 uint32_t header_size_bytes; /* size of just the header in bytes */
35 uint32_t ucode_version;
36 uint32_t ucode_size_bytes; /* size of ucode in bytes */
37 uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */
38 uint32_t crc32; /* crc32 checksum of the payload */
44 uint32_t io_debug_size_bytes; /* size of debug array in dwords */
45 uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */
51 uint32_t ucode_start_addr;
57 uint32_t ppt_offset_bytes; /* soft pptable offset */
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/linux-5.19.10/include/uapi/linux/
Dfuse.h247 uint32_t atimensec;
248 uint32_t mtimensec;
249 uint32_t ctimensec;
250 uint32_t mode;
251 uint32_t nlink;
252 uint32_t uid;
253 uint32_t gid;
254 uint32_t rdev;
255 uint32_t blksize;
256 uint32_t flags;
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