| /linux-5.19.10/drivers/gpu/drm/amd/display/dc/dcn201/ |
| D | dcn201_optc.c | 39 optc1->tg_shift->field_name, optc1->tg_mask->field_name
195 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn201_timing_generator_init()
196 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn201_timing_generator_init()
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| D | dcn201_resource.c | 513 static const struct dcn_optc_mask tg_mask = { variable
771 tgn10->tg_mask = &tg_mask; in dcn201_timing_generator_create()
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| /linux-5.19.10/drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_optc.c | 41 optc1->tg_shift->field_name, optc1->tg_mask->field_name
302 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn31_timing_generator_init()
303 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn31_timing_generator_init()
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| D | dcn31_resource.c | 1077 tgn10->tg_mask = &optc_mask; in dcn31_timing_generator_create()
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| /linux-5.19.10/drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_optc.c | 41 optc1->tg_shift->field_name, optc1->tg_mask->field_name
365 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn30_timing_generator_init()
366 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn30_timing_generator_init()
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| D | dcn30_resource.c | 909 tgn10->tg_mask = &optc_mask; in dcn30_timing_generator_create()
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| /linux-5.19.10/drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_optc.c | 38 optc1->tg_shift->field_name, optc1->tg_mask->field_name
562 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn20_timing_generator_init()
563 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn20_timing_generator_init()
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| D | dcn20_resource.c | 511 static const struct dcn_optc_mask tg_mask = { variable
908 tgn10->tg_mask = &tg_mask; in dcn20_timing_generator_create()
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| /linux-5.19.10/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_optc.c | 39 optc1->tg_shift->field_name, optc1->tg_mask->field_name
291 if (REG(OPTC_DATA_FORMAT_CONTROL) && optc1->tg_mask->OPTC_DATA_FORMAT != 0) { in optc1_program_timing()
302 if (optc1->tg_mask->OTG_H_TIMING_DIV_MODE != 0) { in optc1_program_timing()
1574 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn10_timing_generator_init()
1575 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn10_timing_generator_init()
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| D | dcn10_resource.c | 404 static const struct dcn_optc_mask tg_mask = { variable
726 tgn10->tg_mask = &tg_mask; in dcn10_timing_generator_create()
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| D | dcn10_optc.h | 538 const struct dcn_optc_mask *tg_mask; member
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| /linux-5.19.10/drivers/net/ethernet/mscc/ |
| D | ocelot_vcap.c | 46 u32 tg_mask; /* Current type-group mask */ member
199 data->tg_mask = 0; in vcap_data_offset_get()
203 data->tg_mask |= GENMASK(offset + width - 1, offset); in vcap_data_offset_get()
365 data.tg = (data.tg & ~data.tg_mask); in is2_entry_set()
688 data.tg = (data.tg & ~data.tg_mask); in is1_entry_set()
826 data.tg = (data.tg & ~data.tg_mask); in es0_entry_set()
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| /linux-5.19.10/drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_resource.c | 274 static const struct dcn_optc_mask tg_mask = { variable
1083 tgn10->tg_mask = &tg_mask; in dcn21_timing_generator_create()
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| /linux-5.19.10/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| D | dcn30_fpu.c | 44 optc1->tg_shift->field_name, optc1->tg_mask->field_name
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| /linux-5.19.10/drivers/gpu/drm/amd/display/dc/dcn302/ |
| D | dcn302_resource.c | 620 tgn10->tg_mask = &optc_mask; in dcn302_timing_generator_create()
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| /linux-5.19.10/drivers/gpu/drm/amd/display/dc/dcn303/ |
| D | dcn303_resource.c | 575 tgn10->tg_mask = &optc_mask; in dcn303_timing_generator_create()
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| /linux-5.19.10/drivers/gpu/drm/amd/display/dc/dcn301/ |
| D | dcn301_resource.c | 873 tgn10->tg_mask = &optc_mask; in dcn301_timing_generator_create()
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| /linux-5.19.10/drivers/gpu/drm/amd/display/dc/dcn315/ |
| D | dcn315_resource.c | 1072 tgn10->tg_mask = &optc_mask; in dcn31_timing_generator_create()
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| /linux-5.19.10/drivers/gpu/drm/amd/display/dc/dcn316/ |
| D | dcn316_resource.c | 1071 tgn10->tg_mask = &optc_mask; in dcn31_timing_generator_create()
|