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Searched refs:smu_wm_set (Results 1 – 8 of 8) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
Ddcn316_clk_mgr.c413 struct dcn316_watermarks *table = clk_mgr_dcn316->smu_wm_set.wm_set; in dcn316_notify_wm_ranges()
418 if (!table || clk_mgr_dcn316->smu_wm_set.mc_address.quad_part == 0) in dcn316_notify_wm_ranges()
426 clk_mgr_dcn316->smu_wm_set.mc_address.high_part); in dcn316_notify_wm_ranges()
428 clk_mgr_dcn316->smu_wm_set.mc_address.low_part); in dcn316_notify_wm_ranges()
633 clk_mgr->smu_wm_set.wm_set = (struct dcn316_watermarks *)dm_helpers_allocate_gpu_mem( in dcn316_clk_mgr_construct()
637 &clk_mgr->smu_wm_set.mc_address.quad_part); in dcn316_clk_mgr_construct()
639 if (!clk_mgr->smu_wm_set.wm_set) { in dcn316_clk_mgr_construct()
640 clk_mgr->smu_wm_set.wm_set = &dummy_wms; in dcn316_clk_mgr_construct()
641 clk_mgr->smu_wm_set.mc_address.quad_part = 0; in dcn316_clk_mgr_construct()
643 ASSERT(clk_mgr->smu_wm_set.wm_set); in dcn316_clk_mgr_construct()
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Ddcn316_clk_mgr.h39 struct dcn316_smu_watermark_set smu_wm_set; member
/linux-5.19.10/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
Dvg_clk_mgr.c445 struct watermarks *table = clk_mgr_vgh->smu_wm_set.wm_set; in vg_notify_wm_ranges()
450 if (!table || clk_mgr_vgh->smu_wm_set.mc_address.quad_part == 0) in vg_notify_wm_ranges()
458 clk_mgr_vgh->smu_wm_set.mc_address.high_part); in vg_notify_wm_ranges()
460 clk_mgr_vgh->smu_wm_set.mc_address.low_part); in vg_notify_wm_ranges()
737 clk_mgr->smu_wm_set.wm_set = (struct watermarks *)dm_helpers_allocate_gpu_mem( in vg_clk_mgr_construct()
741 &clk_mgr->smu_wm_set.mc_address.quad_part); in vg_clk_mgr_construct()
743 if (!clk_mgr->smu_wm_set.wm_set) { in vg_clk_mgr_construct()
744 clk_mgr->smu_wm_set.wm_set = &dummy_wms; in vg_clk_mgr_construct()
745 clk_mgr->smu_wm_set.mc_address.quad_part = 0; in vg_clk_mgr_construct()
747 ASSERT(clk_mgr->smu_wm_set.wm_set); in vg_clk_mgr_construct()
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Dvg_clk_mgr.h39 struct smu_watermark_set smu_wm_set; member
/linux-5.19.10/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
Ddcn31_clk_mgr.c472 struct dcn31_watermarks *table = clk_mgr_dcn31->smu_wm_set.wm_set; in dcn31_notify_wm_ranges()
477 if (!table || clk_mgr_dcn31->smu_wm_set.mc_address.quad_part == 0) in dcn31_notify_wm_ranges()
485 clk_mgr_dcn31->smu_wm_set.mc_address.high_part); in dcn31_notify_wm_ranges()
487 clk_mgr_dcn31->smu_wm_set.mc_address.low_part); in dcn31_notify_wm_ranges()
682 clk_mgr->smu_wm_set.wm_set = (struct dcn31_watermarks *)dm_helpers_allocate_gpu_mem( in dcn31_clk_mgr_construct()
686 &clk_mgr->smu_wm_set.mc_address.quad_part); in dcn31_clk_mgr_construct()
688 if (!clk_mgr->smu_wm_set.wm_set) { in dcn31_clk_mgr_construct()
689 clk_mgr->smu_wm_set.wm_set = &dummy_wms; in dcn31_clk_mgr_construct()
690 clk_mgr->smu_wm_set.mc_address.quad_part = 0; in dcn31_clk_mgr_construct()
692 ASSERT(clk_mgr->smu_wm_set.wm_set); in dcn31_clk_mgr_construct()
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Ddcn31_clk_mgr.h39 struct dcn31_smu_watermark_set smu_wm_set; member
/linux-5.19.10/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
Ddcn315_clk_mgr.c407 struct dcn315_watermarks *table = clk_mgr_dcn315->smu_wm_set.wm_set; in dcn315_notify_wm_ranges()
412 if (!table || clk_mgr_dcn315->smu_wm_set.mc_address.quad_part == 0) in dcn315_notify_wm_ranges()
420 clk_mgr_dcn315->smu_wm_set.mc_address.high_part); in dcn315_notify_wm_ranges()
422 clk_mgr_dcn315->smu_wm_set.mc_address.low_part); in dcn315_notify_wm_ranges()
611 clk_mgr->smu_wm_set.wm_set = (struct dcn315_watermarks *)dm_helpers_allocate_gpu_mem( in dcn315_clk_mgr_construct()
615 &clk_mgr->smu_wm_set.mc_address.quad_part); in dcn315_clk_mgr_construct()
617 if (!clk_mgr->smu_wm_set.wm_set) { in dcn315_clk_mgr_construct()
618 clk_mgr->smu_wm_set.wm_set = &dummy_wms; in dcn315_clk_mgr_construct()
619 clk_mgr->smu_wm_set.mc_address.quad_part = 0; in dcn315_clk_mgr_construct()
621 ASSERT(clk_mgr->smu_wm_set.wm_set); in dcn315_clk_mgr_construct()
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Ddcn315_clk_mgr.h39 struct dcn315_smu_watermark_set smu_wm_set; member