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/linux-5.19.10/arch/arm/nwfpe/
Dsoftfloat-macros35 bits are shifted off, they are ``jammed'' into the least significant bit of
60 bits are shifted off, they are ``jammed'' into the least significant bit of
88 _plus_ the number of bits given in `count'. The shifted result is at most
90 bits shifted off form a second 64-bit result as follows: The _last_ bit
91 shifted off is the most-significant bit of the extra result, and the other
93 bits shifted off were all zero. This extra result is stored in the location
97 value is shifted right by the number of bits given in `count', and the
135 number of bits given in `count'. Any bits shifted off are lost. The value
168 number of bits given in `count'. If any nonzero bits are shifted off, they
212 by 64 _plus_ the number of bits given in `count'. The shifted result is
[all …]
/linux-5.19.10/net/sunrpc/auth_gss/
Dgss_krb5_wrap.c389 int shifted = 0; in _rotate_left() local
393 while (shifted < shift) { in _rotate_left()
394 this_shift = min(shift - shifted, LOCAL_BUF_LEN); in _rotate_left()
396 shifted += this_shift; in _rotate_left()
/linux-5.19.10/Documentation/devicetree/bindings/i3c/
Di3c.yaml125 Contains the manufacturer ID left-shifted by 1.
130 Contains the ORing of the part ID left-shifted by 16,
131 the instance ID left-shifted by 12 and extra information.
/linux-5.19.10/Documentation/driver-api/
Dspi.rst9 duplex protocol; for each bit shifted out the MOSI line (one per clock)
10 another is shifted in on the MISO line. Those bits are assembled into
/linux-5.19.10/arch/arm/mm/
Dcache-v7.S49 mov r3, r3, lsl r1 @ NumWays-1 shifted into bits [31:...]
50 movs r1, r2, lsl r1 @ #1 shifted left by same amount
155 movne r4, r4, lsl r5 @ # of ways shifted into bits [31:...]
156 movne r6, r6, lsl r5 @ 1 shifted left by same amount
/linux-5.19.10/drivers/media/rc/
Dserial_ir.c181 unsigned char chunk, shifted; in send_pulse_irdeo() local
190 shifted = chunk << (i * 3); in send_pulse_irdeo()
191 shifted >>= 1; in send_pulse_irdeo()
192 output &= (~shifted); in send_pulse_irdeo()
/linux-5.19.10/Documentation/devicetree/bindings/rtc/
Depson,rx6110.txt28 - spi-cpha: RX6110 works with SPI shifted clock phase
Drtc.yaml39 shifted so the first usable year is the specified one.
/linux-5.19.10/Documentation/ABI/testing/
Dsysfs-driver-hid-prodikeys26 The octave can be shifted via software up/down 2 octaves.
/linux-5.19.10/arch/m68k/fpsp040/
Dsgetem.S109 | shifted bits in d0 and d1
134 | ;be shifted into ms mant
Dround.S375 | ;be shifted into ms mant
445 | ; shifted off in denorm routine)
458 | ; shifted off in denorm routine)
Dbinstr.S17 | shift and a mul by 8 shift. The bits shifted out of the
/linux-5.19.10/Documentation/devicetree/bindings/bus/
Dmoxtet.txt8 - spi-cpha : Required shifted clock phase
/linux-5.19.10/arch/powerpc/lib/
Ddiv64.S39 divwu r11,r11,r9 # then we divide the shifted quantities
/linux-5.19.10/Documentation/i2c/
Dslave-interface.rst110 only means that the previous byte is shifted out to the bus! To ensure seamless
112 still shifted out. If the master sends NACK and stops reading after the byte
113 currently shifted out, this byte requested here is never used. It very likely
/linux-5.19.10/sound/soc/cirrus/
DKconfig21 state machine and the whole stream can be shifted by one byte
/linux-5.19.10/arch/sh/kernel/
Dentry-common.S262 * Note: When we're first called, the TRA value must be shifted
/linux-5.19.10/Documentation/devicetree/bindings/mux/
Dreg-mux.yaml32 - description: pre-shifted bitfield mask
/linux-5.19.10/Documentation/devicetree/bindings/i2c/
Di2c-ocores.txt26 - reg-shift : device register offsets are shifted by this value
/linux-5.19.10/Documentation/driver-api/media/drivers/
Dcx88-devel.rst88 Bits are then right shifted into the GP_SAMPLE register at the specified
/linux-5.19.10/arch/powerpc/boot/
Ddiv64.S39 divwu r11,r11,r9 # then we divide the shifted quantities
/linux-5.19.10/Documentation/input/devices/
Drotary-encoder.rst11 peripherals with two wires. The outputs are phase-shifted by 90 degrees
/linux-5.19.10/Documentation/devicetree/bindings/spi/
Dspi-peripheral-props.yaml40 The device requires shifted clock phase (CPHA) mode.
/linux-5.19.10/arch/parisc/kernel/
Dperf_asm.S86 ;* is shifted shifted backup immediately. This is to compensate
/linux-5.19.10/Documentation/staging/
Dcrc32.rst53 Notice how, to get at bit 32 of the shifted remainder, we look
167 in parallel. Each step, the 32-bit CRC is shifted 64 bits and XORed

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