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Searched refs:se_mask (Results 1 – 25 of 36) sorted by relevance

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/linux-5.19.10/drivers/gpu/drm/amd/amdkfd/
Dkfd_mqd_manager_v11.c48 uint32_t se_mask[KFD_MAX_NUM_SE] = {0}; in update_cu_mask() local
55 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask); in update_cu_mask()
58 m->compute_static_thread_mgmt_se0 = se_mask[0]; in update_cu_mask()
59 m->compute_static_thread_mgmt_se1 = se_mask[1]; in update_cu_mask()
60 m->compute_static_thread_mgmt_se2 = se_mask[2]; in update_cu_mask()
61 m->compute_static_thread_mgmt_se3 = se_mask[3]; in update_cu_mask()
62 m->compute_static_thread_mgmt_se4 = se_mask[4]; in update_cu_mask()
63 m->compute_static_thread_mgmt_se5 = se_mask[5]; in update_cu_mask()
64 m->compute_static_thread_mgmt_se6 = se_mask[6]; in update_cu_mask()
65 m->compute_static_thread_mgmt_se7 = se_mask[7]; in update_cu_mask()
Dkfd_mqd_manager_v9.c50 uint32_t se_mask[KFD_MAX_NUM_SE] = {0}; in update_cu_mask() local
57 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask); in update_cu_mask()
60 m->compute_static_thread_mgmt_se0 = se_mask[0]; in update_cu_mask()
61 m->compute_static_thread_mgmt_se1 = se_mask[1]; in update_cu_mask()
62 m->compute_static_thread_mgmt_se2 = se_mask[2]; in update_cu_mask()
63 m->compute_static_thread_mgmt_se3 = se_mask[3]; in update_cu_mask()
64 m->compute_static_thread_mgmt_se4 = se_mask[4]; in update_cu_mask()
65 m->compute_static_thread_mgmt_se5 = se_mask[5]; in update_cu_mask()
66 m->compute_static_thread_mgmt_se6 = se_mask[6]; in update_cu_mask()
67 m->compute_static_thread_mgmt_se7 = se_mask[7]; in update_cu_mask()
Dkfd_mqd_manager_cik.c49 uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */ in update_cu_mask() local
56 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask); in update_cu_mask()
59 m->compute_static_thread_mgmt_se0 = se_mask[0]; in update_cu_mask()
60 m->compute_static_thread_mgmt_se1 = se_mask[1]; in update_cu_mask()
61 m->compute_static_thread_mgmt_se2 = se_mask[2]; in update_cu_mask()
62 m->compute_static_thread_mgmt_se3 = se_mask[3]; in update_cu_mask()
Dkfd_mqd_manager_v10.c49 uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */ in update_cu_mask() local
56 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask); in update_cu_mask()
59 m->compute_static_thread_mgmt_se0 = se_mask[0]; in update_cu_mask()
60 m->compute_static_thread_mgmt_se1 = se_mask[1]; in update_cu_mask()
61 m->compute_static_thread_mgmt_se2 = se_mask[2]; in update_cu_mask()
62 m->compute_static_thread_mgmt_se3 = se_mask[3]; in update_cu_mask()
Dkfd_mqd_manager_vi.c52 uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */ in update_cu_mask() local
59 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask); in update_cu_mask()
62 m->compute_static_thread_mgmt_se0 = se_mask[0]; in update_cu_mask()
63 m->compute_static_thread_mgmt_se1 = se_mask[1]; in update_cu_mask()
64 m->compute_static_thread_mgmt_se2 = se_mask[2]; in update_cu_mask()
65 m->compute_static_thread_mgmt_se3 = se_mask[3]; in update_cu_mask()
Dkfd_mqd_manager.c99 uint32_t *se_mask) in mqd_symmetrically_map_cu_mask() argument
167 se_mask[i] = 0; in mqd_symmetrically_map_cu_mask()
175 se_mask[se] |= 1 << (cu + sh * 16); in mqd_symmetrically_map_cu_mask()
Dkfd_mqd_manager.h138 uint32_t *se_mask);
/linux-5.19.10/drivers/gpu/drm/amd/display/dc/dce/
Ddce_stream_encoder.c42 enc110->se_shift->field_name, enc110->se_mask->field_name
324 if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN) in dce110_stream_encoder_dp_set_stream_attribute()
327 if (enc110->se_mask->DP_VID_N_MUL) in dce110_stream_encoder_dp_set_stream_attribute()
441 if (enc110->se_mask->DP_DYN_RANGE && enc110->se_mask->DP_YCBCR_RANGE) in dce110_stream_encoder_dp_set_stream_attribute()
560 if (!enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) { in dce110_stream_encoder_hdmi_set_stream_attribute()
609 if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) { in dce110_stream_encoder_hdmi_set_stream_attribute()
732 if (enc110->se_mask->HDMI_AVI_INFO_CONT && in dce110_stream_encoder_update_hdmi_info_packets()
733 enc110->se_mask->HDMI_AVI_INFO_SEND) { in dce110_stream_encoder_update_hdmi_info_packets()
767 if (enc110->se_mask->HDMI_AVI_INFO_CONT && in dce110_stream_encoder_update_hdmi_info_packets()
768 enc110->se_mask->HDMI_AVI_INFO_SEND) { in dce110_stream_encoder_update_hdmi_info_packets()
[all …]
Ddce_stream_encoder.h701 const struct dce_stream_encoder_mask *se_mask; member
711 const struct dce_stream_encoder_mask *se_mask);
/linux-5.19.10/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_stream_encoder.c44 enc1->se_shift->field_name, enc1->se_mask->field_name
631 const struct dcn10_stream_encoder_mask *se_mask) in dcn20_stream_encoder_construct() argument
639 enc1->se_mask = se_mask; in dcn20_stream_encoder_construct()
Ddcn20_stream_encoder.h97 const struct dcn10_stream_encoder_mask *se_mask);
/linux-5.19.10/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_dio_stream_encoder.c44 enc1->se_shift->field_name, enc1->se_mask->field_name
829 const struct dcn10_stream_encoder_mask *se_mask) in dcn30_dio_stream_encoder_construct() argument
839 enc1->se_mask = se_mask; in dcn30_dio_stream_encoder_construct()
Ddcn30_dio_stream_encoder.h288 const struct dcn10_stream_encoder_mask *se_mask);
/linux-5.19.10/drivers/gpu/drm/amd/amdgpu/
Dgfx_v7_0.c1678 unsigned se_mask[4]; in gfx_v7_0_write_harvested_raster_configs() local
1681 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; in gfx_v7_0_write_harvested_raster_configs()
1682 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; in gfx_v7_0_write_harvested_raster_configs()
1683 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask; in gfx_v7_0_write_harvested_raster_configs()
1684 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask; in gfx_v7_0_write_harvested_raster_configs()
1690 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) || in gfx_v7_0_write_harvested_raster_configs()
1691 (!se_mask[2] && !se_mask[3]))) { in gfx_v7_0_write_harvested_raster_configs()
1694 if (!se_mask[0] && !se_mask[1]) { in gfx_v7_0_write_harvested_raster_configs()
1709 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { in gfx_v7_0_write_harvested_raster_configs()
1712 if (!se_mask[idx]) { in gfx_v7_0_write_harvested_raster_configs()
Dgfx_v6_0.c1381 unsigned se_mask[4]; in gfx_v6_0_write_harvested_raster_configs() local
1384 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; in gfx_v6_0_write_harvested_raster_configs()
1385 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; in gfx_v6_0_write_harvested_raster_configs()
1386 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask; in gfx_v6_0_write_harvested_raster_configs()
1387 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask; in gfx_v6_0_write_harvested_raster_configs()
1399 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { in gfx_v6_0_write_harvested_raster_configs()
1402 if (!se_mask[idx]) in gfx_v6_0_write_harvested_raster_configs()
Dgfx_v8_0.c3517 unsigned se_mask[4]; in gfx_v8_0_write_harvested_raster_configs() local
3520 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; in gfx_v8_0_write_harvested_raster_configs()
3521 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; in gfx_v8_0_write_harvested_raster_configs()
3522 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask; in gfx_v8_0_write_harvested_raster_configs()
3523 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask; in gfx_v8_0_write_harvested_raster_configs()
3529 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) || in gfx_v8_0_write_harvested_raster_configs()
3530 (!se_mask[2] && !se_mask[3]))) { in gfx_v8_0_write_harvested_raster_configs()
3533 if (!se_mask[0] && !se_mask[1]) { in gfx_v8_0_write_harvested_raster_configs()
3548 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { in gfx_v8_0_write_harvested_raster_configs()
3551 if (!se_mask[idx]) { in gfx_v8_0_write_harvested_raster_configs()
/linux-5.19.10/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_stream_encoder.c46 enc1->se_shift->field_name, enc1->se_mask->field_name
1619 const struct dcn10_stream_encoder_mask *se_mask) in dcn10_stream_encoder_construct() argument
1627 enc1->se_mask = se_mask; in dcn10_stream_encoder_construct()
Ddcn10_stream_encoder.h586 const struct dcn10_stream_encoder_mask *se_mask; member
596 const struct dcn10_stream_encoder_mask *se_mask);
/linux-5.19.10/drivers/gpu/drm/amd/display/dc/dce100/
Ddce100_resource.c251 static const struct dce_stream_encoder_mask se_mask = { variable
485 &stream_enc_regs[eng_id], &se_shift, &se_mask); in dce100_stream_encoder_create()
/linux-5.19.10/drivers/gpu/drm/amd/display/dc/dce120/
Ddce120_resource.c293 static const struct dce_stream_encoder_mask se_mask = { variable
768 &se_shift, &se_mask); in dce120_stream_encoder_create()
/linux-5.19.10/drivers/gpu/drm/amd/display/dc/dcn201/
Ddcn201_resource.c360 static const struct dcn10_stream_encoder_mask se_mask = { variable
862 &se_shift, &se_mask); in dcn201_stream_encoder_create()
/linux-5.19.10/drivers/gpu/drm/amd/display/dc/dce112/
Ddce112_resource.c304 static const struct dce_stream_encoder_mask se_mask = { variable
515 &se_shift, &se_mask); in dce112_stream_encoder_create()
/linux-5.19.10/drivers/gpu/drm/amd/display/dc/dce60/
Ddce60_resource.c264 static const struct dce_stream_encoder_mask se_mask = { variable
603 &se_shift, &se_mask); in dce60_stream_encoder_create()
/linux-5.19.10/drivers/gpu/drm/amd/display/dc/dce80/
Ddce80_resource.c268 static const struct dce_stream_encoder_mask se_mask = { variable
608 &se_shift, &se_mask); in dce80_stream_encoder_create()
/linux-5.19.10/drivers/ntb/hw/idt/
Dntb_hw_idt.c637 u32 part_mask, port_mask, se_mask; in idt_init_link() local
669 se_mask = ~(IDT_SEMSK_LINKUP | IDT_SEMSK_LINKDN | IDT_SEMSK_GSIGNAL); in idt_init_link()
670 idt_sw_write(ndev, IDT_SW_SEMSK, se_mask); in idt_init_link()

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