Searched refs:sclk_mask (Results 1 – 5 of 5) sorted by relevance
| /linux-5.19.10/drivers/gpu/drm/amd/pm/swsmu/smu12/ |
| D | renoir_ppt.c | 243 uint32_t *sclk_mask, in renoir_get_profiling_clk_mask() argument
249 if (sclk_mask) in renoir_get_profiling_clk_mask()
250 *sclk_mask = 0; in renoir_get_profiling_clk_mask()
256 if(sclk_mask) in renoir_get_profiling_clk_mask()
258 *sclk_mask = 3 - 1; in renoir_get_profiling_clk_mask()
925 uint32_t sclk_mask, mclk_mask, soc_mask; in renoir_set_performance_level() local
1006 &sclk_mask, in renoir_set_performance_level()
1011 renoir_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask); in renoir_set_performance_level()
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| /linux-5.19.10/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| D | vega12_hwmgr.c | 1697 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) in vega12_get_profiling_clk_mask() argument
1704 *sclk_mask = 0; in vega12_get_profiling_clk_mask()
1711 *sclk_mask = VEGA12_UMD_PSTATE_GFXCLK_LEVEL; in vega12_get_profiling_clk_mask()
1717 *sclk_mask = 0; in vega12_get_profiling_clk_mask()
1721 *sclk_mask = gfx_dpm_table->count - 1; in vega12_get_profiling_clk_mask()
1751 uint32_t sclk_mask = 0; in vega12_dpm_force_dpm_level() local
1769 ret = vega12_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega12_dpm_force_dpm_level()
1772 vega12_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask); in vega12_dpm_force_dpm_level()
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| D | smu7_hwmgr.c | 3116 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *pcie_mask) in smu7_get_profiling_clk() argument
3147 *sclk_mask = count; in smu7_get_profiling_clk()
3152 *sclk_mask = 0; in smu7_get_profiling_clk()
3157 *sclk_mask = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1; in smu7_get_profiling_clk()
3165 *sclk_mask = count; in smu7_get_profiling_clk()
3170 *sclk_mask = 0; in smu7_get_profiling_clk()
3175 *sclk_mask = table_info->vdd_dep_on_sclk->count - 1; in smu7_get_profiling_clk()
3194 uint32_t sclk_mask = 0; in smu7_force_dpm_level() local
3199 smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask); in smu7_force_dpm_level()
3215 ret = smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask); in smu7_force_dpm_level()
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| D | vega20_hwmgr.c | 2522 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) in vega20_get_profiling_clk_mask() argument
2529 *sclk_mask = 0; in vega20_get_profiling_clk_mask()
2536 *sclk_mask = VEGA20_UMD_PSTATE_GFXCLK_LEVEL; in vega20_get_profiling_clk_mask()
2542 *sclk_mask = 0; in vega20_get_profiling_clk_mask()
2546 *sclk_mask = gfx_dpm_table->count - 1; in vega20_get_profiling_clk_mask()
2722 uint32_t sclk_mask, mclk_mask, soc_mask; in vega20_dpm_force_dpm_level() local
2741 ret = vega20_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega20_dpm_force_dpm_level()
2744 vega20_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask); in vega20_dpm_force_dpm_level()
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| D | vega10_hwmgr.c | 4161 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) in vega10_get_profiling_clk_mask() argument
4169 *sclk_mask = VEGA10_UMD_PSTATE_GFXCLK_LEVEL; in vega10_get_profiling_clk_mask()
4177 *sclk_mask = 0; in vega10_get_profiling_clk_mask()
4185 *sclk_mask = 4; in vega10_get_profiling_clk_mask()
4187 *sclk_mask = table_info->vdd_dep_on_sclk->count - 1; in vega10_get_profiling_clk_mask()
4280 uint32_t sclk_mask = 0; in vega10_dpm_force_dpm_level() local
4285 vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega10_dpm_force_dpm_level()
4301 ret = vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega10_dpm_force_dpm_level()
4304 vega10_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask); in vega10_dpm_force_dpm_level()
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