1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell RVU Admin Function driver
3 *
4 * Copyright (C) 2018 Marvell.
5 *
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/module.h>
10 #include <linux/pci.h>
11
12 #include "rvu_struct.h"
13 #include "rvu_reg.h"
14 #include "rvu.h"
15 #include "npc.h"
16 #include "cgx.h"
17 #include "npc_profile.h"
18
19 #define RSVD_MCAM_ENTRIES_PER_PF 3 /* Broadcast, Promisc and AllMulticast */
20 #define RSVD_MCAM_ENTRIES_PER_NIXLF 1 /* Ucast for LFs */
21
22 #define NPC_PARSE_RESULT_DMAC_OFFSET 8
23 #define NPC_HW_TSTAMP_OFFSET 8ULL
24 #define NPC_KEX_CHAN_MASK 0xFFFULL
25 #define NPC_KEX_PF_FUNC_MASK 0xFFFFULL
26
27 #define ALIGN_8B_CEIL(__a) (((__a) + 7) & (-8))
28
29 static const char def_pfl_name[] = "default";
30
31 static void npc_mcam_free_all_entries(struct rvu *rvu, struct npc_mcam *mcam,
32 int blkaddr, u16 pcifunc);
33 static void npc_mcam_free_all_counters(struct rvu *rvu, struct npc_mcam *mcam,
34 u16 pcifunc);
35
is_npc_intf_tx(u8 intf)36 bool is_npc_intf_tx(u8 intf)
37 {
38 return !!(intf & 0x1);
39 }
40
is_npc_intf_rx(u8 intf)41 bool is_npc_intf_rx(u8 intf)
42 {
43 return !(intf & 0x1);
44 }
45
is_npc_interface_valid(struct rvu * rvu,u8 intf)46 bool is_npc_interface_valid(struct rvu *rvu, u8 intf)
47 {
48 struct rvu_hwinfo *hw = rvu->hw;
49
50 return intf < hw->npc_intfs;
51 }
52
rvu_npc_get_tx_nibble_cfg(struct rvu * rvu,u64 nibble_ena)53 int rvu_npc_get_tx_nibble_cfg(struct rvu *rvu, u64 nibble_ena)
54 {
55 /* Due to a HW issue in these silicon versions, parse nibble enable
56 * configuration has to be identical for both Rx and Tx interfaces.
57 */
58 if (is_rvu_96xx_B0(rvu))
59 return nibble_ena;
60 return 0;
61 }
62
npc_mcam_verify_pf_func(struct rvu * rvu,struct mcam_entry * entry_data,u8 intf,u16 pcifunc)63 static int npc_mcam_verify_pf_func(struct rvu *rvu,
64 struct mcam_entry *entry_data, u8 intf,
65 u16 pcifunc)
66 {
67 u16 pf_func, pf_func_mask;
68
69 if (is_npc_intf_rx(intf))
70 return 0;
71
72 pf_func_mask = (entry_data->kw_mask[0] >> 32) &
73 NPC_KEX_PF_FUNC_MASK;
74 pf_func = (entry_data->kw[0] >> 32) & NPC_KEX_PF_FUNC_MASK;
75
76 pf_func = be16_to_cpu((__force __be16)pf_func);
77 if (pf_func_mask != NPC_KEX_PF_FUNC_MASK ||
78 ((pf_func & ~RVU_PFVF_FUNC_MASK) !=
79 (pcifunc & ~RVU_PFVF_FUNC_MASK)))
80 return -EINVAL;
81
82 return 0;
83 }
84
rvu_npc_set_pkind(struct rvu * rvu,int pkind,struct rvu_pfvf * pfvf)85 void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf)
86 {
87 int blkaddr;
88 u64 val = 0;
89
90 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
91 if (blkaddr < 0)
92 return;
93
94 /* Config CPI base for the PKIND */
95 val = pkind | 1ULL << 62;
96 rvu_write64(rvu, blkaddr, NPC_AF_PKINDX_CPI_DEFX(pkind, 0), val);
97 }
98
rvu_npc_get_pkind(struct rvu * rvu,u16 pf)99 int rvu_npc_get_pkind(struct rvu *rvu, u16 pf)
100 {
101 struct npc_pkind *pkind = &rvu->hw->pkind;
102 u32 map;
103 int i;
104
105 for (i = 0; i < pkind->rsrc.max; i++) {
106 map = pkind->pfchan_map[i];
107 if (((map >> 16) & 0x3F) == pf)
108 return i;
109 }
110 return -1;
111 }
112
113 #define NPC_AF_ACTION0_PTR_ADVANCE GENMASK_ULL(27, 20)
114
npc_config_ts_kpuaction(struct rvu * rvu,int pf,u16 pcifunc,bool enable)115 int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool enable)
116 {
117 int pkind, blkaddr;
118 u64 val;
119
120 pkind = rvu_npc_get_pkind(rvu, pf);
121 if (pkind < 0) {
122 dev_err(rvu->dev, "%s: pkind not mapped\n", __func__);
123 return -EINVAL;
124 }
125
126 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, pcifunc);
127 if (blkaddr < 0) {
128 dev_err(rvu->dev, "%s: NPC block not implemented\n", __func__);
129 return -EINVAL;
130 }
131
132 val = rvu_read64(rvu, blkaddr, NPC_AF_PKINDX_ACTION0(pkind));
133 val &= ~NPC_AF_ACTION0_PTR_ADVANCE;
134 /* If timestamp is enabled then configure NPC to shift 8 bytes */
135 if (enable)
136 val |= FIELD_PREP(NPC_AF_ACTION0_PTR_ADVANCE,
137 NPC_HW_TSTAMP_OFFSET);
138 rvu_write64(rvu, blkaddr, NPC_AF_PKINDX_ACTION0(pkind), val);
139
140 return 0;
141 }
142
npc_get_ucast_mcam_index(struct npc_mcam * mcam,u16 pcifunc,int nixlf)143 static int npc_get_ucast_mcam_index(struct npc_mcam *mcam, u16 pcifunc,
144 int nixlf)
145 {
146 struct rvu_hwinfo *hw = container_of(mcam, struct rvu_hwinfo, mcam);
147 struct rvu *rvu = hw->rvu;
148 int blkaddr = 0, max = 0;
149 struct rvu_block *block;
150 struct rvu_pfvf *pfvf;
151
152 pfvf = rvu_get_pfvf(rvu, pcifunc);
153 /* Given a PF/VF and NIX LF number calculate the unicast mcam
154 * entry index based on the NIX block assigned to the PF/VF.
155 */
156 blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr);
157 while (blkaddr) {
158 if (pfvf->nix_blkaddr == blkaddr)
159 break;
160 block = &rvu->hw->block[blkaddr];
161 max += block->lf.max;
162 blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr);
163 }
164
165 return mcam->nixlf_offset + (max + nixlf) * RSVD_MCAM_ENTRIES_PER_NIXLF;
166 }
167
npc_get_nixlf_mcam_index(struct npc_mcam * mcam,u16 pcifunc,int nixlf,int type)168 int npc_get_nixlf_mcam_index(struct npc_mcam *mcam,
169 u16 pcifunc, int nixlf, int type)
170 {
171 int pf = rvu_get_pf(pcifunc);
172 int index;
173
174 /* Check if this is for a PF */
175 if (pf && !(pcifunc & RVU_PFVF_FUNC_MASK)) {
176 /* Reserved entries exclude PF0 */
177 pf--;
178 index = mcam->pf_offset + (pf * RSVD_MCAM_ENTRIES_PER_PF);
179 /* Broadcast address matching entry should be first so
180 * that the packet can be replicated to all VFs.
181 */
182 if (type == NIXLF_BCAST_ENTRY)
183 return index;
184 else if (type == NIXLF_ALLMULTI_ENTRY)
185 return index + 1;
186 else if (type == NIXLF_PROMISC_ENTRY)
187 return index + 2;
188 }
189
190 return npc_get_ucast_mcam_index(mcam, pcifunc, nixlf);
191 }
192
npc_get_bank(struct npc_mcam * mcam,int index)193 int npc_get_bank(struct npc_mcam *mcam, int index)
194 {
195 int bank = index / mcam->banksize;
196
197 /* 0,1 & 2,3 banks are combined for this keysize */
198 if (mcam->keysize == NPC_MCAM_KEY_X2)
199 return bank ? 2 : 0;
200
201 return bank;
202 }
203
is_mcam_entry_enabled(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,int index)204 bool is_mcam_entry_enabled(struct rvu *rvu, struct npc_mcam *mcam,
205 int blkaddr, int index)
206 {
207 int bank = npc_get_bank(mcam, index);
208 u64 cfg;
209
210 index &= (mcam->banksize - 1);
211 cfg = rvu_read64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_CFG(index, bank));
212 return (cfg & 1);
213 }
214
npc_enable_mcam_entry(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,int index,bool enable)215 void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
216 int blkaddr, int index, bool enable)
217 {
218 int bank = npc_get_bank(mcam, index);
219 int actbank = bank;
220
221 index &= (mcam->banksize - 1);
222 for (; bank < (actbank + mcam->banks_per_entry); bank++) {
223 rvu_write64(rvu, blkaddr,
224 NPC_AF_MCAMEX_BANKX_CFG(index, bank),
225 enable ? 1 : 0);
226 }
227 }
228
npc_clear_mcam_entry(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,int index)229 static void npc_clear_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
230 int blkaddr, int index)
231 {
232 int bank = npc_get_bank(mcam, index);
233 int actbank = bank;
234
235 index &= (mcam->banksize - 1);
236 for (; bank < (actbank + mcam->banks_per_entry); bank++) {
237 rvu_write64(rvu, blkaddr,
238 NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 1), 0);
239 rvu_write64(rvu, blkaddr,
240 NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 0), 0);
241
242 rvu_write64(rvu, blkaddr,
243 NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 1), 0);
244 rvu_write64(rvu, blkaddr,
245 NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 0), 0);
246
247 rvu_write64(rvu, blkaddr,
248 NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 1), 0);
249 rvu_write64(rvu, blkaddr,
250 NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 0), 0);
251 }
252 }
253
npc_get_keyword(struct mcam_entry * entry,int idx,u64 * cam0,u64 * cam1)254 static void npc_get_keyword(struct mcam_entry *entry, int idx,
255 u64 *cam0, u64 *cam1)
256 {
257 u64 kw_mask = 0x00;
258
259 #define CAM_MASK(n) (BIT_ULL(n) - 1)
260
261 /* 0, 2, 4, 6 indices refer to BANKX_CAMX_W0 and
262 * 1, 3, 5, 7 indices refer to BANKX_CAMX_W1.
263 *
264 * Also, only 48 bits of BANKX_CAMX_W1 are valid.
265 */
266 switch (idx) {
267 case 0:
268 /* BANK(X)_CAM_W0<63:0> = MCAM_KEY[KW0]<63:0> */
269 *cam1 = entry->kw[0];
270 kw_mask = entry->kw_mask[0];
271 break;
272 case 1:
273 /* BANK(X)_CAM_W1<47:0> = MCAM_KEY[KW1]<47:0> */
274 *cam1 = entry->kw[1] & CAM_MASK(48);
275 kw_mask = entry->kw_mask[1] & CAM_MASK(48);
276 break;
277 case 2:
278 /* BANK(X + 1)_CAM_W0<15:0> = MCAM_KEY[KW1]<63:48>
279 * BANK(X + 1)_CAM_W0<63:16> = MCAM_KEY[KW2]<47:0>
280 */
281 *cam1 = (entry->kw[1] >> 48) & CAM_MASK(16);
282 *cam1 |= ((entry->kw[2] & CAM_MASK(48)) << 16);
283 kw_mask = (entry->kw_mask[1] >> 48) & CAM_MASK(16);
284 kw_mask |= ((entry->kw_mask[2] & CAM_MASK(48)) << 16);
285 break;
286 case 3:
287 /* BANK(X + 1)_CAM_W1<15:0> = MCAM_KEY[KW2]<63:48>
288 * BANK(X + 1)_CAM_W1<47:16> = MCAM_KEY[KW3]<31:0>
289 */
290 *cam1 = (entry->kw[2] >> 48) & CAM_MASK(16);
291 *cam1 |= ((entry->kw[3] & CAM_MASK(32)) << 16);
292 kw_mask = (entry->kw_mask[2] >> 48) & CAM_MASK(16);
293 kw_mask |= ((entry->kw_mask[3] & CAM_MASK(32)) << 16);
294 break;
295 case 4:
296 /* BANK(X + 2)_CAM_W0<31:0> = MCAM_KEY[KW3]<63:32>
297 * BANK(X + 2)_CAM_W0<63:32> = MCAM_KEY[KW4]<31:0>
298 */
299 *cam1 = (entry->kw[3] >> 32) & CAM_MASK(32);
300 *cam1 |= ((entry->kw[4] & CAM_MASK(32)) << 32);
301 kw_mask = (entry->kw_mask[3] >> 32) & CAM_MASK(32);
302 kw_mask |= ((entry->kw_mask[4] & CAM_MASK(32)) << 32);
303 break;
304 case 5:
305 /* BANK(X + 2)_CAM_W1<31:0> = MCAM_KEY[KW4]<63:32>
306 * BANK(X + 2)_CAM_W1<47:32> = MCAM_KEY[KW5]<15:0>
307 */
308 *cam1 = (entry->kw[4] >> 32) & CAM_MASK(32);
309 *cam1 |= ((entry->kw[5] & CAM_MASK(16)) << 32);
310 kw_mask = (entry->kw_mask[4] >> 32) & CAM_MASK(32);
311 kw_mask |= ((entry->kw_mask[5] & CAM_MASK(16)) << 32);
312 break;
313 case 6:
314 /* BANK(X + 3)_CAM_W0<47:0> = MCAM_KEY[KW5]<63:16>
315 * BANK(X + 3)_CAM_W0<63:48> = MCAM_KEY[KW6]<15:0>
316 */
317 *cam1 = (entry->kw[5] >> 16) & CAM_MASK(48);
318 *cam1 |= ((entry->kw[6] & CAM_MASK(16)) << 48);
319 kw_mask = (entry->kw_mask[5] >> 16) & CAM_MASK(48);
320 kw_mask |= ((entry->kw_mask[6] & CAM_MASK(16)) << 48);
321 break;
322 case 7:
323 /* BANK(X + 3)_CAM_W1<47:0> = MCAM_KEY[KW6]<63:16> */
324 *cam1 = (entry->kw[6] >> 16) & CAM_MASK(48);
325 kw_mask = (entry->kw_mask[6] >> 16) & CAM_MASK(48);
326 break;
327 }
328
329 *cam1 &= kw_mask;
330 *cam0 = ~*cam1 & kw_mask;
331 }
332
npc_fill_entryword(struct mcam_entry * entry,int idx,u64 cam0,u64 cam1)333 static void npc_fill_entryword(struct mcam_entry *entry, int idx,
334 u64 cam0, u64 cam1)
335 {
336 /* Similar to npc_get_keyword, but fills mcam_entry structure from
337 * CAM registers.
338 */
339 switch (idx) {
340 case 0:
341 entry->kw[0] = cam1;
342 entry->kw_mask[0] = cam1 ^ cam0;
343 break;
344 case 1:
345 entry->kw[1] = cam1;
346 entry->kw_mask[1] = cam1 ^ cam0;
347 break;
348 case 2:
349 entry->kw[1] |= (cam1 & CAM_MASK(16)) << 48;
350 entry->kw[2] = (cam1 >> 16) & CAM_MASK(48);
351 entry->kw_mask[1] |= ((cam1 ^ cam0) & CAM_MASK(16)) << 48;
352 entry->kw_mask[2] = ((cam1 ^ cam0) >> 16) & CAM_MASK(48);
353 break;
354 case 3:
355 entry->kw[2] |= (cam1 & CAM_MASK(16)) << 48;
356 entry->kw[3] = (cam1 >> 16) & CAM_MASK(32);
357 entry->kw_mask[2] |= ((cam1 ^ cam0) & CAM_MASK(16)) << 48;
358 entry->kw_mask[3] = ((cam1 ^ cam0) >> 16) & CAM_MASK(32);
359 break;
360 case 4:
361 entry->kw[3] |= (cam1 & CAM_MASK(32)) << 32;
362 entry->kw[4] = (cam1 >> 32) & CAM_MASK(32);
363 entry->kw_mask[3] |= ((cam1 ^ cam0) & CAM_MASK(32)) << 32;
364 entry->kw_mask[4] = ((cam1 ^ cam0) >> 32) & CAM_MASK(32);
365 break;
366 case 5:
367 entry->kw[4] |= (cam1 & CAM_MASK(32)) << 32;
368 entry->kw[5] = (cam1 >> 32) & CAM_MASK(16);
369 entry->kw_mask[4] |= ((cam1 ^ cam0) & CAM_MASK(32)) << 32;
370 entry->kw_mask[5] = ((cam1 ^ cam0) >> 32) & CAM_MASK(16);
371 break;
372 case 6:
373 entry->kw[5] |= (cam1 & CAM_MASK(48)) << 16;
374 entry->kw[6] = (cam1 >> 48) & CAM_MASK(16);
375 entry->kw_mask[5] |= ((cam1 ^ cam0) & CAM_MASK(48)) << 16;
376 entry->kw_mask[6] = ((cam1 ^ cam0) >> 48) & CAM_MASK(16);
377 break;
378 case 7:
379 entry->kw[6] |= (cam1 & CAM_MASK(48)) << 16;
380 entry->kw_mask[6] |= ((cam1 ^ cam0) & CAM_MASK(48)) << 16;
381 break;
382 }
383 }
384
npc_get_default_entry_action(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,u16 pf_func)385 static u64 npc_get_default_entry_action(struct rvu *rvu, struct npc_mcam *mcam,
386 int blkaddr, u16 pf_func)
387 {
388 int bank, nixlf, index;
389
390 /* get ucast entry rule entry index */
391 nix_get_nixlf(rvu, pf_func, &nixlf, NULL);
392 index = npc_get_nixlf_mcam_index(mcam, pf_func, nixlf,
393 NIXLF_UCAST_ENTRY);
394 bank = npc_get_bank(mcam, index);
395 index &= (mcam->banksize - 1);
396
397 return rvu_read64(rvu, blkaddr,
398 NPC_AF_MCAMEX_BANKX_ACTION(index, bank));
399 }
400
npc_fixup_vf_rule(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,int index,struct mcam_entry * entry,bool * enable)401 static void npc_fixup_vf_rule(struct rvu *rvu, struct npc_mcam *mcam,
402 int blkaddr, int index, struct mcam_entry *entry,
403 bool *enable)
404 {
405 struct rvu_npc_mcam_rule *rule;
406 u16 owner, target_func;
407 struct rvu_pfvf *pfvf;
408 u64 rx_action;
409
410 owner = mcam->entry2pfvf_map[index];
411 target_func = (entry->action >> 4) & 0xffff;
412 /* do nothing when target is LBK/PF or owner is not PF */
413 if (is_pffunc_af(owner) || is_afvf(target_func) ||
414 (owner & RVU_PFVF_FUNC_MASK) ||
415 !(target_func & RVU_PFVF_FUNC_MASK))
416 return;
417
418 /* save entry2target_pffunc */
419 pfvf = rvu_get_pfvf(rvu, target_func);
420 mcam->entry2target_pffunc[index] = target_func;
421
422 /* don't enable rule when nixlf not attached or initialized */
423 if (!(is_nixlf_attached(rvu, target_func) &&
424 test_bit(NIXLF_INITIALIZED, &pfvf->flags)))
425 *enable = false;
426
427 /* fix up not needed for the rules added by user(ntuple filters) */
428 list_for_each_entry(rule, &mcam->mcam_rules, list) {
429 if (rule->entry == index)
430 return;
431 }
432
433 /* copy VF default entry action to the VF mcam entry */
434 rx_action = npc_get_default_entry_action(rvu, mcam, blkaddr,
435 target_func);
436 if (rx_action)
437 entry->action = rx_action;
438 }
439
npc_config_mcam_entry(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,int index,u8 intf,struct mcam_entry * entry,bool enable)440 static void npc_config_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
441 int blkaddr, int index, u8 intf,
442 struct mcam_entry *entry, bool enable)
443 {
444 int bank = npc_get_bank(mcam, index);
445 int kw = 0, actbank, actindex;
446 u8 tx_intf_mask = ~intf & 0x3;
447 u8 tx_intf = intf;
448 u64 cam0, cam1;
449
450 actbank = bank; /* Save bank id, to set action later on */
451 actindex = index;
452 index &= (mcam->banksize - 1);
453
454 /* Disable before mcam entry update */
455 npc_enable_mcam_entry(rvu, mcam, blkaddr, actindex, false);
456
457 /* Clear mcam entry to avoid writes being suppressed by NPC */
458 npc_clear_mcam_entry(rvu, mcam, blkaddr, actindex);
459
460 /* CAM1 takes the comparison value and
461 * CAM0 specifies match for a bit in key being '0' or '1' or 'dontcare'.
462 * CAM1<n> = 0 & CAM0<n> = 1 => match if key<n> = 0
463 * CAM1<n> = 1 & CAM0<n> = 0 => match if key<n> = 1
464 * CAM1<n> = 0 & CAM0<n> = 0 => always match i.e dontcare.
465 */
466 for (; bank < (actbank + mcam->banks_per_entry); bank++, kw = kw + 2) {
467 /* Interface should be set in all banks */
468 if (is_npc_intf_tx(intf)) {
469 /* Last bit must be set and rest don't care
470 * for TX interfaces
471 */
472 tx_intf_mask = 0x1;
473 tx_intf = intf & tx_intf_mask;
474 tx_intf_mask = ~tx_intf & tx_intf_mask;
475 }
476
477 rvu_write64(rvu, blkaddr,
478 NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 1),
479 tx_intf);
480 rvu_write64(rvu, blkaddr,
481 NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 0),
482 tx_intf_mask);
483
484 /* Set the match key */
485 npc_get_keyword(entry, kw, &cam0, &cam1);
486 rvu_write64(rvu, blkaddr,
487 NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 1), cam1);
488 rvu_write64(rvu, blkaddr,
489 NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 0), cam0);
490
491 npc_get_keyword(entry, kw + 1, &cam0, &cam1);
492 rvu_write64(rvu, blkaddr,
493 NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 1), cam1);
494 rvu_write64(rvu, blkaddr,
495 NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 0), cam0);
496 }
497
498 /* PF installing VF rule */
499 if (is_npc_intf_rx(intf) && actindex < mcam->bmap_entries)
500 npc_fixup_vf_rule(rvu, mcam, blkaddr, actindex, entry, &enable);
501
502 /* Set 'action' */
503 rvu_write64(rvu, blkaddr,
504 NPC_AF_MCAMEX_BANKX_ACTION(index, actbank), entry->action);
505
506 /* Set TAG 'action' */
507 rvu_write64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_TAG_ACT(index, actbank),
508 entry->vtag_action);
509
510 /* Enable the entry */
511 if (enable)
512 npc_enable_mcam_entry(rvu, mcam, blkaddr, actindex, true);
513 }
514
npc_read_mcam_entry(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,u16 src,struct mcam_entry * entry,u8 * intf,u8 * ena)515 void npc_read_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
516 int blkaddr, u16 src,
517 struct mcam_entry *entry, u8 *intf, u8 *ena)
518 {
519 int sbank = npc_get_bank(mcam, src);
520 int bank, kw = 0;
521 u64 cam0, cam1;
522
523 src &= (mcam->banksize - 1);
524 bank = sbank;
525
526 for (; bank < (sbank + mcam->banks_per_entry); bank++, kw = kw + 2) {
527 cam1 = rvu_read64(rvu, blkaddr,
528 NPC_AF_MCAMEX_BANKX_CAMX_W0(src, bank, 1));
529 cam0 = rvu_read64(rvu, blkaddr,
530 NPC_AF_MCAMEX_BANKX_CAMX_W0(src, bank, 0));
531 npc_fill_entryword(entry, kw, cam0, cam1);
532
533 cam1 = rvu_read64(rvu, blkaddr,
534 NPC_AF_MCAMEX_BANKX_CAMX_W1(src, bank, 1));
535 cam0 = rvu_read64(rvu, blkaddr,
536 NPC_AF_MCAMEX_BANKX_CAMX_W1(src, bank, 0));
537 npc_fill_entryword(entry, kw + 1, cam0, cam1);
538 }
539
540 entry->action = rvu_read64(rvu, blkaddr,
541 NPC_AF_MCAMEX_BANKX_ACTION(src, sbank));
542 entry->vtag_action =
543 rvu_read64(rvu, blkaddr,
544 NPC_AF_MCAMEX_BANKX_TAG_ACT(src, sbank));
545 *intf = rvu_read64(rvu, blkaddr,
546 NPC_AF_MCAMEX_BANKX_CAMX_INTF(src, sbank, 1)) & 3;
547 *ena = rvu_read64(rvu, blkaddr,
548 NPC_AF_MCAMEX_BANKX_CFG(src, sbank)) & 1;
549 }
550
npc_copy_mcam_entry(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,u16 src,u16 dest)551 static void npc_copy_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
552 int blkaddr, u16 src, u16 dest)
553 {
554 int dbank = npc_get_bank(mcam, dest);
555 int sbank = npc_get_bank(mcam, src);
556 u64 cfg, sreg, dreg;
557 int bank, i;
558
559 src &= (mcam->banksize - 1);
560 dest &= (mcam->banksize - 1);
561
562 /* Copy INTF's, W0's, W1's CAM0 and CAM1 configuration */
563 for (bank = 0; bank < mcam->banks_per_entry; bank++) {
564 sreg = NPC_AF_MCAMEX_BANKX_CAMX_INTF(src, sbank + bank, 0);
565 dreg = NPC_AF_MCAMEX_BANKX_CAMX_INTF(dest, dbank + bank, 0);
566 for (i = 0; i < 6; i++) {
567 cfg = rvu_read64(rvu, blkaddr, sreg + (i * 8));
568 rvu_write64(rvu, blkaddr, dreg + (i * 8), cfg);
569 }
570 }
571
572 /* Copy action */
573 cfg = rvu_read64(rvu, blkaddr,
574 NPC_AF_MCAMEX_BANKX_ACTION(src, sbank));
575 rvu_write64(rvu, blkaddr,
576 NPC_AF_MCAMEX_BANKX_ACTION(dest, dbank), cfg);
577
578 /* Copy TAG action */
579 cfg = rvu_read64(rvu, blkaddr,
580 NPC_AF_MCAMEX_BANKX_TAG_ACT(src, sbank));
581 rvu_write64(rvu, blkaddr,
582 NPC_AF_MCAMEX_BANKX_TAG_ACT(dest, dbank), cfg);
583
584 /* Enable or disable */
585 cfg = rvu_read64(rvu, blkaddr,
586 NPC_AF_MCAMEX_BANKX_CFG(src, sbank));
587 rvu_write64(rvu, blkaddr,
588 NPC_AF_MCAMEX_BANKX_CFG(dest, dbank), cfg);
589 }
590
npc_get_mcam_action(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,int index)591 static u64 npc_get_mcam_action(struct rvu *rvu, struct npc_mcam *mcam,
592 int blkaddr, int index)
593 {
594 int bank = npc_get_bank(mcam, index);
595
596 index &= (mcam->banksize - 1);
597 return rvu_read64(rvu, blkaddr,
598 NPC_AF_MCAMEX_BANKX_ACTION(index, bank));
599 }
600
rvu_npc_install_ucast_entry(struct rvu * rvu,u16 pcifunc,int nixlf,u64 chan,u8 * mac_addr)601 void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc,
602 int nixlf, u64 chan, u8 *mac_addr)
603 {
604 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
605 struct npc_install_flow_req req = { 0 };
606 struct npc_install_flow_rsp rsp = { 0 };
607 struct npc_mcam *mcam = &rvu->hw->mcam;
608 struct nix_rx_action action = { 0 };
609 int blkaddr, index;
610
611 /* AF's and SDP VFs work in promiscuous mode */
612 if (is_afvf(pcifunc) || is_sdp_vf(pcifunc))
613 return;
614
615 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
616 if (blkaddr < 0)
617 return;
618
619 index = npc_get_nixlf_mcam_index(mcam, pcifunc,
620 nixlf, NIXLF_UCAST_ENTRY);
621
622 /* Don't change the action if entry is already enabled
623 * Otherwise RSS action may get overwritten.
624 */
625 if (is_mcam_entry_enabled(rvu, mcam, blkaddr, index)) {
626 *(u64 *)&action = npc_get_mcam_action(rvu, mcam,
627 blkaddr, index);
628 } else {
629 action.op = NIX_RX_ACTIONOP_UCAST;
630 action.pf_func = pcifunc;
631 }
632
633 req.default_rule = 1;
634 ether_addr_copy(req.packet.dmac, mac_addr);
635 eth_broadcast_addr((u8 *)&req.mask.dmac);
636 req.features = BIT_ULL(NPC_DMAC);
637 req.channel = chan;
638 req.chan_mask = 0xFFFU;
639 req.intf = pfvf->nix_rx_intf;
640 req.op = action.op;
641 req.hdr.pcifunc = 0; /* AF is requester */
642 req.vf = action.pf_func;
643 req.index = action.index;
644 req.match_id = action.match_id;
645 req.flow_key_alg = action.flow_key_alg;
646
647 rvu_mbox_handler_npc_install_flow(rvu, &req, &rsp);
648 }
649
rvu_npc_install_promisc_entry(struct rvu * rvu,u16 pcifunc,int nixlf,u64 chan,u8 chan_cnt)650 void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc,
651 int nixlf, u64 chan, u8 chan_cnt)
652 {
653 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
654 struct npc_install_flow_req req = { 0 };
655 struct npc_install_flow_rsp rsp = { 0 };
656 struct npc_mcam *mcam = &rvu->hw->mcam;
657 struct rvu_hwinfo *hw = rvu->hw;
658 int blkaddr, ucast_idx, index;
659 struct nix_rx_action action = { 0 };
660 u64 relaxed_mask;
661
662 if (!hw->cap.nix_rx_multicast && is_cgx_vf(rvu, pcifunc))
663 return;
664
665 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
666 if (blkaddr < 0)
667 return;
668
669 index = npc_get_nixlf_mcam_index(mcam, pcifunc,
670 nixlf, NIXLF_PROMISC_ENTRY);
671
672 if (is_cgx_vf(rvu, pcifunc))
673 index = npc_get_nixlf_mcam_index(mcam,
674 pcifunc & ~RVU_PFVF_FUNC_MASK,
675 nixlf, NIXLF_PROMISC_ENTRY);
676
677 /* If the corresponding PF's ucast action is RSS,
678 * use the same action for promisc also
679 */
680 ucast_idx = npc_get_nixlf_mcam_index(mcam, pcifunc,
681 nixlf, NIXLF_UCAST_ENTRY);
682 if (is_mcam_entry_enabled(rvu, mcam, blkaddr, ucast_idx))
683 *(u64 *)&action = npc_get_mcam_action(rvu, mcam,
684 blkaddr, ucast_idx);
685
686 if (action.op != NIX_RX_ACTIONOP_RSS) {
687 *(u64 *)&action = 0;
688 action.op = NIX_RX_ACTIONOP_UCAST;
689 }
690
691 /* RX_ACTION set to MCAST for CGX PF's */
692 if (hw->cap.nix_rx_multicast && pfvf->use_mce_list &&
693 is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc))) {
694 *(u64 *)&action = 0;
695 action.op = NIX_RX_ACTIONOP_MCAST;
696 pfvf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK);
697 action.index = pfvf->promisc_mce_idx;
698 }
699
700 /* For cn10k the upper two bits of the channel number are
701 * cpt channel number. with masking out these bits in the
702 * mcam entry, same entry used for NIX will allow packets
703 * received from cpt for parsing.
704 */
705 if (!is_rvu_otx2(rvu)) {
706 req.chan_mask = NIX_CHAN_CPT_X2P_MASK;
707 } else {
708 req.chan_mask = 0xFFFU;
709 }
710
711 if (chan_cnt > 1) {
712 if (!is_power_of_2(chan_cnt)) {
713 dev_err(rvu->dev,
714 "%s: channel count more than 1, must be power of 2\n", __func__);
715 return;
716 }
717 relaxed_mask = GENMASK_ULL(BITS_PER_LONG_LONG - 1,
718 ilog2(chan_cnt));
719 req.chan_mask &= relaxed_mask;
720 }
721
722 req.channel = chan;
723 req.intf = pfvf->nix_rx_intf;
724 req.entry = index;
725 req.op = action.op;
726 req.hdr.pcifunc = 0; /* AF is requester */
727 req.vf = pcifunc;
728 req.index = action.index;
729 req.match_id = action.match_id;
730 req.flow_key_alg = action.flow_key_alg;
731
732 rvu_mbox_handler_npc_install_flow(rvu, &req, &rsp);
733 }
734
rvu_npc_enable_promisc_entry(struct rvu * rvu,u16 pcifunc,int nixlf,bool enable)735 void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc,
736 int nixlf, bool enable)
737 {
738 struct npc_mcam *mcam = &rvu->hw->mcam;
739 int blkaddr, index;
740
741 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
742 if (blkaddr < 0)
743 return;
744
745 /* Get 'pcifunc' of PF device */
746 pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK;
747
748 index = npc_get_nixlf_mcam_index(mcam, pcifunc,
749 nixlf, NIXLF_PROMISC_ENTRY);
750 npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable);
751 }
752
rvu_npc_install_bcast_match_entry(struct rvu * rvu,u16 pcifunc,int nixlf,u64 chan)753 void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc,
754 int nixlf, u64 chan)
755 {
756 struct rvu_pfvf *pfvf;
757 struct npc_install_flow_req req = { 0 };
758 struct npc_install_flow_rsp rsp = { 0 };
759 struct npc_mcam *mcam = &rvu->hw->mcam;
760 struct rvu_hwinfo *hw = rvu->hw;
761 int blkaddr, index;
762
763 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
764 if (blkaddr < 0)
765 return;
766
767 /* Skip LBK VFs */
768 if (is_afvf(pcifunc))
769 return;
770
771 /* If pkt replication is not supported,
772 * then only PF is allowed to add a bcast match entry.
773 */
774 if (!hw->cap.nix_rx_multicast && is_vf(pcifunc))
775 return;
776
777 /* Get 'pcifunc' of PF device */
778 pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK;
779 pfvf = rvu_get_pfvf(rvu, pcifunc);
780 index = npc_get_nixlf_mcam_index(mcam, pcifunc,
781 nixlf, NIXLF_BCAST_ENTRY);
782
783 if (!hw->cap.nix_rx_multicast) {
784 /* Early silicon doesn't support pkt replication,
785 * so install entry with UCAST action, so that PF
786 * receives all broadcast packets.
787 */
788 req.op = NIX_RX_ACTIONOP_UCAST;
789 } else {
790 req.op = NIX_RX_ACTIONOP_MCAST;
791 req.index = pfvf->bcast_mce_idx;
792 }
793
794 eth_broadcast_addr((u8 *)&req.packet.dmac);
795 eth_broadcast_addr((u8 *)&req.mask.dmac);
796 req.features = BIT_ULL(NPC_DMAC);
797 req.channel = chan;
798 req.chan_mask = 0xFFFU;
799 req.intf = pfvf->nix_rx_intf;
800 req.entry = index;
801 req.hdr.pcifunc = 0; /* AF is requester */
802 req.vf = pcifunc;
803
804 rvu_mbox_handler_npc_install_flow(rvu, &req, &rsp);
805 }
806
rvu_npc_enable_bcast_entry(struct rvu * rvu,u16 pcifunc,int nixlf,bool enable)807 void rvu_npc_enable_bcast_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
808 bool enable)
809 {
810 struct npc_mcam *mcam = &rvu->hw->mcam;
811 int blkaddr, index;
812
813 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
814 if (blkaddr < 0)
815 return;
816
817 /* Get 'pcifunc' of PF device */
818 pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK;
819
820 index = npc_get_nixlf_mcam_index(mcam, pcifunc, nixlf,
821 NIXLF_BCAST_ENTRY);
822 npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable);
823 }
824
rvu_npc_install_allmulti_entry(struct rvu * rvu,u16 pcifunc,int nixlf,u64 chan)825 void rvu_npc_install_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
826 u64 chan)
827 {
828 struct npc_install_flow_req req = { 0 };
829 struct npc_install_flow_rsp rsp = { 0 };
830 struct npc_mcam *mcam = &rvu->hw->mcam;
831 struct rvu_hwinfo *hw = rvu->hw;
832 int blkaddr, ucast_idx, index;
833 u8 mac_addr[ETH_ALEN] = { 0 };
834 struct nix_rx_action action = { 0 };
835 struct rvu_pfvf *pfvf;
836 u16 vf_func;
837
838 /* Only CGX PF/VF can add allmulticast entry */
839 if (is_afvf(pcifunc) && is_sdp_vf(pcifunc))
840 return;
841
842 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
843 if (blkaddr < 0)
844 return;
845
846 /* Get 'pcifunc' of PF device */
847 vf_func = pcifunc & RVU_PFVF_FUNC_MASK;
848 pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK;
849 pfvf = rvu_get_pfvf(rvu, pcifunc);
850 index = npc_get_nixlf_mcam_index(mcam, pcifunc,
851 nixlf, NIXLF_ALLMULTI_ENTRY);
852
853 /* If the corresponding PF's ucast action is RSS,
854 * use the same action for multicast entry also
855 */
856 ucast_idx = npc_get_nixlf_mcam_index(mcam, pcifunc,
857 nixlf, NIXLF_UCAST_ENTRY);
858 if (is_mcam_entry_enabled(rvu, mcam, blkaddr, ucast_idx))
859 *(u64 *)&action = npc_get_mcam_action(rvu, mcam,
860 blkaddr, ucast_idx);
861
862 if (action.op != NIX_RX_ACTIONOP_RSS) {
863 *(u64 *)&action = 0;
864 action.op = NIX_RX_ACTIONOP_UCAST;
865 action.pf_func = pcifunc;
866 }
867
868 /* RX_ACTION set to MCAST for CGX PF's */
869 if (hw->cap.nix_rx_multicast && pfvf->use_mce_list) {
870 *(u64 *)&action = 0;
871 action.op = NIX_RX_ACTIONOP_MCAST;
872 action.index = pfvf->mcast_mce_idx;
873 }
874
875 mac_addr[0] = 0x01; /* LSB bit of 1st byte in DMAC */
876 ether_addr_copy(req.packet.dmac, mac_addr);
877 ether_addr_copy(req.mask.dmac, mac_addr);
878 req.features = BIT_ULL(NPC_DMAC);
879
880 /* For cn10k the upper two bits of the channel number are
881 * cpt channel number. with masking out these bits in the
882 * mcam entry, same entry used for NIX will allow packets
883 * received from cpt for parsing.
884 */
885 if (!is_rvu_otx2(rvu))
886 req.chan_mask = NIX_CHAN_CPT_X2P_MASK;
887 else
888 req.chan_mask = 0xFFFU;
889
890 req.channel = chan;
891 req.intf = pfvf->nix_rx_intf;
892 req.entry = index;
893 req.op = action.op;
894 req.hdr.pcifunc = 0; /* AF is requester */
895 req.vf = pcifunc | vf_func;
896 req.index = action.index;
897 req.match_id = action.match_id;
898 req.flow_key_alg = action.flow_key_alg;
899
900 rvu_mbox_handler_npc_install_flow(rvu, &req, &rsp);
901 }
902
rvu_npc_enable_allmulti_entry(struct rvu * rvu,u16 pcifunc,int nixlf,bool enable)903 void rvu_npc_enable_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
904 bool enable)
905 {
906 struct npc_mcam *mcam = &rvu->hw->mcam;
907 int blkaddr, index;
908
909 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
910 if (blkaddr < 0)
911 return;
912
913 /* Get 'pcifunc' of PF device */
914 pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK;
915
916 index = npc_get_nixlf_mcam_index(mcam, pcifunc, nixlf,
917 NIXLF_ALLMULTI_ENTRY);
918 npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable);
919 }
920
npc_update_vf_flow_entry(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,u16 pcifunc,u64 rx_action)921 static void npc_update_vf_flow_entry(struct rvu *rvu, struct npc_mcam *mcam,
922 int blkaddr, u16 pcifunc, u64 rx_action)
923 {
924 int actindex, index, bank, entry;
925 struct rvu_npc_mcam_rule *rule;
926 bool enable, update;
927
928 if (!(pcifunc & RVU_PFVF_FUNC_MASK))
929 return;
930
931 mutex_lock(&mcam->lock);
932 for (index = 0; index < mcam->bmap_entries; index++) {
933 if (mcam->entry2target_pffunc[index] == pcifunc) {
934 update = true;
935 /* update not needed for the rules added via ntuple filters */
936 list_for_each_entry(rule, &mcam->mcam_rules, list) {
937 if (rule->entry == index)
938 update = false;
939 }
940 if (!update)
941 continue;
942 bank = npc_get_bank(mcam, index);
943 actindex = index;
944 entry = index & (mcam->banksize - 1);
945
946 /* read vf flow entry enable status */
947 enable = is_mcam_entry_enabled(rvu, mcam, blkaddr,
948 actindex);
949 /* disable before mcam entry update */
950 npc_enable_mcam_entry(rvu, mcam, blkaddr, actindex,
951 false);
952 /* update 'action' */
953 rvu_write64(rvu, blkaddr,
954 NPC_AF_MCAMEX_BANKX_ACTION(entry, bank),
955 rx_action);
956 if (enable)
957 npc_enable_mcam_entry(rvu, mcam, blkaddr,
958 actindex, true);
959 }
960 }
961 mutex_unlock(&mcam->lock);
962 }
963
rvu_npc_update_flowkey_alg_idx(struct rvu * rvu,u16 pcifunc,int nixlf,int group,int alg_idx,int mcam_index)964 void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf,
965 int group, int alg_idx, int mcam_index)
966 {
967 struct npc_mcam *mcam = &rvu->hw->mcam;
968 struct rvu_hwinfo *hw = rvu->hw;
969 struct nix_rx_action action;
970 int blkaddr, index, bank;
971 struct rvu_pfvf *pfvf;
972
973 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
974 if (blkaddr < 0)
975 return;
976
977 /* Check if this is for reserved default entry */
978 if (mcam_index < 0) {
979 if (group != DEFAULT_RSS_CONTEXT_GROUP)
980 return;
981 index = npc_get_nixlf_mcam_index(mcam, pcifunc,
982 nixlf, NIXLF_UCAST_ENTRY);
983 } else {
984 /* TODO: validate this mcam index */
985 index = mcam_index;
986 }
987
988 if (index >= mcam->total_entries)
989 return;
990
991 bank = npc_get_bank(mcam, index);
992 index &= (mcam->banksize - 1);
993
994 *(u64 *)&action = rvu_read64(rvu, blkaddr,
995 NPC_AF_MCAMEX_BANKX_ACTION(index, bank));
996 /* Ignore if no action was set earlier */
997 if (!*(u64 *)&action)
998 return;
999
1000 action.op = NIX_RX_ACTIONOP_RSS;
1001 action.pf_func = pcifunc;
1002 action.index = group;
1003 action.flow_key_alg = alg_idx;
1004
1005 rvu_write64(rvu, blkaddr,
1006 NPC_AF_MCAMEX_BANKX_ACTION(index, bank), *(u64 *)&action);
1007
1008 /* update the VF flow rule action with the VF default entry action */
1009 if (mcam_index < 0)
1010 npc_update_vf_flow_entry(rvu, mcam, blkaddr, pcifunc,
1011 *(u64 *)&action);
1012
1013 /* update the action change in default rule */
1014 pfvf = rvu_get_pfvf(rvu, pcifunc);
1015 if (pfvf->def_ucast_rule)
1016 pfvf->def_ucast_rule->rx_action = action;
1017
1018 index = npc_get_nixlf_mcam_index(mcam, pcifunc,
1019 nixlf, NIXLF_PROMISC_ENTRY);
1020
1021 /* If PF's promiscuous entry is enabled,
1022 * Set RSS action for that entry as well
1023 */
1024 if ((!hw->cap.nix_rx_multicast || !pfvf->use_mce_list) &&
1025 is_mcam_entry_enabled(rvu, mcam, blkaddr, index)) {
1026 bank = npc_get_bank(mcam, index);
1027 index &= (mcam->banksize - 1);
1028
1029 rvu_write64(rvu, blkaddr,
1030 NPC_AF_MCAMEX_BANKX_ACTION(index, bank),
1031 *(u64 *)&action);
1032 }
1033 }
1034
npc_enadis_default_mce_entry(struct rvu * rvu,u16 pcifunc,int nixlf,int type,bool enable)1035 void npc_enadis_default_mce_entry(struct rvu *rvu, u16 pcifunc,
1036 int nixlf, int type, bool enable)
1037 {
1038 struct npc_mcam *mcam = &rvu->hw->mcam;
1039 struct rvu_hwinfo *hw = rvu->hw;
1040 struct nix_mce_list *mce_list;
1041 int index, blkaddr, mce_idx;
1042 struct rvu_pfvf *pfvf;
1043
1044 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1045 if (blkaddr < 0)
1046 return;
1047
1048 index = npc_get_nixlf_mcam_index(mcam, pcifunc & ~RVU_PFVF_FUNC_MASK,
1049 nixlf, type);
1050
1051 /* disable MCAM entry when packet replication is not supported by hw */
1052 if (!hw->cap.nix_rx_multicast && !is_vf(pcifunc)) {
1053 npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable);
1054 return;
1055 }
1056
1057 /* return incase mce list is not enabled */
1058 pfvf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK);
1059 if (hw->cap.nix_rx_multicast && is_vf(pcifunc) &&
1060 type != NIXLF_BCAST_ENTRY && !pfvf->use_mce_list)
1061 return;
1062
1063 nix_get_mce_list(rvu, pcifunc, type, &mce_list, &mce_idx);
1064
1065 nix_update_mce_list(rvu, pcifunc, mce_list,
1066 mce_idx, index, enable);
1067 if (enable)
1068 npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable);
1069 }
1070
npc_enadis_default_entries(struct rvu * rvu,u16 pcifunc,int nixlf,bool enable)1071 static void npc_enadis_default_entries(struct rvu *rvu, u16 pcifunc,
1072 int nixlf, bool enable)
1073 {
1074 struct npc_mcam *mcam = &rvu->hw->mcam;
1075 int index, blkaddr;
1076
1077 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1078 if (blkaddr < 0)
1079 return;
1080
1081 /* Ucast MCAM match entry of this PF/VF */
1082 index = npc_get_nixlf_mcam_index(mcam, pcifunc,
1083 nixlf, NIXLF_UCAST_ENTRY);
1084 npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable);
1085
1086 /* Nothing to do for VFs, on platforms where pkt replication
1087 * is not supported
1088 */
1089 if ((pcifunc & RVU_PFVF_FUNC_MASK) && !rvu->hw->cap.nix_rx_multicast)
1090 return;
1091
1092 /* add/delete pf_func to broadcast MCE list */
1093 npc_enadis_default_mce_entry(rvu, pcifunc, nixlf,
1094 NIXLF_BCAST_ENTRY, enable);
1095 }
1096
rvu_npc_disable_default_entries(struct rvu * rvu,u16 pcifunc,int nixlf)1097 void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf)
1098 {
1099 if (nixlf < 0)
1100 return;
1101
1102 npc_enadis_default_entries(rvu, pcifunc, nixlf, false);
1103
1104 /* Delete multicast and promisc MCAM entries */
1105 npc_enadis_default_mce_entry(rvu, pcifunc, nixlf,
1106 NIXLF_ALLMULTI_ENTRY, false);
1107 npc_enadis_default_mce_entry(rvu, pcifunc, nixlf,
1108 NIXLF_PROMISC_ENTRY, false);
1109 }
1110
rvu_npc_enable_default_entries(struct rvu * rvu,u16 pcifunc,int nixlf)1111 void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf)
1112 {
1113 if (nixlf < 0)
1114 return;
1115
1116 /* Enables only broadcast match entry. Promisc/Allmulti are enabled
1117 * in set_rx_mode mbox handler.
1118 */
1119 npc_enadis_default_entries(rvu, pcifunc, nixlf, true);
1120 }
1121
rvu_npc_disable_mcam_entries(struct rvu * rvu,u16 pcifunc,int nixlf)1122 void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf)
1123 {
1124 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
1125 struct npc_mcam *mcam = &rvu->hw->mcam;
1126 struct rvu_npc_mcam_rule *rule, *tmp;
1127 int blkaddr;
1128
1129 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1130 if (blkaddr < 0)
1131 return;
1132
1133 mutex_lock(&mcam->lock);
1134
1135 /* Disable MCAM entries directing traffic to this 'pcifunc' */
1136 list_for_each_entry_safe(rule, tmp, &mcam->mcam_rules, list) {
1137 if (is_npc_intf_rx(rule->intf) &&
1138 rule->rx_action.pf_func == pcifunc &&
1139 rule->rx_action.op != NIX_RX_ACTIONOP_MCAST) {
1140 npc_enable_mcam_entry(rvu, mcam, blkaddr,
1141 rule->entry, false);
1142 rule->enable = false;
1143 /* Indicate that default rule is disabled */
1144 if (rule->default_rule) {
1145 pfvf->def_ucast_rule = NULL;
1146 list_del(&rule->list);
1147 kfree(rule);
1148 }
1149 }
1150 }
1151
1152 mutex_unlock(&mcam->lock);
1153
1154 npc_mcam_disable_flows(rvu, pcifunc);
1155
1156 rvu_npc_disable_default_entries(rvu, pcifunc, nixlf);
1157 }
1158
rvu_npc_free_mcam_entries(struct rvu * rvu,u16 pcifunc,int nixlf)1159 void rvu_npc_free_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf)
1160 {
1161 struct npc_mcam *mcam = &rvu->hw->mcam;
1162 struct rvu_npc_mcam_rule *rule, *tmp;
1163 int blkaddr;
1164
1165 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1166 if (blkaddr < 0)
1167 return;
1168
1169 mutex_lock(&mcam->lock);
1170
1171 /* Free all MCAM entries owned by this 'pcifunc' */
1172 npc_mcam_free_all_entries(rvu, mcam, blkaddr, pcifunc);
1173
1174 /* Free all MCAM counters owned by this 'pcifunc' */
1175 npc_mcam_free_all_counters(rvu, mcam, pcifunc);
1176
1177 /* Delete MCAM entries owned by this 'pcifunc' */
1178 list_for_each_entry_safe(rule, tmp, &mcam->mcam_rules, list) {
1179 if (rule->owner == pcifunc && !rule->default_rule) {
1180 list_del(&rule->list);
1181 kfree(rule);
1182 }
1183 }
1184
1185 mutex_unlock(&mcam->lock);
1186
1187 rvu_npc_disable_default_entries(rvu, pcifunc, nixlf);
1188 }
1189
1190 #define SET_KEX_LD(intf, lid, ltype, ld, cfg) \
1191 rvu_write64(rvu, blkaddr, \
1192 NPC_AF_INTFX_LIDX_LTX_LDX_CFG(intf, lid, ltype, ld), cfg)
1193
1194 #define SET_KEX_LDFLAGS(intf, ld, flags, cfg) \
1195 rvu_write64(rvu, blkaddr, \
1196 NPC_AF_INTFX_LDATAX_FLAGSX_CFG(intf, ld, flags), cfg)
1197
npc_program_mkex_rx(struct rvu * rvu,int blkaddr,struct npc_mcam_kex * mkex,u8 intf)1198 static void npc_program_mkex_rx(struct rvu *rvu, int blkaddr,
1199 struct npc_mcam_kex *mkex, u8 intf)
1200 {
1201 int lid, lt, ld, fl;
1202
1203 if (is_npc_intf_tx(intf))
1204 return;
1205
1206 rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(intf),
1207 mkex->keyx_cfg[NIX_INTF_RX]);
1208
1209 /* Program LDATA */
1210 for (lid = 0; lid < NPC_MAX_LID; lid++) {
1211 for (lt = 0; lt < NPC_MAX_LT; lt++) {
1212 for (ld = 0; ld < NPC_MAX_LD; ld++)
1213 SET_KEX_LD(intf, lid, lt, ld,
1214 mkex->intf_lid_lt_ld[NIX_INTF_RX]
1215 [lid][lt][ld]);
1216 }
1217 }
1218 /* Program LFLAGS */
1219 for (ld = 0; ld < NPC_MAX_LD; ld++) {
1220 for (fl = 0; fl < NPC_MAX_LFL; fl++)
1221 SET_KEX_LDFLAGS(intf, ld, fl,
1222 mkex->intf_ld_flags[NIX_INTF_RX]
1223 [ld][fl]);
1224 }
1225 }
1226
npc_program_mkex_tx(struct rvu * rvu,int blkaddr,struct npc_mcam_kex * mkex,u8 intf)1227 static void npc_program_mkex_tx(struct rvu *rvu, int blkaddr,
1228 struct npc_mcam_kex *mkex, u8 intf)
1229 {
1230 int lid, lt, ld, fl;
1231
1232 if (is_npc_intf_rx(intf))
1233 return;
1234
1235 rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(intf),
1236 mkex->keyx_cfg[NIX_INTF_TX]);
1237
1238 /* Program LDATA */
1239 for (lid = 0; lid < NPC_MAX_LID; lid++) {
1240 for (lt = 0; lt < NPC_MAX_LT; lt++) {
1241 for (ld = 0; ld < NPC_MAX_LD; ld++)
1242 SET_KEX_LD(intf, lid, lt, ld,
1243 mkex->intf_lid_lt_ld[NIX_INTF_TX]
1244 [lid][lt][ld]);
1245 }
1246 }
1247 /* Program LFLAGS */
1248 for (ld = 0; ld < NPC_MAX_LD; ld++) {
1249 for (fl = 0; fl < NPC_MAX_LFL; fl++)
1250 SET_KEX_LDFLAGS(intf, ld, fl,
1251 mkex->intf_ld_flags[NIX_INTF_TX]
1252 [ld][fl]);
1253 }
1254 }
1255
npc_program_mkex_profile(struct rvu * rvu,int blkaddr,struct npc_mcam_kex * mkex)1256 static void npc_program_mkex_profile(struct rvu *rvu, int blkaddr,
1257 struct npc_mcam_kex *mkex)
1258 {
1259 struct rvu_hwinfo *hw = rvu->hw;
1260 u8 intf;
1261 int ld;
1262
1263 for (ld = 0; ld < NPC_MAX_LD; ld++)
1264 rvu_write64(rvu, blkaddr, NPC_AF_KEX_LDATAX_FLAGS_CFG(ld),
1265 mkex->kex_ld_flags[ld]);
1266
1267 for (intf = 0; intf < hw->npc_intfs; intf++) {
1268 npc_program_mkex_rx(rvu, blkaddr, mkex, intf);
1269 npc_program_mkex_tx(rvu, blkaddr, mkex, intf);
1270 }
1271 }
1272
npc_fwdb_prfl_img_map(struct rvu * rvu,void __iomem ** prfl_img_addr,u64 * size)1273 static int npc_fwdb_prfl_img_map(struct rvu *rvu, void __iomem **prfl_img_addr,
1274 u64 *size)
1275 {
1276 u64 prfl_addr, prfl_sz;
1277
1278 if (!rvu->fwdata)
1279 return -EINVAL;
1280
1281 prfl_addr = rvu->fwdata->mcam_addr;
1282 prfl_sz = rvu->fwdata->mcam_sz;
1283
1284 if (!prfl_addr || !prfl_sz)
1285 return -EINVAL;
1286
1287 *prfl_img_addr = ioremap_wc(prfl_addr, prfl_sz);
1288 if (!(*prfl_img_addr))
1289 return -ENOMEM;
1290
1291 *size = prfl_sz;
1292
1293 return 0;
1294 }
1295
1296 /* strtoull of "mkexprof" with base:36 */
1297 #define MKEX_END_SIGN 0xdeadbeef
1298
npc_load_mkex_profile(struct rvu * rvu,int blkaddr,const char * mkex_profile)1299 static void npc_load_mkex_profile(struct rvu *rvu, int blkaddr,
1300 const char *mkex_profile)
1301 {
1302 struct device *dev = &rvu->pdev->dev;
1303 struct npc_mcam_kex *mcam_kex;
1304 void __iomem *mkex_prfl_addr = NULL;
1305 u64 prfl_sz;
1306 int ret;
1307
1308 /* If user not selected mkex profile */
1309 if (rvu->kpu_fwdata_sz ||
1310 !strncmp(mkex_profile, def_pfl_name, MKEX_NAME_LEN))
1311 goto program_mkex;
1312
1313 /* Setting up the mapping for mkex profile image */
1314 ret = npc_fwdb_prfl_img_map(rvu, &mkex_prfl_addr, &prfl_sz);
1315 if (ret < 0)
1316 goto program_mkex;
1317
1318 mcam_kex = (struct npc_mcam_kex __force *)mkex_prfl_addr;
1319
1320 while (((s64)prfl_sz > 0) && (mcam_kex->mkex_sign != MKEX_END_SIGN)) {
1321 /* Compare with mkex mod_param name string */
1322 if (mcam_kex->mkex_sign == MKEX_SIGN &&
1323 !strncmp(mcam_kex->name, mkex_profile, MKEX_NAME_LEN)) {
1324 /* Due to an errata (35786) in A0/B0 pass silicon,
1325 * parse nibble enable configuration has to be
1326 * identical for both Rx and Tx interfaces.
1327 */
1328 if (!is_rvu_96xx_B0(rvu) ||
1329 mcam_kex->keyx_cfg[NIX_INTF_RX] == mcam_kex->keyx_cfg[NIX_INTF_TX])
1330 rvu->kpu.mkex = mcam_kex;
1331 goto program_mkex;
1332 }
1333
1334 mcam_kex++;
1335 prfl_sz -= sizeof(struct npc_mcam_kex);
1336 }
1337 dev_warn(dev, "Failed to load requested profile: %s\n", mkex_profile);
1338
1339 program_mkex:
1340 dev_info(rvu->dev, "Using %s mkex profile\n", rvu->kpu.mkex->name);
1341 /* Program selected mkex profile */
1342 npc_program_mkex_profile(rvu, blkaddr, rvu->kpu.mkex);
1343 if (mkex_prfl_addr)
1344 iounmap(mkex_prfl_addr);
1345 }
1346
npc_config_kpuaction(struct rvu * rvu,int blkaddr,const struct npc_kpu_profile_action * kpuaction,int kpu,int entry,bool pkind)1347 static void npc_config_kpuaction(struct rvu *rvu, int blkaddr,
1348 const struct npc_kpu_profile_action *kpuaction,
1349 int kpu, int entry, bool pkind)
1350 {
1351 struct npc_kpu_action0 action0 = {0};
1352 struct npc_kpu_action1 action1 = {0};
1353 u64 reg;
1354
1355 action1.errlev = kpuaction->errlev;
1356 action1.errcode = kpuaction->errcode;
1357 action1.dp0_offset = kpuaction->dp0_offset;
1358 action1.dp1_offset = kpuaction->dp1_offset;
1359 action1.dp2_offset = kpuaction->dp2_offset;
1360
1361 if (pkind)
1362 reg = NPC_AF_PKINDX_ACTION1(entry);
1363 else
1364 reg = NPC_AF_KPUX_ENTRYX_ACTION1(kpu, entry);
1365
1366 rvu_write64(rvu, blkaddr, reg, *(u64 *)&action1);
1367
1368 action0.byp_count = kpuaction->bypass_count;
1369 action0.capture_ena = kpuaction->cap_ena;
1370 action0.parse_done = kpuaction->parse_done;
1371 action0.next_state = kpuaction->next_state;
1372 action0.capture_lid = kpuaction->lid;
1373 action0.capture_ltype = kpuaction->ltype;
1374 action0.capture_flags = kpuaction->flags;
1375 action0.ptr_advance = kpuaction->ptr_advance;
1376 action0.var_len_offset = kpuaction->offset;
1377 action0.var_len_mask = kpuaction->mask;
1378 action0.var_len_right = kpuaction->right;
1379 action0.var_len_shift = kpuaction->shift;
1380
1381 if (pkind)
1382 reg = NPC_AF_PKINDX_ACTION0(entry);
1383 else
1384 reg = NPC_AF_KPUX_ENTRYX_ACTION0(kpu, entry);
1385
1386 rvu_write64(rvu, blkaddr, reg, *(u64 *)&action0);
1387 }
1388
npc_config_kpucam(struct rvu * rvu,int blkaddr,const struct npc_kpu_profile_cam * kpucam,int kpu,int entry)1389 static void npc_config_kpucam(struct rvu *rvu, int blkaddr,
1390 const struct npc_kpu_profile_cam *kpucam,
1391 int kpu, int entry)
1392 {
1393 struct npc_kpu_cam cam0 = {0};
1394 struct npc_kpu_cam cam1 = {0};
1395
1396 cam1.state = kpucam->state & kpucam->state_mask;
1397 cam1.dp0_data = kpucam->dp0 & kpucam->dp0_mask;
1398 cam1.dp1_data = kpucam->dp1 & kpucam->dp1_mask;
1399 cam1.dp2_data = kpucam->dp2 & kpucam->dp2_mask;
1400
1401 cam0.state = ~kpucam->state & kpucam->state_mask;
1402 cam0.dp0_data = ~kpucam->dp0 & kpucam->dp0_mask;
1403 cam0.dp1_data = ~kpucam->dp1 & kpucam->dp1_mask;
1404 cam0.dp2_data = ~kpucam->dp2 & kpucam->dp2_mask;
1405
1406 rvu_write64(rvu, blkaddr,
1407 NPC_AF_KPUX_ENTRYX_CAMX(kpu, entry, 0), *(u64 *)&cam0);
1408 rvu_write64(rvu, blkaddr,
1409 NPC_AF_KPUX_ENTRYX_CAMX(kpu, entry, 1), *(u64 *)&cam1);
1410 }
1411
enable_mask(int count)1412 static inline u64 enable_mask(int count)
1413 {
1414 return (((count) < 64) ? ~(BIT_ULL(count) - 1) : (0x00ULL));
1415 }
1416
npc_program_kpu_profile(struct rvu * rvu,int blkaddr,int kpu,const struct npc_kpu_profile * profile)1417 static void npc_program_kpu_profile(struct rvu *rvu, int blkaddr, int kpu,
1418 const struct npc_kpu_profile *profile)
1419 {
1420 int entry, num_entries, max_entries;
1421 u64 entry_mask;
1422
1423 if (profile->cam_entries != profile->action_entries) {
1424 dev_err(rvu->dev,
1425 "KPU%d: CAM and action entries [%d != %d] not equal\n",
1426 kpu, profile->cam_entries, profile->action_entries);
1427 }
1428
1429 max_entries = rvu->hw->npc_kpu_entries;
1430
1431 /* Program CAM match entries for previous KPU extracted data */
1432 num_entries = min_t(int, profile->cam_entries, max_entries);
1433 for (entry = 0; entry < num_entries; entry++)
1434 npc_config_kpucam(rvu, blkaddr,
1435 &profile->cam[entry], kpu, entry);
1436
1437 /* Program this KPU's actions */
1438 num_entries = min_t(int, profile->action_entries, max_entries);
1439 for (entry = 0; entry < num_entries; entry++)
1440 npc_config_kpuaction(rvu, blkaddr, &profile->action[entry],
1441 kpu, entry, false);
1442
1443 /* Enable all programmed entries */
1444 num_entries = min_t(int, profile->action_entries, profile->cam_entries);
1445 entry_mask = enable_mask(num_entries);
1446 /* Disable first KPU_MAX_CST_ENT entries for built-in profile */
1447 if (!rvu->kpu.custom)
1448 entry_mask |= GENMASK_ULL(KPU_MAX_CST_ENT - 1, 0);
1449 rvu_write64(rvu, blkaddr,
1450 NPC_AF_KPUX_ENTRY_DISX(kpu, 0), entry_mask);
1451 if (num_entries > 64) {
1452 rvu_write64(rvu, blkaddr,
1453 NPC_AF_KPUX_ENTRY_DISX(kpu, 1),
1454 enable_mask(num_entries - 64));
1455 }
1456
1457 /* Enable this KPU */
1458 rvu_write64(rvu, blkaddr, NPC_AF_KPUX_CFG(kpu), 0x01);
1459 }
1460
npc_prepare_default_kpu(struct npc_kpu_profile_adapter * profile)1461 static int npc_prepare_default_kpu(struct npc_kpu_profile_adapter *profile)
1462 {
1463 profile->custom = 0;
1464 profile->name = def_pfl_name;
1465 profile->version = NPC_KPU_PROFILE_VER;
1466 profile->ikpu = ikpu_action_entries;
1467 profile->pkinds = ARRAY_SIZE(ikpu_action_entries);
1468 profile->kpu = npc_kpu_profiles;
1469 profile->kpus = ARRAY_SIZE(npc_kpu_profiles);
1470 profile->lt_def = &npc_lt_defaults;
1471 profile->mkex = &npc_mkex_default;
1472
1473 return 0;
1474 }
1475
npc_apply_custom_kpu(struct rvu * rvu,struct npc_kpu_profile_adapter * profile)1476 static int npc_apply_custom_kpu(struct rvu *rvu,
1477 struct npc_kpu_profile_adapter *profile)
1478 {
1479 size_t hdr_sz = sizeof(struct npc_kpu_profile_fwdata), offset = 0;
1480 struct npc_kpu_profile_fwdata *fw = rvu->kpu_fwdata;
1481 struct npc_kpu_profile_action *action;
1482 struct npc_kpu_profile_cam *cam;
1483 struct npc_kpu_fwdata *fw_kpu;
1484 int entries;
1485 u16 kpu, entry;
1486
1487 if (rvu->kpu_fwdata_sz < hdr_sz) {
1488 dev_warn(rvu->dev, "Invalid KPU profile size\n");
1489 return -EINVAL;
1490 }
1491 if (le64_to_cpu(fw->signature) != KPU_SIGN) {
1492 dev_warn(rvu->dev, "Invalid KPU profile signature %llx\n",
1493 fw->signature);
1494 return -EINVAL;
1495 }
1496 /* Verify if the using known profile structure */
1497 if (NPC_KPU_VER_MAJ(profile->version) >
1498 NPC_KPU_VER_MAJ(NPC_KPU_PROFILE_VER)) {
1499 dev_warn(rvu->dev, "Not supported Major version: %d > %d\n",
1500 NPC_KPU_VER_MAJ(profile->version),
1501 NPC_KPU_VER_MAJ(NPC_KPU_PROFILE_VER));
1502 return -EINVAL;
1503 }
1504 /* Verify if profile is aligned with the required kernel changes */
1505 if (NPC_KPU_VER_MIN(profile->version) <
1506 NPC_KPU_VER_MIN(NPC_KPU_PROFILE_VER)) {
1507 dev_warn(rvu->dev,
1508 "Invalid KPU profile version: %d.%d.%d expected version <= %d.%d.%d\n",
1509 NPC_KPU_VER_MAJ(profile->version),
1510 NPC_KPU_VER_MIN(profile->version),
1511 NPC_KPU_VER_PATCH(profile->version),
1512 NPC_KPU_VER_MAJ(NPC_KPU_PROFILE_VER),
1513 NPC_KPU_VER_MIN(NPC_KPU_PROFILE_VER),
1514 NPC_KPU_VER_PATCH(NPC_KPU_PROFILE_VER));
1515 return -EINVAL;
1516 }
1517 /* Verify if profile fits the HW */
1518 if (fw->kpus > profile->kpus) {
1519 dev_warn(rvu->dev, "Not enough KPUs: %d > %ld\n", fw->kpus,
1520 profile->kpus);
1521 return -EINVAL;
1522 }
1523
1524 profile->custom = 1;
1525 profile->name = fw->name;
1526 profile->version = le64_to_cpu(fw->version);
1527 profile->mkex = &fw->mkex;
1528 profile->lt_def = &fw->lt_def;
1529
1530 for (kpu = 0; kpu < fw->kpus; kpu++) {
1531 fw_kpu = (struct npc_kpu_fwdata *)(fw->data + offset);
1532 if (fw_kpu->entries > KPU_MAX_CST_ENT)
1533 dev_warn(rvu->dev,
1534 "Too many custom entries on KPU%d: %d > %d\n",
1535 kpu, fw_kpu->entries, KPU_MAX_CST_ENT);
1536 entries = min(fw_kpu->entries, KPU_MAX_CST_ENT);
1537 cam = (struct npc_kpu_profile_cam *)fw_kpu->data;
1538 offset += sizeof(*fw_kpu) + fw_kpu->entries * sizeof(*cam);
1539 action = (struct npc_kpu_profile_action *)(fw->data + offset);
1540 offset += fw_kpu->entries * sizeof(*action);
1541 if (rvu->kpu_fwdata_sz < hdr_sz + offset) {
1542 dev_warn(rvu->dev,
1543 "Profile size mismatch on KPU%i parsing.\n",
1544 kpu + 1);
1545 return -EINVAL;
1546 }
1547 for (entry = 0; entry < entries; entry++) {
1548 profile->kpu[kpu].cam[entry] = cam[entry];
1549 profile->kpu[kpu].action[entry] = action[entry];
1550 }
1551 }
1552
1553 return 0;
1554 }
1555
npc_load_kpu_prfl_img(struct rvu * rvu,void __iomem * prfl_addr,u64 prfl_sz,const char * kpu_profile)1556 static int npc_load_kpu_prfl_img(struct rvu *rvu, void __iomem *prfl_addr,
1557 u64 prfl_sz, const char *kpu_profile)
1558 {
1559 struct npc_kpu_profile_fwdata *kpu_data = NULL;
1560 int rc = -EINVAL;
1561
1562 kpu_data = (struct npc_kpu_profile_fwdata __force *)prfl_addr;
1563 if (le64_to_cpu(kpu_data->signature) == KPU_SIGN &&
1564 !strncmp(kpu_data->name, kpu_profile, KPU_NAME_LEN)) {
1565 dev_info(rvu->dev, "Loading KPU profile from firmware db: %s\n",
1566 kpu_profile);
1567 rvu->kpu_fwdata = kpu_data;
1568 rvu->kpu_fwdata_sz = prfl_sz;
1569 rvu->kpu_prfl_addr = prfl_addr;
1570 rc = 0;
1571 }
1572
1573 return rc;
1574 }
1575
npc_fwdb_detect_load_prfl_img(struct rvu * rvu,uint64_t prfl_sz,const char * kpu_profile)1576 static int npc_fwdb_detect_load_prfl_img(struct rvu *rvu, uint64_t prfl_sz,
1577 const char *kpu_profile)
1578 {
1579 struct npc_coalesced_kpu_prfl *img_data = NULL;
1580 int i = 0, rc = -EINVAL;
1581 void __iomem *kpu_prfl_addr;
1582 u16 offset;
1583
1584 img_data = (struct npc_coalesced_kpu_prfl __force *)rvu->kpu_prfl_addr;
1585 if (le64_to_cpu(img_data->signature) == KPU_SIGN &&
1586 !strncmp(img_data->name, kpu_profile, KPU_NAME_LEN)) {
1587 /* Loaded profile is a single KPU profile. */
1588 rc = npc_load_kpu_prfl_img(rvu, rvu->kpu_prfl_addr,
1589 prfl_sz, kpu_profile);
1590 goto done;
1591 }
1592
1593 /* Loaded profile is coalesced image, offset of first KPU profile.*/
1594 offset = offsetof(struct npc_coalesced_kpu_prfl, prfl_sz) +
1595 (img_data->num_prfl * sizeof(uint16_t));
1596 /* Check if mapped image is coalesced image. */
1597 while (i < img_data->num_prfl) {
1598 /* Profile image offsets are rounded up to next 8 multiple.*/
1599 offset = ALIGN_8B_CEIL(offset);
1600 kpu_prfl_addr = (void __iomem *)((uintptr_t)rvu->kpu_prfl_addr +
1601 offset);
1602 rc = npc_load_kpu_prfl_img(rvu, kpu_prfl_addr,
1603 img_data->prfl_sz[i], kpu_profile);
1604 if (!rc)
1605 break;
1606 /* Calculating offset of profile image based on profile size.*/
1607 offset += img_data->prfl_sz[i];
1608 i++;
1609 }
1610 done:
1611 return rc;
1612 }
1613
npc_load_kpu_profile_fwdb(struct rvu * rvu,const char * kpu_profile)1614 static int npc_load_kpu_profile_fwdb(struct rvu *rvu, const char *kpu_profile)
1615 {
1616 int ret = -EINVAL;
1617 u64 prfl_sz;
1618
1619 /* Setting up the mapping for NPC profile image */
1620 ret = npc_fwdb_prfl_img_map(rvu, &rvu->kpu_prfl_addr, &prfl_sz);
1621 if (ret < 0)
1622 goto done;
1623
1624 /* Detect if profile is coalesced or single KPU profile and load */
1625 ret = npc_fwdb_detect_load_prfl_img(rvu, prfl_sz, kpu_profile);
1626 if (ret == 0)
1627 goto done;
1628
1629 /* Cleaning up if KPU profile image from fwdata is not valid. */
1630 if (rvu->kpu_prfl_addr) {
1631 iounmap(rvu->kpu_prfl_addr);
1632 rvu->kpu_prfl_addr = NULL;
1633 rvu->kpu_fwdata_sz = 0;
1634 rvu->kpu_fwdata = NULL;
1635 }
1636
1637 done:
1638 return ret;
1639 }
1640
npc_load_kpu_profile(struct rvu * rvu)1641 static void npc_load_kpu_profile(struct rvu *rvu)
1642 {
1643 struct npc_kpu_profile_adapter *profile = &rvu->kpu;
1644 const char *kpu_profile = rvu->kpu_pfl_name;
1645 const struct firmware *fw = NULL;
1646 bool retry_fwdb = false;
1647
1648 /* If user not specified profile customization */
1649 if (!strncmp(kpu_profile, def_pfl_name, KPU_NAME_LEN))
1650 goto revert_to_default;
1651 /* First prepare default KPU, then we'll customize top entries. */
1652 npc_prepare_default_kpu(profile);
1653
1654 /* Order of preceedence for load loading NPC profile (high to low)
1655 * Firmware binary in filesystem.
1656 * Firmware database method.
1657 * Default KPU profile.
1658 */
1659 if (!request_firmware_direct(&fw, kpu_profile, rvu->dev)) {
1660 dev_info(rvu->dev, "Loading KPU profile from firmware: %s\n",
1661 kpu_profile);
1662 rvu->kpu_fwdata = kzalloc(fw->size, GFP_KERNEL);
1663 if (rvu->kpu_fwdata) {
1664 memcpy(rvu->kpu_fwdata, fw->data, fw->size);
1665 rvu->kpu_fwdata_sz = fw->size;
1666 }
1667 release_firmware(fw);
1668 retry_fwdb = true;
1669 goto program_kpu;
1670 }
1671
1672 load_image_fwdb:
1673 /* Loading the KPU profile using firmware database */
1674 if (npc_load_kpu_profile_fwdb(rvu, kpu_profile))
1675 goto revert_to_default;
1676
1677 program_kpu:
1678 /* Apply profile customization if firmware was loaded. */
1679 if (!rvu->kpu_fwdata_sz || npc_apply_custom_kpu(rvu, profile)) {
1680 /* If image from firmware filesystem fails to load or invalid
1681 * retry with firmware database method.
1682 */
1683 if (rvu->kpu_fwdata || rvu->kpu_fwdata_sz) {
1684 /* Loading image from firmware database failed. */
1685 if (rvu->kpu_prfl_addr) {
1686 iounmap(rvu->kpu_prfl_addr);
1687 rvu->kpu_prfl_addr = NULL;
1688 } else {
1689 kfree(rvu->kpu_fwdata);
1690 }
1691 rvu->kpu_fwdata = NULL;
1692 rvu->kpu_fwdata_sz = 0;
1693 if (retry_fwdb) {
1694 retry_fwdb = false;
1695 goto load_image_fwdb;
1696 }
1697 }
1698
1699 dev_warn(rvu->dev,
1700 "Can't load KPU profile %s. Using default.\n",
1701 kpu_profile);
1702 kfree(rvu->kpu_fwdata);
1703 rvu->kpu_fwdata = NULL;
1704 goto revert_to_default;
1705 }
1706
1707 dev_info(rvu->dev, "Using custom profile '%s', version %d.%d.%d\n",
1708 profile->name, NPC_KPU_VER_MAJ(profile->version),
1709 NPC_KPU_VER_MIN(profile->version),
1710 NPC_KPU_VER_PATCH(profile->version));
1711
1712 return;
1713
1714 revert_to_default:
1715 npc_prepare_default_kpu(profile);
1716 }
1717
npc_parser_profile_init(struct rvu * rvu,int blkaddr)1718 static void npc_parser_profile_init(struct rvu *rvu, int blkaddr)
1719 {
1720 struct rvu_hwinfo *hw = rvu->hw;
1721 int num_pkinds, num_kpus, idx;
1722
1723 /* Disable all KPUs and their entries */
1724 for (idx = 0; idx < hw->npc_kpus; idx++) {
1725 rvu_write64(rvu, blkaddr,
1726 NPC_AF_KPUX_ENTRY_DISX(idx, 0), ~0ULL);
1727 rvu_write64(rvu, blkaddr,
1728 NPC_AF_KPUX_ENTRY_DISX(idx, 1), ~0ULL);
1729 rvu_write64(rvu, blkaddr, NPC_AF_KPUX_CFG(idx), 0x00);
1730 }
1731
1732 /* Load and customize KPU profile. */
1733 npc_load_kpu_profile(rvu);
1734
1735 /* First program IKPU profile i.e PKIND configs.
1736 * Check HW max count to avoid configuring junk or
1737 * writing to unsupported CSR addresses.
1738 */
1739 num_pkinds = rvu->kpu.pkinds;
1740 num_pkinds = min_t(int, hw->npc_pkinds, num_pkinds);
1741
1742 for (idx = 0; idx < num_pkinds; idx++)
1743 npc_config_kpuaction(rvu, blkaddr, &rvu->kpu.ikpu[idx], 0, idx, true);
1744
1745 /* Program KPU CAM and Action profiles */
1746 num_kpus = rvu->kpu.kpus;
1747 num_kpus = min_t(int, hw->npc_kpus, num_kpus);
1748
1749 for (idx = 0; idx < num_kpus; idx++)
1750 npc_program_kpu_profile(rvu, blkaddr, idx, &rvu->kpu.kpu[idx]);
1751 }
1752
npc_mcam_rsrcs_init(struct rvu * rvu,int blkaddr)1753 static int npc_mcam_rsrcs_init(struct rvu *rvu, int blkaddr)
1754 {
1755 int nixlf_count = rvu_get_nixlf_count(rvu);
1756 struct npc_mcam *mcam = &rvu->hw->mcam;
1757 int rsvd, err;
1758 u16 index;
1759 int cntr;
1760 u64 cfg;
1761
1762 /* Actual number of MCAM entries vary by entry size */
1763 cfg = (rvu_read64(rvu, blkaddr,
1764 NPC_AF_INTFX_KEX_CFG(0)) >> 32) & 0x07;
1765 mcam->total_entries = (mcam->banks / BIT_ULL(cfg)) * mcam->banksize;
1766 mcam->keysize = cfg;
1767
1768 /* Number of banks combined per MCAM entry */
1769 if (cfg == NPC_MCAM_KEY_X4)
1770 mcam->banks_per_entry = 4;
1771 else if (cfg == NPC_MCAM_KEY_X2)
1772 mcam->banks_per_entry = 2;
1773 else
1774 mcam->banks_per_entry = 1;
1775
1776 /* Reserve one MCAM entry for each of the NIX LF to
1777 * guarantee space to install default matching DMAC rule.
1778 * Also reserve 2 MCAM entries for each PF for default
1779 * channel based matching or 'bcast & promisc' matching to
1780 * support BCAST and PROMISC modes of operation for PFs.
1781 * PF0 is excluded.
1782 */
1783 rsvd = (nixlf_count * RSVD_MCAM_ENTRIES_PER_NIXLF) +
1784 ((rvu->hw->total_pfs - 1) * RSVD_MCAM_ENTRIES_PER_PF);
1785 if (mcam->total_entries <= rsvd) {
1786 dev_warn(rvu->dev,
1787 "Insufficient NPC MCAM size %d for pkt I/O, exiting\n",
1788 mcam->total_entries);
1789 return -ENOMEM;
1790 }
1791
1792 mcam->bmap_entries = mcam->total_entries - rsvd;
1793 mcam->nixlf_offset = mcam->bmap_entries;
1794 mcam->pf_offset = mcam->nixlf_offset + nixlf_count;
1795
1796 /* Allocate bitmaps for managing MCAM entries */
1797 mcam->bmap = devm_kcalloc(rvu->dev, BITS_TO_LONGS(mcam->bmap_entries),
1798 sizeof(long), GFP_KERNEL);
1799 if (!mcam->bmap)
1800 return -ENOMEM;
1801
1802 mcam->bmap_reverse = devm_kcalloc(rvu->dev,
1803 BITS_TO_LONGS(mcam->bmap_entries),
1804 sizeof(long), GFP_KERNEL);
1805 if (!mcam->bmap_reverse)
1806 return -ENOMEM;
1807
1808 mcam->bmap_fcnt = mcam->bmap_entries;
1809
1810 /* Alloc memory for saving entry to RVU PFFUNC allocation mapping */
1811 mcam->entry2pfvf_map = devm_kcalloc(rvu->dev, mcam->bmap_entries,
1812 sizeof(u16), GFP_KERNEL);
1813 if (!mcam->entry2pfvf_map)
1814 return -ENOMEM;
1815
1816 /* Reserve 1/8th of MCAM entries at the bottom for low priority
1817 * allocations and another 1/8th at the top for high priority
1818 * allocations.
1819 */
1820 mcam->lprio_count = mcam->bmap_entries / 8;
1821 if (mcam->lprio_count > BITS_PER_LONG)
1822 mcam->lprio_count = round_down(mcam->lprio_count,
1823 BITS_PER_LONG);
1824 mcam->lprio_start = mcam->bmap_entries - mcam->lprio_count;
1825 mcam->hprio_count = mcam->lprio_count;
1826 mcam->hprio_end = mcam->hprio_count;
1827
1828
1829 /* Allocate bitmap for managing MCAM counters and memory
1830 * for saving counter to RVU PFFUNC allocation mapping.
1831 */
1832 err = rvu_alloc_bitmap(&mcam->counters);
1833 if (err)
1834 return err;
1835
1836 mcam->cntr2pfvf_map = devm_kcalloc(rvu->dev, mcam->counters.max,
1837 sizeof(u16), GFP_KERNEL);
1838 if (!mcam->cntr2pfvf_map)
1839 goto free_mem;
1840
1841 /* Alloc memory for MCAM entry to counter mapping and for tracking
1842 * counter's reference count.
1843 */
1844 mcam->entry2cntr_map = devm_kcalloc(rvu->dev, mcam->bmap_entries,
1845 sizeof(u16), GFP_KERNEL);
1846 if (!mcam->entry2cntr_map)
1847 goto free_mem;
1848
1849 mcam->cntr_refcnt = devm_kcalloc(rvu->dev, mcam->counters.max,
1850 sizeof(u16), GFP_KERNEL);
1851 if (!mcam->cntr_refcnt)
1852 goto free_mem;
1853
1854 /* Alloc memory for saving target device of mcam rule */
1855 mcam->entry2target_pffunc = devm_kcalloc(rvu->dev, mcam->total_entries,
1856 sizeof(u16), GFP_KERNEL);
1857 if (!mcam->entry2target_pffunc)
1858 goto free_mem;
1859
1860 for (index = 0; index < mcam->bmap_entries; index++) {
1861 mcam->entry2pfvf_map[index] = NPC_MCAM_INVALID_MAP;
1862 mcam->entry2cntr_map[index] = NPC_MCAM_INVALID_MAP;
1863 }
1864
1865 for (cntr = 0; cntr < mcam->counters.max; cntr++)
1866 mcam->cntr2pfvf_map[cntr] = NPC_MCAM_INVALID_MAP;
1867
1868 mutex_init(&mcam->lock);
1869
1870 return 0;
1871
1872 free_mem:
1873 kfree(mcam->counters.bmap);
1874 return -ENOMEM;
1875 }
1876
rvu_npc_hw_init(struct rvu * rvu,int blkaddr)1877 static void rvu_npc_hw_init(struct rvu *rvu, int blkaddr)
1878 {
1879 struct npc_pkind *pkind = &rvu->hw->pkind;
1880 struct npc_mcam *mcam = &rvu->hw->mcam;
1881 struct rvu_hwinfo *hw = rvu->hw;
1882 u64 npc_const, npc_const1;
1883 u64 npc_const2 = 0;
1884
1885 npc_const = rvu_read64(rvu, blkaddr, NPC_AF_CONST);
1886 npc_const1 = rvu_read64(rvu, blkaddr, NPC_AF_CONST1);
1887 if (npc_const1 & BIT_ULL(63))
1888 npc_const2 = rvu_read64(rvu, blkaddr, NPC_AF_CONST2);
1889
1890 pkind->rsrc.max = NPC_UNRESERVED_PKIND_COUNT;
1891 hw->npc_pkinds = (npc_const1 >> 12) & 0xFFULL;
1892 hw->npc_kpu_entries = npc_const1 & 0xFFFULL;
1893 hw->npc_kpus = (npc_const >> 8) & 0x1FULL;
1894 hw->npc_intfs = npc_const & 0xFULL;
1895 hw->npc_counters = (npc_const >> 48) & 0xFFFFULL;
1896
1897 mcam->banks = (npc_const >> 44) & 0xFULL;
1898 mcam->banksize = (npc_const >> 28) & 0xFFFFULL;
1899 hw->npc_stat_ena = BIT_ULL(9);
1900 /* Extended set */
1901 if (npc_const2) {
1902 hw->npc_ext_set = true;
1903 /* 96xx supports only match_stats and npc_counters
1904 * reflected in NPC_AF_CONST reg.
1905 * STAT_SEL and ENA are at [0:8] and 9 bit positions.
1906 * 98xx has both match_stat and ext and npc_counter
1907 * reflected in NPC_AF_CONST2
1908 * STAT_SEL_EXT added at [12:14] bit position.
1909 * cn10k supports only ext and hence npc_counters in
1910 * NPC_AF_CONST is 0 and npc_counters reflected in NPC_AF_CONST2.
1911 * STAT_SEL bitpos incremented from [0:8] to [0:11] and ENA bit moved to 63
1912 */
1913 if (!hw->npc_counters)
1914 hw->npc_stat_ena = BIT_ULL(63);
1915 hw->npc_counters = (npc_const2 >> 16) & 0xFFFFULL;
1916 mcam->banksize = npc_const2 & 0xFFFFULL;
1917 }
1918
1919 mcam->counters.max = hw->npc_counters;
1920 }
1921
rvu_npc_setup_interfaces(struct rvu * rvu,int blkaddr)1922 static void rvu_npc_setup_interfaces(struct rvu *rvu, int blkaddr)
1923 {
1924 struct npc_mcam_kex *mkex = rvu->kpu.mkex;
1925 struct npc_mcam *mcam = &rvu->hw->mcam;
1926 struct rvu_hwinfo *hw = rvu->hw;
1927 u64 nibble_ena, rx_kex, tx_kex;
1928 u8 intf;
1929
1930 /* Reserve last counter for MCAM RX miss action which is set to
1931 * drop packet. This way we will know how many pkts didn't match
1932 * any MCAM entry.
1933 */
1934 mcam->counters.max--;
1935 mcam->rx_miss_act_cntr = mcam->counters.max;
1936
1937 rx_kex = mkex->keyx_cfg[NIX_INTF_RX];
1938 tx_kex = mkex->keyx_cfg[NIX_INTF_TX];
1939 nibble_ena = FIELD_GET(NPC_PARSE_NIBBLE, rx_kex);
1940
1941 nibble_ena = rvu_npc_get_tx_nibble_cfg(rvu, nibble_ena);
1942 if (nibble_ena) {
1943 tx_kex &= ~NPC_PARSE_NIBBLE;
1944 tx_kex |= FIELD_PREP(NPC_PARSE_NIBBLE, nibble_ena);
1945 mkex->keyx_cfg[NIX_INTF_TX] = tx_kex;
1946 }
1947
1948 /* Configure RX interfaces */
1949 for (intf = 0; intf < hw->npc_intfs; intf++) {
1950 if (is_npc_intf_tx(intf))
1951 continue;
1952
1953 /* Set RX MCAM search key size. LA..LE (ltype only) + Channel */
1954 rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(intf),
1955 rx_kex);
1956
1957 /* If MCAM lookup doesn't result in a match, drop the received
1958 * packet. And map this action to a counter to count dropped
1959 * packets.
1960 */
1961 rvu_write64(rvu, blkaddr,
1962 NPC_AF_INTFX_MISS_ACT(intf), NIX_RX_ACTIONOP_DROP);
1963
1964 /* NPC_AF_INTFX_MISS_STAT_ACT[14:12] - counter[11:9]
1965 * NPC_AF_INTFX_MISS_STAT_ACT[8:0] - counter[8:0]
1966 */
1967 rvu_write64(rvu, blkaddr,
1968 NPC_AF_INTFX_MISS_STAT_ACT(intf),
1969 ((mcam->rx_miss_act_cntr >> 9) << 12) |
1970 hw->npc_stat_ena | mcam->rx_miss_act_cntr);
1971 }
1972
1973 /* Configure TX interfaces */
1974 for (intf = 0; intf < hw->npc_intfs; intf++) {
1975 if (is_npc_intf_rx(intf))
1976 continue;
1977
1978 /* Extract Ltypes LID_LA to LID_LE */
1979 rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(intf),
1980 tx_kex);
1981
1982 /* Set TX miss action to UCAST_DEFAULT i.e
1983 * transmit the packet on NIX LF SQ's default channel.
1984 */
1985 rvu_write64(rvu, blkaddr,
1986 NPC_AF_INTFX_MISS_ACT(intf),
1987 NIX_TX_ACTIONOP_UCAST_DEFAULT);
1988 }
1989 }
1990
rvu_npc_init(struct rvu * rvu)1991 int rvu_npc_init(struct rvu *rvu)
1992 {
1993 struct npc_kpu_profile_adapter *kpu = &rvu->kpu;
1994 struct npc_pkind *pkind = &rvu->hw->pkind;
1995 struct npc_mcam *mcam = &rvu->hw->mcam;
1996 int blkaddr, entry, bank, err;
1997
1998 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1999 if (blkaddr < 0) {
2000 dev_err(rvu->dev, "%s: NPC block not implemented\n", __func__);
2001 return -ENODEV;
2002 }
2003
2004 rvu_npc_hw_init(rvu, blkaddr);
2005
2006 /* First disable all MCAM entries, to stop traffic towards NIXLFs */
2007 for (bank = 0; bank < mcam->banks; bank++) {
2008 for (entry = 0; entry < mcam->banksize; entry++)
2009 rvu_write64(rvu, blkaddr,
2010 NPC_AF_MCAMEX_BANKX_CFG(entry, bank), 0);
2011 }
2012
2013 err = rvu_alloc_bitmap(&pkind->rsrc);
2014 if (err)
2015 return err;
2016 /* Reserve PKIND#0 for LBKs. Power reset value of LBK_CH_PKIND is '0',
2017 * no need to configure PKIND for all LBKs separately.
2018 */
2019 rvu_alloc_rsrc(&pkind->rsrc);
2020
2021 /* Allocate mem for pkind to PF and channel mapping info */
2022 pkind->pfchan_map = devm_kcalloc(rvu->dev, pkind->rsrc.max,
2023 sizeof(u32), GFP_KERNEL);
2024 if (!pkind->pfchan_map)
2025 return -ENOMEM;
2026
2027 /* Configure KPU profile */
2028 npc_parser_profile_init(rvu, blkaddr);
2029
2030 /* Config Outer L2, IPv4's NPC layer info */
2031 rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_OL2,
2032 (kpu->lt_def->pck_ol2.lid << 8) | (kpu->lt_def->pck_ol2.ltype_match << 4) |
2033 kpu->lt_def->pck_ol2.ltype_mask);
2034 rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_OIP4,
2035 (kpu->lt_def->pck_oip4.lid << 8) | (kpu->lt_def->pck_oip4.ltype_match << 4) |
2036 kpu->lt_def->pck_oip4.ltype_mask);
2037
2038 /* Config Inner IPV4 NPC layer info */
2039 rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_IIP4,
2040 (kpu->lt_def->pck_iip4.lid << 8) | (kpu->lt_def->pck_iip4.ltype_match << 4) |
2041 kpu->lt_def->pck_iip4.ltype_mask);
2042
2043 /* Enable below for Rx pkts.
2044 * - Outer IPv4 header checksum validation.
2045 * - Detect outer L2 broadcast address and set NPC_RESULT_S[L2B].
2046 * - Detect outer L2 multicast address and set NPC_RESULT_S[L2M].
2047 * - Inner IPv4 header checksum validation.
2048 * - Set non zero checksum error code value
2049 */
2050 rvu_write64(rvu, blkaddr, NPC_AF_PCK_CFG,
2051 rvu_read64(rvu, blkaddr, NPC_AF_PCK_CFG) |
2052 ((u64)NPC_EC_OIP4_CSUM << 32) | (NPC_EC_IIP4_CSUM << 24) |
2053 BIT_ULL(7) | BIT_ULL(6) | BIT_ULL(2) | BIT_ULL(1));
2054
2055 rvu_npc_setup_interfaces(rvu, blkaddr);
2056
2057 /* Configure MKEX profile */
2058 npc_load_mkex_profile(rvu, blkaddr, rvu->mkex_pfl_name);
2059
2060 err = npc_mcam_rsrcs_init(rvu, blkaddr);
2061 if (err)
2062 return err;
2063
2064 err = npc_flow_steering_init(rvu, blkaddr);
2065 if (err) {
2066 dev_err(rvu->dev,
2067 "Incorrect mkex profile loaded using default mkex\n");
2068 npc_load_mkex_profile(rvu, blkaddr, def_pfl_name);
2069 }
2070
2071 return 0;
2072 }
2073
rvu_npc_freemem(struct rvu * rvu)2074 void rvu_npc_freemem(struct rvu *rvu)
2075 {
2076 struct npc_pkind *pkind = &rvu->hw->pkind;
2077 struct npc_mcam *mcam = &rvu->hw->mcam;
2078
2079 kfree(pkind->rsrc.bmap);
2080 kfree(mcam->counters.bmap);
2081 if (rvu->kpu_prfl_addr)
2082 iounmap(rvu->kpu_prfl_addr);
2083 else
2084 kfree(rvu->kpu_fwdata);
2085 mutex_destroy(&mcam->lock);
2086 }
2087
rvu_npc_get_mcam_entry_alloc_info(struct rvu * rvu,u16 pcifunc,int blkaddr,int * alloc_cnt,int * enable_cnt)2088 void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc,
2089 int blkaddr, int *alloc_cnt,
2090 int *enable_cnt)
2091 {
2092 struct npc_mcam *mcam = &rvu->hw->mcam;
2093 int entry;
2094
2095 *alloc_cnt = 0;
2096 *enable_cnt = 0;
2097
2098 for (entry = 0; entry < mcam->bmap_entries; entry++) {
2099 if (mcam->entry2pfvf_map[entry] == pcifunc) {
2100 (*alloc_cnt)++;
2101 if (is_mcam_entry_enabled(rvu, mcam, blkaddr, entry))
2102 (*enable_cnt)++;
2103 }
2104 }
2105 }
2106
rvu_npc_get_mcam_counter_alloc_info(struct rvu * rvu,u16 pcifunc,int blkaddr,int * alloc_cnt,int * enable_cnt)2107 void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc,
2108 int blkaddr, int *alloc_cnt,
2109 int *enable_cnt)
2110 {
2111 struct npc_mcam *mcam = &rvu->hw->mcam;
2112 int cntr;
2113
2114 *alloc_cnt = 0;
2115 *enable_cnt = 0;
2116
2117 for (cntr = 0; cntr < mcam->counters.max; cntr++) {
2118 if (mcam->cntr2pfvf_map[cntr] == pcifunc) {
2119 (*alloc_cnt)++;
2120 if (mcam->cntr_refcnt[cntr])
2121 (*enable_cnt)++;
2122 }
2123 }
2124 }
2125
npc_mcam_verify_entry(struct npc_mcam * mcam,u16 pcifunc,int entry)2126 static int npc_mcam_verify_entry(struct npc_mcam *mcam,
2127 u16 pcifunc, int entry)
2128 {
2129 /* verify AF installed entries */
2130 if (is_pffunc_af(pcifunc))
2131 return 0;
2132 /* Verify if entry is valid and if it is indeed
2133 * allocated to the requesting PFFUNC.
2134 */
2135 if (entry >= mcam->bmap_entries)
2136 return NPC_MCAM_INVALID_REQ;
2137
2138 if (pcifunc != mcam->entry2pfvf_map[entry])
2139 return NPC_MCAM_PERM_DENIED;
2140
2141 return 0;
2142 }
2143
npc_mcam_verify_counter(struct npc_mcam * mcam,u16 pcifunc,int cntr)2144 static int npc_mcam_verify_counter(struct npc_mcam *mcam,
2145 u16 pcifunc, int cntr)
2146 {
2147 /* Verify if counter is valid and if it is indeed
2148 * allocated to the requesting PFFUNC.
2149 */
2150 if (cntr >= mcam->counters.max)
2151 return NPC_MCAM_INVALID_REQ;
2152
2153 if (pcifunc != mcam->cntr2pfvf_map[cntr])
2154 return NPC_MCAM_PERM_DENIED;
2155
2156 return 0;
2157 }
2158
npc_map_mcam_entry_and_cntr(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,u16 entry,u16 cntr)2159 static void npc_map_mcam_entry_and_cntr(struct rvu *rvu, struct npc_mcam *mcam,
2160 int blkaddr, u16 entry, u16 cntr)
2161 {
2162 u16 index = entry & (mcam->banksize - 1);
2163 u32 bank = npc_get_bank(mcam, entry);
2164 struct rvu_hwinfo *hw = rvu->hw;
2165
2166 /* Set mapping and increment counter's refcnt */
2167 mcam->entry2cntr_map[entry] = cntr;
2168 mcam->cntr_refcnt[cntr]++;
2169 /* Enable stats */
2170 rvu_write64(rvu, blkaddr,
2171 NPC_AF_MCAMEX_BANKX_STAT_ACT(index, bank),
2172 ((cntr >> 9) << 12) | hw->npc_stat_ena | cntr);
2173 }
2174
npc_unmap_mcam_entry_and_cntr(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,u16 entry,u16 cntr)2175 static void npc_unmap_mcam_entry_and_cntr(struct rvu *rvu,
2176 struct npc_mcam *mcam,
2177 int blkaddr, u16 entry, u16 cntr)
2178 {
2179 u16 index = entry & (mcam->banksize - 1);
2180 u32 bank = npc_get_bank(mcam, entry);
2181
2182 /* Remove mapping and reduce counter's refcnt */
2183 mcam->entry2cntr_map[entry] = NPC_MCAM_INVALID_MAP;
2184 mcam->cntr_refcnt[cntr]--;
2185 /* Disable stats */
2186 rvu_write64(rvu, blkaddr,
2187 NPC_AF_MCAMEX_BANKX_STAT_ACT(index, bank), 0x00);
2188 }
2189
2190 /* Sets MCAM entry in bitmap as used. Update
2191 * reverse bitmap too. Should be called with
2192 * 'mcam->lock' held.
2193 */
npc_mcam_set_bit(struct npc_mcam * mcam,u16 index)2194 static void npc_mcam_set_bit(struct npc_mcam *mcam, u16 index)
2195 {
2196 u16 entry, rentry;
2197
2198 entry = index;
2199 rentry = mcam->bmap_entries - index - 1;
2200
2201 __set_bit(entry, mcam->bmap);
2202 __set_bit(rentry, mcam->bmap_reverse);
2203 mcam->bmap_fcnt--;
2204 }
2205
2206 /* Sets MCAM entry in bitmap as free. Update
2207 * reverse bitmap too. Should be called with
2208 * 'mcam->lock' held.
2209 */
npc_mcam_clear_bit(struct npc_mcam * mcam,u16 index)2210 static void npc_mcam_clear_bit(struct npc_mcam *mcam, u16 index)
2211 {
2212 u16 entry, rentry;
2213
2214 entry = index;
2215 rentry = mcam->bmap_entries - index - 1;
2216
2217 __clear_bit(entry, mcam->bmap);
2218 __clear_bit(rentry, mcam->bmap_reverse);
2219 mcam->bmap_fcnt++;
2220 }
2221
npc_mcam_free_all_entries(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,u16 pcifunc)2222 static void npc_mcam_free_all_entries(struct rvu *rvu, struct npc_mcam *mcam,
2223 int blkaddr, u16 pcifunc)
2224 {
2225 u16 index, cntr;
2226
2227 /* Scan all MCAM entries and free the ones mapped to 'pcifunc' */
2228 for (index = 0; index < mcam->bmap_entries; index++) {
2229 if (mcam->entry2pfvf_map[index] == pcifunc) {
2230 mcam->entry2pfvf_map[index] = NPC_MCAM_INVALID_MAP;
2231 /* Free the entry in bitmap */
2232 npc_mcam_clear_bit(mcam, index);
2233 /* Disable the entry */
2234 npc_enable_mcam_entry(rvu, mcam, blkaddr, index, false);
2235
2236 /* Update entry2counter mapping */
2237 cntr = mcam->entry2cntr_map[index];
2238 if (cntr != NPC_MCAM_INVALID_MAP)
2239 npc_unmap_mcam_entry_and_cntr(rvu, mcam,
2240 blkaddr, index,
2241 cntr);
2242 mcam->entry2target_pffunc[index] = 0x0;
2243 }
2244 }
2245 }
2246
npc_mcam_free_all_counters(struct rvu * rvu,struct npc_mcam * mcam,u16 pcifunc)2247 static void npc_mcam_free_all_counters(struct rvu *rvu, struct npc_mcam *mcam,
2248 u16 pcifunc)
2249 {
2250 u16 cntr;
2251
2252 /* Scan all MCAM counters and free the ones mapped to 'pcifunc' */
2253 for (cntr = 0; cntr < mcam->counters.max; cntr++) {
2254 if (mcam->cntr2pfvf_map[cntr] == pcifunc) {
2255 mcam->cntr2pfvf_map[cntr] = NPC_MCAM_INVALID_MAP;
2256 mcam->cntr_refcnt[cntr] = 0;
2257 rvu_free_rsrc(&mcam->counters, cntr);
2258 /* This API is expected to be called after freeing
2259 * MCAM entries, which inturn will remove
2260 * 'entry to counter' mapping.
2261 * No need to do it again.
2262 */
2263 }
2264 }
2265 }
2266
2267 /* Find area of contiguous free entries of size 'nr'.
2268 * If not found return max contiguous free entries available.
2269 */
npc_mcam_find_zero_area(unsigned long * map,u16 size,u16 start,u16 nr,u16 * max_area)2270 static u16 npc_mcam_find_zero_area(unsigned long *map, u16 size, u16 start,
2271 u16 nr, u16 *max_area)
2272 {
2273 u16 max_area_start = 0;
2274 u16 index, next, end;
2275
2276 *max_area = 0;
2277
2278 again:
2279 index = find_next_zero_bit(map, size, start);
2280 if (index >= size)
2281 return max_area_start;
2282
2283 end = ((index + nr) >= size) ? size : index + nr;
2284 next = find_next_bit(map, end, index);
2285 if (*max_area < (next - index)) {
2286 *max_area = next - index;
2287 max_area_start = index;
2288 }
2289
2290 if (next < end) {
2291 start = next + 1;
2292 goto again;
2293 }
2294
2295 return max_area_start;
2296 }
2297
2298 /* Find number of free MCAM entries available
2299 * within range i.e in between 'start' and 'end'.
2300 */
npc_mcam_get_free_count(unsigned long * map,u16 start,u16 end)2301 static u16 npc_mcam_get_free_count(unsigned long *map, u16 start, u16 end)
2302 {
2303 u16 index, next;
2304 u16 fcnt = 0;
2305
2306 again:
2307 if (start >= end)
2308 return fcnt;
2309
2310 index = find_next_zero_bit(map, end, start);
2311 if (index >= end)
2312 return fcnt;
2313
2314 next = find_next_bit(map, end, index);
2315 if (next <= end) {
2316 fcnt += next - index;
2317 start = next + 1;
2318 goto again;
2319 }
2320
2321 fcnt += end - index;
2322 return fcnt;
2323 }
2324
2325 static void
npc_get_mcam_search_range_priority(struct npc_mcam * mcam,struct npc_mcam_alloc_entry_req * req,u16 * start,u16 * end,bool * reverse)2326 npc_get_mcam_search_range_priority(struct npc_mcam *mcam,
2327 struct npc_mcam_alloc_entry_req *req,
2328 u16 *start, u16 *end, bool *reverse)
2329 {
2330 u16 fcnt;
2331
2332 if (req->priority == NPC_MCAM_HIGHER_PRIO)
2333 goto hprio;
2334
2335 /* For a low priority entry allocation
2336 * - If reference entry is not in hprio zone then
2337 * search range: ref_entry to end.
2338 * - If reference entry is in hprio zone and if
2339 * request can be accomodated in non-hprio zone then
2340 * search range: 'start of middle zone' to 'end'
2341 * - else search in reverse, so that less number of hprio
2342 * zone entries are allocated.
2343 */
2344
2345 *reverse = false;
2346 *start = req->ref_entry + 1;
2347 *end = mcam->bmap_entries;
2348
2349 if (req->ref_entry >= mcam->hprio_end)
2350 return;
2351
2352 fcnt = npc_mcam_get_free_count(mcam->bmap,
2353 mcam->hprio_end, mcam->bmap_entries);
2354 if (fcnt > req->count)
2355 *start = mcam->hprio_end;
2356 else
2357 *reverse = true;
2358 return;
2359
2360 hprio:
2361 /* For a high priority entry allocation, search is always
2362 * in reverse to preserve hprio zone entries.
2363 * - If reference entry is not in lprio zone then
2364 * search range: 0 to ref_entry.
2365 * - If reference entry is in lprio zone and if
2366 * request can be accomodated in middle zone then
2367 * search range: 'hprio_end' to 'lprio_start'
2368 */
2369
2370 *reverse = true;
2371 *start = 0;
2372 *end = req->ref_entry;
2373
2374 if (req->ref_entry <= mcam->lprio_start)
2375 return;
2376
2377 fcnt = npc_mcam_get_free_count(mcam->bmap,
2378 mcam->hprio_end, mcam->lprio_start);
2379 if (fcnt < req->count)
2380 return;
2381 *start = mcam->hprio_end;
2382 *end = mcam->lprio_start;
2383 }
2384
npc_mcam_alloc_entries(struct npc_mcam * mcam,u16 pcifunc,struct npc_mcam_alloc_entry_req * req,struct npc_mcam_alloc_entry_rsp * rsp)2385 static int npc_mcam_alloc_entries(struct npc_mcam *mcam, u16 pcifunc,
2386 struct npc_mcam_alloc_entry_req *req,
2387 struct npc_mcam_alloc_entry_rsp *rsp)
2388 {
2389 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES];
2390 u16 fcnt, hp_fcnt, lp_fcnt;
2391 u16 start, end, index;
2392 int entry, next_start;
2393 bool reverse = false;
2394 unsigned long *bmap;
2395 u16 max_contig;
2396
2397 mutex_lock(&mcam->lock);
2398
2399 /* Check if there are any free entries */
2400 if (!mcam->bmap_fcnt) {
2401 mutex_unlock(&mcam->lock);
2402 return NPC_MCAM_ALLOC_FAILED;
2403 }
2404
2405 /* MCAM entries are divided into high priority, middle and
2406 * low priority zones. Idea is to not allocate top and lower
2407 * most entries as much as possible, this is to increase
2408 * probability of honouring priority allocation requests.
2409 *
2410 * Two bitmaps are used for mcam entry management,
2411 * mcam->bmap for forward search i.e '0 to mcam->bmap_entries'.
2412 * mcam->bmap_reverse for reverse search i.e 'mcam->bmap_entries to 0'.
2413 *
2414 * Reverse bitmap is used to allocate entries
2415 * - when a higher priority entry is requested
2416 * - when available free entries are less.
2417 * Lower priority ones out of avaialble free entries are always
2418 * chosen when 'high vs low' question arises.
2419 */
2420
2421 /* Get the search range for priority allocation request */
2422 if (req->priority) {
2423 npc_get_mcam_search_range_priority(mcam, req,
2424 &start, &end, &reverse);
2425 goto alloc;
2426 }
2427
2428 /* For a VF base MCAM match rule is set by its PF. And all the
2429 * further MCAM rules installed by VF on its own are
2430 * concatenated with the base rule set by its PF. Hence PF entries
2431 * should be at lower priority compared to VF entries. Otherwise
2432 * base rule is hit always and rules installed by VF will be of
2433 * no use. Hence if the request is from PF and NOT a priority
2434 * allocation request then allocate low priority entries.
2435 */
2436 if (!(pcifunc & RVU_PFVF_FUNC_MASK))
2437 goto lprio_alloc;
2438
2439 /* Find out the search range for non-priority allocation request
2440 *
2441 * Get MCAM free entry count in middle zone.
2442 */
2443 lp_fcnt = npc_mcam_get_free_count(mcam->bmap,
2444 mcam->lprio_start,
2445 mcam->bmap_entries);
2446 hp_fcnt = npc_mcam_get_free_count(mcam->bmap, 0, mcam->hprio_end);
2447 fcnt = mcam->bmap_fcnt - lp_fcnt - hp_fcnt;
2448
2449 /* Check if request can be accomodated in the middle zone */
2450 if (fcnt > req->count) {
2451 start = mcam->hprio_end;
2452 end = mcam->lprio_start;
2453 } else if ((fcnt + (hp_fcnt / 2) + (lp_fcnt / 2)) > req->count) {
2454 /* Expand search zone from half of hprio zone to
2455 * half of lprio zone.
2456 */
2457 start = mcam->hprio_end / 2;
2458 end = mcam->bmap_entries - (mcam->lprio_count / 2);
2459 reverse = true;
2460 } else {
2461 /* Not enough free entries, search all entries in reverse,
2462 * so that low priority ones will get used up.
2463 */
2464 lprio_alloc:
2465 reverse = true;
2466 start = 0;
2467 end = mcam->bmap_entries;
2468 }
2469
2470 alloc:
2471 if (reverse) {
2472 bmap = mcam->bmap_reverse;
2473 start = mcam->bmap_entries - start;
2474 end = mcam->bmap_entries - end;
2475 swap(start, end);
2476 } else {
2477 bmap = mcam->bmap;
2478 }
2479
2480 if (req->contig) {
2481 /* Allocate requested number of contiguous entries, if
2482 * unsuccessful find max contiguous entries available.
2483 */
2484 index = npc_mcam_find_zero_area(bmap, end, start,
2485 req->count, &max_contig);
2486 rsp->count = max_contig;
2487 if (reverse)
2488 rsp->entry = mcam->bmap_entries - index - max_contig;
2489 else
2490 rsp->entry = index;
2491 } else {
2492 /* Allocate requested number of non-contiguous entries,
2493 * if unsuccessful allocate as many as possible.
2494 */
2495 rsp->count = 0;
2496 next_start = start;
2497 for (entry = 0; entry < req->count; entry++) {
2498 index = find_next_zero_bit(bmap, end, next_start);
2499 if (index >= end)
2500 break;
2501
2502 next_start = start + (index - start) + 1;
2503
2504 /* Save the entry's index */
2505 if (reverse)
2506 index = mcam->bmap_entries - index - 1;
2507 entry_list[entry] = index;
2508 rsp->count++;
2509 }
2510 }
2511
2512 /* If allocating requested no of entries is unsucessful,
2513 * expand the search range to full bitmap length and retry.
2514 */
2515 if (!req->priority && (rsp->count < req->count) &&
2516 ((end - start) != mcam->bmap_entries)) {
2517 reverse = true;
2518 start = 0;
2519 end = mcam->bmap_entries;
2520 goto alloc;
2521 }
2522
2523 /* For priority entry allocation requests, if allocation is
2524 * failed then expand search to max possible range and retry.
2525 */
2526 if (req->priority && rsp->count < req->count) {
2527 if (req->priority == NPC_MCAM_LOWER_PRIO &&
2528 (start != (req->ref_entry + 1))) {
2529 start = req->ref_entry + 1;
2530 end = mcam->bmap_entries;
2531 reverse = false;
2532 goto alloc;
2533 } else if ((req->priority == NPC_MCAM_HIGHER_PRIO) &&
2534 ((end - start) != req->ref_entry)) {
2535 start = 0;
2536 end = req->ref_entry;
2537 reverse = true;
2538 goto alloc;
2539 }
2540 }
2541
2542 /* Copy MCAM entry indices into mbox response entry_list.
2543 * Requester always expects indices in ascending order, so
2544 * so reverse the list if reverse bitmap is used for allocation.
2545 */
2546 if (!req->contig && rsp->count) {
2547 index = 0;
2548 for (entry = rsp->count - 1; entry >= 0; entry--) {
2549 if (reverse)
2550 rsp->entry_list[index++] = entry_list[entry];
2551 else
2552 rsp->entry_list[entry] = entry_list[entry];
2553 }
2554 }
2555
2556 /* Mark the allocated entries as used and set nixlf mapping */
2557 for (entry = 0; entry < rsp->count; entry++) {
2558 index = req->contig ?
2559 (rsp->entry + entry) : rsp->entry_list[entry];
2560 npc_mcam_set_bit(mcam, index);
2561 mcam->entry2pfvf_map[index] = pcifunc;
2562 mcam->entry2cntr_map[index] = NPC_MCAM_INVALID_MAP;
2563 }
2564
2565 /* Update available free count in mbox response */
2566 rsp->free_count = mcam->bmap_fcnt;
2567
2568 mutex_unlock(&mcam->lock);
2569 return 0;
2570 }
2571
rvu_mbox_handler_npc_mcam_alloc_entry(struct rvu * rvu,struct npc_mcam_alloc_entry_req * req,struct npc_mcam_alloc_entry_rsp * rsp)2572 int rvu_mbox_handler_npc_mcam_alloc_entry(struct rvu *rvu,
2573 struct npc_mcam_alloc_entry_req *req,
2574 struct npc_mcam_alloc_entry_rsp *rsp)
2575 {
2576 struct npc_mcam *mcam = &rvu->hw->mcam;
2577 u16 pcifunc = req->hdr.pcifunc;
2578 int blkaddr;
2579
2580 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2581 if (blkaddr < 0)
2582 return NPC_MCAM_INVALID_REQ;
2583
2584 rsp->entry = NPC_MCAM_ENTRY_INVALID;
2585 rsp->free_count = 0;
2586
2587 /* Check if ref_entry is within range */
2588 if (req->priority && req->ref_entry >= mcam->bmap_entries) {
2589 dev_err(rvu->dev, "%s: reference entry %d is out of range\n",
2590 __func__, req->ref_entry);
2591 return NPC_MCAM_INVALID_REQ;
2592 }
2593
2594 /* ref_entry can't be '0' if requested priority is high.
2595 * Can't be last entry if requested priority is low.
2596 */
2597 if ((!req->ref_entry && req->priority == NPC_MCAM_HIGHER_PRIO) ||
2598 ((req->ref_entry == (mcam->bmap_entries - 1)) &&
2599 req->priority == NPC_MCAM_LOWER_PRIO))
2600 return NPC_MCAM_INVALID_REQ;
2601
2602 /* Since list of allocated indices needs to be sent to requester,
2603 * max number of non-contiguous entries per mbox msg is limited.
2604 */
2605 if (!req->contig && req->count > NPC_MAX_NONCONTIG_ENTRIES) {
2606 dev_err(rvu->dev,
2607 "%s: %d Non-contiguous MCAM entries requested is more than max (%d) allowed\n",
2608 __func__, req->count, NPC_MAX_NONCONTIG_ENTRIES);
2609 return NPC_MCAM_INVALID_REQ;
2610 }
2611
2612 /* Alloc request from PFFUNC with no NIXLF attached should be denied */
2613 if (!is_pffunc_af(pcifunc) && !is_nixlf_attached(rvu, pcifunc))
2614 return NPC_MCAM_ALLOC_DENIED;
2615
2616 return npc_mcam_alloc_entries(mcam, pcifunc, req, rsp);
2617 }
2618
rvu_mbox_handler_npc_mcam_free_entry(struct rvu * rvu,struct npc_mcam_free_entry_req * req,struct msg_rsp * rsp)2619 int rvu_mbox_handler_npc_mcam_free_entry(struct rvu *rvu,
2620 struct npc_mcam_free_entry_req *req,
2621 struct msg_rsp *rsp)
2622 {
2623 struct npc_mcam *mcam = &rvu->hw->mcam;
2624 u16 pcifunc = req->hdr.pcifunc;
2625 int blkaddr, rc = 0;
2626 u16 cntr;
2627
2628 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2629 if (blkaddr < 0)
2630 return NPC_MCAM_INVALID_REQ;
2631
2632 /* Free request from PFFUNC with no NIXLF attached, ignore */
2633 if (!is_pffunc_af(pcifunc) && !is_nixlf_attached(rvu, pcifunc))
2634 return NPC_MCAM_INVALID_REQ;
2635
2636 mutex_lock(&mcam->lock);
2637
2638 if (req->all)
2639 goto free_all;
2640
2641 rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry);
2642 if (rc)
2643 goto exit;
2644
2645 mcam->entry2pfvf_map[req->entry] = NPC_MCAM_INVALID_MAP;
2646 mcam->entry2target_pffunc[req->entry] = 0x0;
2647 npc_mcam_clear_bit(mcam, req->entry);
2648 npc_enable_mcam_entry(rvu, mcam, blkaddr, req->entry, false);
2649
2650 /* Update entry2counter mapping */
2651 cntr = mcam->entry2cntr_map[req->entry];
2652 if (cntr != NPC_MCAM_INVALID_MAP)
2653 npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr,
2654 req->entry, cntr);
2655
2656 goto exit;
2657
2658 free_all:
2659 /* Free up all entries allocated to requesting PFFUNC */
2660 npc_mcam_free_all_entries(rvu, mcam, blkaddr, pcifunc);
2661 exit:
2662 mutex_unlock(&mcam->lock);
2663 return rc;
2664 }
2665
rvu_mbox_handler_npc_mcam_read_entry(struct rvu * rvu,struct npc_mcam_read_entry_req * req,struct npc_mcam_read_entry_rsp * rsp)2666 int rvu_mbox_handler_npc_mcam_read_entry(struct rvu *rvu,
2667 struct npc_mcam_read_entry_req *req,
2668 struct npc_mcam_read_entry_rsp *rsp)
2669 {
2670 struct npc_mcam *mcam = &rvu->hw->mcam;
2671 u16 pcifunc = req->hdr.pcifunc;
2672 int blkaddr, rc;
2673
2674 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2675 if (blkaddr < 0)
2676 return NPC_MCAM_INVALID_REQ;
2677
2678 mutex_lock(&mcam->lock);
2679 rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry);
2680 if (!rc) {
2681 npc_read_mcam_entry(rvu, mcam, blkaddr, req->entry,
2682 &rsp->entry_data,
2683 &rsp->intf, &rsp->enable);
2684 }
2685
2686 mutex_unlock(&mcam->lock);
2687 return rc;
2688 }
2689
rvu_mbox_handler_npc_mcam_write_entry(struct rvu * rvu,struct npc_mcam_write_entry_req * req,struct msg_rsp * rsp)2690 int rvu_mbox_handler_npc_mcam_write_entry(struct rvu *rvu,
2691 struct npc_mcam_write_entry_req *req,
2692 struct msg_rsp *rsp)
2693 {
2694 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc);
2695 struct npc_mcam *mcam = &rvu->hw->mcam;
2696 u16 pcifunc = req->hdr.pcifunc;
2697 int blkaddr, rc;
2698 u8 nix_intf;
2699
2700 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2701 if (blkaddr < 0)
2702 return NPC_MCAM_INVALID_REQ;
2703
2704 mutex_lock(&mcam->lock);
2705 rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry);
2706 if (rc)
2707 goto exit;
2708
2709 if (req->set_cntr &&
2710 npc_mcam_verify_counter(mcam, pcifunc, req->cntr)) {
2711 rc = NPC_MCAM_INVALID_REQ;
2712 goto exit;
2713 }
2714
2715 if (!is_npc_interface_valid(rvu, req->intf)) {
2716 rc = NPC_MCAM_INVALID_REQ;
2717 goto exit;
2718 }
2719
2720 if (is_npc_intf_tx(req->intf))
2721 nix_intf = pfvf->nix_tx_intf;
2722 else
2723 nix_intf = pfvf->nix_rx_intf;
2724
2725 if (!is_pffunc_af(pcifunc) &&
2726 npc_mcam_verify_pf_func(rvu, &req->entry_data, req->intf, pcifunc)) {
2727 rc = NPC_MCAM_INVALID_REQ;
2728 goto exit;
2729 }
2730
2731 /* For AF installed rules, the nix_intf should be set to target NIX */
2732 if (is_pffunc_af(req->hdr.pcifunc))
2733 nix_intf = req->intf;
2734
2735 npc_config_mcam_entry(rvu, mcam, blkaddr, req->entry, nix_intf,
2736 &req->entry_data, req->enable_entry);
2737
2738 if (req->set_cntr)
2739 npc_map_mcam_entry_and_cntr(rvu, mcam, blkaddr,
2740 req->entry, req->cntr);
2741
2742 rc = 0;
2743 exit:
2744 mutex_unlock(&mcam->lock);
2745 return rc;
2746 }
2747
rvu_mbox_handler_npc_mcam_ena_entry(struct rvu * rvu,struct npc_mcam_ena_dis_entry_req * req,struct msg_rsp * rsp)2748 int rvu_mbox_handler_npc_mcam_ena_entry(struct rvu *rvu,
2749 struct npc_mcam_ena_dis_entry_req *req,
2750 struct msg_rsp *rsp)
2751 {
2752 struct npc_mcam *mcam = &rvu->hw->mcam;
2753 u16 pcifunc = req->hdr.pcifunc;
2754 int blkaddr, rc;
2755
2756 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2757 if (blkaddr < 0)
2758 return NPC_MCAM_INVALID_REQ;
2759
2760 mutex_lock(&mcam->lock);
2761 rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry);
2762 mutex_unlock(&mcam->lock);
2763 if (rc)
2764 return rc;
2765
2766 npc_enable_mcam_entry(rvu, mcam, blkaddr, req->entry, true);
2767
2768 return 0;
2769 }
2770
rvu_mbox_handler_npc_mcam_dis_entry(struct rvu * rvu,struct npc_mcam_ena_dis_entry_req * req,struct msg_rsp * rsp)2771 int rvu_mbox_handler_npc_mcam_dis_entry(struct rvu *rvu,
2772 struct npc_mcam_ena_dis_entry_req *req,
2773 struct msg_rsp *rsp)
2774 {
2775 struct npc_mcam *mcam = &rvu->hw->mcam;
2776 u16 pcifunc = req->hdr.pcifunc;
2777 int blkaddr, rc;
2778
2779 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2780 if (blkaddr < 0)
2781 return NPC_MCAM_INVALID_REQ;
2782
2783 mutex_lock(&mcam->lock);
2784 rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry);
2785 mutex_unlock(&mcam->lock);
2786 if (rc)
2787 return rc;
2788
2789 npc_enable_mcam_entry(rvu, mcam, blkaddr, req->entry, false);
2790
2791 return 0;
2792 }
2793
rvu_mbox_handler_npc_mcam_shift_entry(struct rvu * rvu,struct npc_mcam_shift_entry_req * req,struct npc_mcam_shift_entry_rsp * rsp)2794 int rvu_mbox_handler_npc_mcam_shift_entry(struct rvu *rvu,
2795 struct npc_mcam_shift_entry_req *req,
2796 struct npc_mcam_shift_entry_rsp *rsp)
2797 {
2798 struct npc_mcam *mcam = &rvu->hw->mcam;
2799 u16 pcifunc = req->hdr.pcifunc;
2800 u16 old_entry, new_entry;
2801 int blkaddr, rc = 0;
2802 u16 index, cntr;
2803
2804 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2805 if (blkaddr < 0)
2806 return NPC_MCAM_INVALID_REQ;
2807
2808 if (req->shift_count > NPC_MCAM_MAX_SHIFTS)
2809 return NPC_MCAM_INVALID_REQ;
2810
2811 mutex_lock(&mcam->lock);
2812 for (index = 0; index < req->shift_count; index++) {
2813 old_entry = req->curr_entry[index];
2814 new_entry = req->new_entry[index];
2815
2816 /* Check if both old and new entries are valid and
2817 * does belong to this PFFUNC or not.
2818 */
2819 rc = npc_mcam_verify_entry(mcam, pcifunc, old_entry);
2820 if (rc)
2821 break;
2822
2823 rc = npc_mcam_verify_entry(mcam, pcifunc, new_entry);
2824 if (rc)
2825 break;
2826
2827 /* new_entry should not have a counter mapped */
2828 if (mcam->entry2cntr_map[new_entry] != NPC_MCAM_INVALID_MAP) {
2829 rc = NPC_MCAM_PERM_DENIED;
2830 break;
2831 }
2832
2833 /* Disable the new_entry */
2834 npc_enable_mcam_entry(rvu, mcam, blkaddr, new_entry, false);
2835
2836 /* Copy rule from old entry to new entry */
2837 npc_copy_mcam_entry(rvu, mcam, blkaddr, old_entry, new_entry);
2838
2839 /* Copy counter mapping, if any */
2840 cntr = mcam->entry2cntr_map[old_entry];
2841 if (cntr != NPC_MCAM_INVALID_MAP) {
2842 npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr,
2843 old_entry, cntr);
2844 npc_map_mcam_entry_and_cntr(rvu, mcam, blkaddr,
2845 new_entry, cntr);
2846 }
2847
2848 /* Enable new_entry and disable old_entry */
2849 npc_enable_mcam_entry(rvu, mcam, blkaddr, new_entry, true);
2850 npc_enable_mcam_entry(rvu, mcam, blkaddr, old_entry, false);
2851 }
2852
2853 /* If shift has failed then report the failed index */
2854 if (index != req->shift_count) {
2855 rc = NPC_MCAM_PERM_DENIED;
2856 rsp->failed_entry_idx = index;
2857 }
2858
2859 mutex_unlock(&mcam->lock);
2860 return rc;
2861 }
2862
rvu_mbox_handler_npc_mcam_alloc_counter(struct rvu * rvu,struct npc_mcam_alloc_counter_req * req,struct npc_mcam_alloc_counter_rsp * rsp)2863 int rvu_mbox_handler_npc_mcam_alloc_counter(struct rvu *rvu,
2864 struct npc_mcam_alloc_counter_req *req,
2865 struct npc_mcam_alloc_counter_rsp *rsp)
2866 {
2867 struct npc_mcam *mcam = &rvu->hw->mcam;
2868 u16 pcifunc = req->hdr.pcifunc;
2869 u16 max_contig, cntr;
2870 int blkaddr, index;
2871
2872 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2873 if (blkaddr < 0)
2874 return NPC_MCAM_INVALID_REQ;
2875
2876 /* If the request is from a PFFUNC with no NIXLF attached, ignore */
2877 if (!is_pffunc_af(pcifunc) && !is_nixlf_attached(rvu, pcifunc))
2878 return NPC_MCAM_INVALID_REQ;
2879
2880 /* Since list of allocated counter IDs needs to be sent to requester,
2881 * max number of non-contiguous counters per mbox msg is limited.
2882 */
2883 if (!req->contig && req->count > NPC_MAX_NONCONTIG_COUNTERS)
2884 return NPC_MCAM_INVALID_REQ;
2885
2886 mutex_lock(&mcam->lock);
2887
2888 /* Check if unused counters are available or not */
2889 if (!rvu_rsrc_free_count(&mcam->counters)) {
2890 mutex_unlock(&mcam->lock);
2891 return NPC_MCAM_ALLOC_FAILED;
2892 }
2893
2894 rsp->count = 0;
2895
2896 if (req->contig) {
2897 /* Allocate requested number of contiguous counters, if
2898 * unsuccessful find max contiguous entries available.
2899 */
2900 index = npc_mcam_find_zero_area(mcam->counters.bmap,
2901 mcam->counters.max, 0,
2902 req->count, &max_contig);
2903 rsp->count = max_contig;
2904 rsp->cntr = index;
2905 for (cntr = index; cntr < (index + max_contig); cntr++) {
2906 __set_bit(cntr, mcam->counters.bmap);
2907 mcam->cntr2pfvf_map[cntr] = pcifunc;
2908 }
2909 } else {
2910 /* Allocate requested number of non-contiguous counters,
2911 * if unsuccessful allocate as many as possible.
2912 */
2913 for (cntr = 0; cntr < req->count; cntr++) {
2914 index = rvu_alloc_rsrc(&mcam->counters);
2915 if (index < 0)
2916 break;
2917 rsp->cntr_list[cntr] = index;
2918 rsp->count++;
2919 mcam->cntr2pfvf_map[index] = pcifunc;
2920 }
2921 }
2922
2923 mutex_unlock(&mcam->lock);
2924 return 0;
2925 }
2926
rvu_mbox_handler_npc_mcam_free_counter(struct rvu * rvu,struct npc_mcam_oper_counter_req * req,struct msg_rsp * rsp)2927 int rvu_mbox_handler_npc_mcam_free_counter(struct rvu *rvu,
2928 struct npc_mcam_oper_counter_req *req, struct msg_rsp *rsp)
2929 {
2930 struct npc_mcam *mcam = &rvu->hw->mcam;
2931 u16 index, entry = 0;
2932 int blkaddr, err;
2933
2934 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2935 if (blkaddr < 0)
2936 return NPC_MCAM_INVALID_REQ;
2937
2938 mutex_lock(&mcam->lock);
2939 err = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr);
2940 if (err) {
2941 mutex_unlock(&mcam->lock);
2942 return err;
2943 }
2944
2945 /* Mark counter as free/unused */
2946 mcam->cntr2pfvf_map[req->cntr] = NPC_MCAM_INVALID_MAP;
2947 rvu_free_rsrc(&mcam->counters, req->cntr);
2948
2949 /* Disable all MCAM entry's stats which are using this counter */
2950 while (entry < mcam->bmap_entries) {
2951 if (!mcam->cntr_refcnt[req->cntr])
2952 break;
2953
2954 index = find_next_bit(mcam->bmap, mcam->bmap_entries, entry);
2955 if (index >= mcam->bmap_entries)
2956 break;
2957 entry = index + 1;
2958 if (mcam->entry2cntr_map[index] != req->cntr)
2959 continue;
2960
2961 npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr,
2962 index, req->cntr);
2963 }
2964
2965 mutex_unlock(&mcam->lock);
2966 return 0;
2967 }
2968
rvu_mbox_handler_npc_mcam_unmap_counter(struct rvu * rvu,struct npc_mcam_unmap_counter_req * req,struct msg_rsp * rsp)2969 int rvu_mbox_handler_npc_mcam_unmap_counter(struct rvu *rvu,
2970 struct npc_mcam_unmap_counter_req *req, struct msg_rsp *rsp)
2971 {
2972 struct npc_mcam *mcam = &rvu->hw->mcam;
2973 u16 index, entry = 0;
2974 int blkaddr, rc;
2975
2976 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2977 if (blkaddr < 0)
2978 return NPC_MCAM_INVALID_REQ;
2979
2980 mutex_lock(&mcam->lock);
2981 rc = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr);
2982 if (rc)
2983 goto exit;
2984
2985 /* Unmap the MCAM entry and counter */
2986 if (!req->all) {
2987 rc = npc_mcam_verify_entry(mcam, req->hdr.pcifunc, req->entry);
2988 if (rc)
2989 goto exit;
2990 npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr,
2991 req->entry, req->cntr);
2992 goto exit;
2993 }
2994
2995 /* Disable all MCAM entry's stats which are using this counter */
2996 while (entry < mcam->bmap_entries) {
2997 if (!mcam->cntr_refcnt[req->cntr])
2998 break;
2999
3000 index = find_next_bit(mcam->bmap, mcam->bmap_entries, entry);
3001 if (index >= mcam->bmap_entries)
3002 break;
3003 entry = index + 1;
3004
3005 if (mcam->entry2cntr_map[index] != req->cntr)
3006 continue;
3007
3008 npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr,
3009 index, req->cntr);
3010 }
3011 exit:
3012 mutex_unlock(&mcam->lock);
3013 return rc;
3014 }
3015
rvu_mbox_handler_npc_mcam_clear_counter(struct rvu * rvu,struct npc_mcam_oper_counter_req * req,struct msg_rsp * rsp)3016 int rvu_mbox_handler_npc_mcam_clear_counter(struct rvu *rvu,
3017 struct npc_mcam_oper_counter_req *req, struct msg_rsp *rsp)
3018 {
3019 struct npc_mcam *mcam = &rvu->hw->mcam;
3020 int blkaddr, err;
3021
3022 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
3023 if (blkaddr < 0)
3024 return NPC_MCAM_INVALID_REQ;
3025
3026 mutex_lock(&mcam->lock);
3027 err = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr);
3028 mutex_unlock(&mcam->lock);
3029 if (err)
3030 return err;
3031
3032 rvu_write64(rvu, blkaddr, NPC_AF_MATCH_STATX(req->cntr), 0x00);
3033
3034 return 0;
3035 }
3036
rvu_mbox_handler_npc_mcam_counter_stats(struct rvu * rvu,struct npc_mcam_oper_counter_req * req,struct npc_mcam_oper_counter_rsp * rsp)3037 int rvu_mbox_handler_npc_mcam_counter_stats(struct rvu *rvu,
3038 struct npc_mcam_oper_counter_req *req,
3039 struct npc_mcam_oper_counter_rsp *rsp)
3040 {
3041 struct npc_mcam *mcam = &rvu->hw->mcam;
3042 int blkaddr, err;
3043
3044 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
3045 if (blkaddr < 0)
3046 return NPC_MCAM_INVALID_REQ;
3047
3048 mutex_lock(&mcam->lock);
3049 err = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr);
3050 mutex_unlock(&mcam->lock);
3051 if (err)
3052 return err;
3053
3054 rsp->stat = rvu_read64(rvu, blkaddr, NPC_AF_MATCH_STATX(req->cntr));
3055 rsp->stat &= BIT_ULL(48) - 1;
3056
3057 return 0;
3058 }
3059
rvu_mbox_handler_npc_mcam_alloc_and_write_entry(struct rvu * rvu,struct npc_mcam_alloc_and_write_entry_req * req,struct npc_mcam_alloc_and_write_entry_rsp * rsp)3060 int rvu_mbox_handler_npc_mcam_alloc_and_write_entry(struct rvu *rvu,
3061 struct npc_mcam_alloc_and_write_entry_req *req,
3062 struct npc_mcam_alloc_and_write_entry_rsp *rsp)
3063 {
3064 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc);
3065 struct npc_mcam_alloc_counter_req cntr_req;
3066 struct npc_mcam_alloc_counter_rsp cntr_rsp;
3067 struct npc_mcam_alloc_entry_req entry_req;
3068 struct npc_mcam_alloc_entry_rsp entry_rsp;
3069 struct npc_mcam *mcam = &rvu->hw->mcam;
3070 u16 entry = NPC_MCAM_ENTRY_INVALID;
3071 u16 cntr = NPC_MCAM_ENTRY_INVALID;
3072 int blkaddr, rc;
3073 u8 nix_intf;
3074
3075 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
3076 if (blkaddr < 0)
3077 return NPC_MCAM_INVALID_REQ;
3078
3079 if (!is_npc_interface_valid(rvu, req->intf))
3080 return NPC_MCAM_INVALID_REQ;
3081
3082 if (npc_mcam_verify_pf_func(rvu, &req->entry_data, req->intf,
3083 req->hdr.pcifunc))
3084 return NPC_MCAM_INVALID_REQ;
3085
3086 /* Try to allocate a MCAM entry */
3087 entry_req.hdr.pcifunc = req->hdr.pcifunc;
3088 entry_req.contig = true;
3089 entry_req.priority = req->priority;
3090 entry_req.ref_entry = req->ref_entry;
3091 entry_req.count = 1;
3092
3093 rc = rvu_mbox_handler_npc_mcam_alloc_entry(rvu,
3094 &entry_req, &entry_rsp);
3095 if (rc)
3096 return rc;
3097
3098 if (!entry_rsp.count)
3099 return NPC_MCAM_ALLOC_FAILED;
3100
3101 entry = entry_rsp.entry;
3102
3103 if (!req->alloc_cntr)
3104 goto write_entry;
3105
3106 /* Now allocate counter */
3107 cntr_req.hdr.pcifunc = req->hdr.pcifunc;
3108 cntr_req.contig = true;
3109 cntr_req.count = 1;
3110
3111 rc = rvu_mbox_handler_npc_mcam_alloc_counter(rvu, &cntr_req, &cntr_rsp);
3112 if (rc) {
3113 /* Free allocated MCAM entry */
3114 mutex_lock(&mcam->lock);
3115 mcam->entry2pfvf_map[entry] = NPC_MCAM_INVALID_MAP;
3116 npc_mcam_clear_bit(mcam, entry);
3117 mutex_unlock(&mcam->lock);
3118 return rc;
3119 }
3120
3121 cntr = cntr_rsp.cntr;
3122
3123 write_entry:
3124 mutex_lock(&mcam->lock);
3125
3126 if (is_npc_intf_tx(req->intf))
3127 nix_intf = pfvf->nix_tx_intf;
3128 else
3129 nix_intf = pfvf->nix_rx_intf;
3130
3131 npc_config_mcam_entry(rvu, mcam, blkaddr, entry, nix_intf,
3132 &req->entry_data, req->enable_entry);
3133
3134 if (req->alloc_cntr)
3135 npc_map_mcam_entry_and_cntr(rvu, mcam, blkaddr, entry, cntr);
3136 mutex_unlock(&mcam->lock);
3137
3138 rsp->entry = entry;
3139 rsp->cntr = cntr;
3140
3141 return 0;
3142 }
3143
3144 #define GET_KEX_CFG(intf) \
3145 rvu_read64(rvu, BLKADDR_NPC, NPC_AF_INTFX_KEX_CFG(intf))
3146
3147 #define GET_KEX_FLAGS(ld) \
3148 rvu_read64(rvu, BLKADDR_NPC, NPC_AF_KEX_LDATAX_FLAGS_CFG(ld))
3149
3150 #define GET_KEX_LD(intf, lid, lt, ld) \
3151 rvu_read64(rvu, BLKADDR_NPC, \
3152 NPC_AF_INTFX_LIDX_LTX_LDX_CFG(intf, lid, lt, ld))
3153
3154 #define GET_KEX_LDFLAGS(intf, ld, fl) \
3155 rvu_read64(rvu, BLKADDR_NPC, \
3156 NPC_AF_INTFX_LDATAX_FLAGSX_CFG(intf, ld, fl))
3157
rvu_mbox_handler_npc_get_kex_cfg(struct rvu * rvu,struct msg_req * req,struct npc_get_kex_cfg_rsp * rsp)3158 int rvu_mbox_handler_npc_get_kex_cfg(struct rvu *rvu, struct msg_req *req,
3159 struct npc_get_kex_cfg_rsp *rsp)
3160 {
3161 int lid, lt, ld, fl;
3162
3163 rsp->rx_keyx_cfg = GET_KEX_CFG(NIX_INTF_RX);
3164 rsp->tx_keyx_cfg = GET_KEX_CFG(NIX_INTF_TX);
3165 for (lid = 0; lid < NPC_MAX_LID; lid++) {
3166 for (lt = 0; lt < NPC_MAX_LT; lt++) {
3167 for (ld = 0; ld < NPC_MAX_LD; ld++) {
3168 rsp->intf_lid_lt_ld[NIX_INTF_RX][lid][lt][ld] =
3169 GET_KEX_LD(NIX_INTF_RX, lid, lt, ld);
3170 rsp->intf_lid_lt_ld[NIX_INTF_TX][lid][lt][ld] =
3171 GET_KEX_LD(NIX_INTF_TX, lid, lt, ld);
3172 }
3173 }
3174 }
3175 for (ld = 0; ld < NPC_MAX_LD; ld++)
3176 rsp->kex_ld_flags[ld] = GET_KEX_FLAGS(ld);
3177
3178 for (ld = 0; ld < NPC_MAX_LD; ld++) {
3179 for (fl = 0; fl < NPC_MAX_LFL; fl++) {
3180 rsp->intf_ld_flags[NIX_INTF_RX][ld][fl] =
3181 GET_KEX_LDFLAGS(NIX_INTF_RX, ld, fl);
3182 rsp->intf_ld_flags[NIX_INTF_TX][ld][fl] =
3183 GET_KEX_LDFLAGS(NIX_INTF_TX, ld, fl);
3184 }
3185 }
3186 memcpy(rsp->mkex_pfl_name, rvu->mkex_pfl_name, MKEX_NAME_LEN);
3187 return 0;
3188 }
3189
3190 static int
npc_set_var_len_offset_pkind(struct rvu * rvu,u16 pcifunc,u64 pkind,u8 var_len_off,u8 var_len_off_mask,u8 shift_dir)3191 npc_set_var_len_offset_pkind(struct rvu *rvu, u16 pcifunc, u64 pkind,
3192 u8 var_len_off, u8 var_len_off_mask, u8 shift_dir)
3193 {
3194 struct npc_kpu_action0 *act0;
3195 u8 shift_count = 0;
3196 int blkaddr;
3197 u64 val;
3198
3199 if (!var_len_off_mask)
3200 return -EINVAL;
3201
3202 if (var_len_off_mask != 0xff) {
3203 if (shift_dir)
3204 shift_count = __ffs(var_len_off_mask);
3205 else
3206 shift_count = (8 - __fls(var_len_off_mask));
3207 }
3208 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, pcifunc);
3209 if (blkaddr < 0) {
3210 dev_err(rvu->dev, "%s: NPC block not implemented\n", __func__);
3211 return -EINVAL;
3212 }
3213 val = rvu_read64(rvu, blkaddr, NPC_AF_PKINDX_ACTION0(pkind));
3214 act0 = (struct npc_kpu_action0 *)&val;
3215 act0->var_len_shift = shift_count;
3216 act0->var_len_right = shift_dir;
3217 act0->var_len_mask = var_len_off_mask;
3218 act0->var_len_offset = var_len_off;
3219 rvu_write64(rvu, blkaddr, NPC_AF_PKINDX_ACTION0(pkind), val);
3220 return 0;
3221 }
3222
rvu_npc_set_parse_mode(struct rvu * rvu,u16 pcifunc,u64 mode,u8 dir,u64 pkind,u8 var_len_off,u8 var_len_off_mask,u8 shift_dir)3223 int rvu_npc_set_parse_mode(struct rvu *rvu, u16 pcifunc, u64 mode, u8 dir,
3224 u64 pkind, u8 var_len_off, u8 var_len_off_mask,
3225 u8 shift_dir)
3226
3227 {
3228 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
3229 int blkaddr, nixlf, rc, intf_mode;
3230 int pf = rvu_get_pf(pcifunc);
3231 u64 rxpkind, txpkind;
3232 u8 cgx_id, lmac_id;
3233
3234 /* use default pkind to disable edsa/higig */
3235 rxpkind = rvu_npc_get_pkind(rvu, pf);
3236 txpkind = NPC_TX_DEF_PKIND;
3237 intf_mode = NPC_INTF_MODE_DEF;
3238
3239 if (mode & OTX2_PRIV_FLAGS_CUSTOM) {
3240 if (pkind == NPC_RX_CUSTOM_PRE_L2_PKIND) {
3241 rc = npc_set_var_len_offset_pkind(rvu, pcifunc, pkind,
3242 var_len_off,
3243 var_len_off_mask,
3244 shift_dir);
3245 if (rc)
3246 return rc;
3247 }
3248 rxpkind = pkind;
3249 txpkind = pkind;
3250 }
3251
3252 if (dir & PKIND_RX) {
3253 /* rx pkind set req valid only for cgx mapped PFs */
3254 if (!is_cgx_config_permitted(rvu, pcifunc))
3255 return 0;
3256 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
3257
3258 rc = cgx_set_pkind(rvu_cgx_pdata(cgx_id, rvu), lmac_id,
3259 rxpkind);
3260 if (rc)
3261 return rc;
3262 }
3263
3264 if (dir & PKIND_TX) {
3265 /* Tx pkind set request valid if PCIFUNC has NIXLF attached */
3266 rc = nix_get_nixlf(rvu, pcifunc, &nixlf, &blkaddr);
3267 if (rc)
3268 return rc;
3269
3270 rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_PARSE_CFG(nixlf),
3271 txpkind);
3272 }
3273
3274 pfvf->intf_mode = intf_mode;
3275 return 0;
3276 }
3277
rvu_mbox_handler_npc_set_pkind(struct rvu * rvu,struct npc_set_pkind * req,struct msg_rsp * rsp)3278 int rvu_mbox_handler_npc_set_pkind(struct rvu *rvu, struct npc_set_pkind *req,
3279 struct msg_rsp *rsp)
3280 {
3281 return rvu_npc_set_parse_mode(rvu, req->hdr.pcifunc, req->mode,
3282 req->dir, req->pkind, req->var_len_off,
3283 req->var_len_off_mask, req->shift_dir);
3284 }
3285
rvu_mbox_handler_npc_read_base_steer_rule(struct rvu * rvu,struct msg_req * req,struct npc_mcam_read_base_rule_rsp * rsp)3286 int rvu_mbox_handler_npc_read_base_steer_rule(struct rvu *rvu,
3287 struct msg_req *req,
3288 struct npc_mcam_read_base_rule_rsp *rsp)
3289 {
3290 struct npc_mcam *mcam = &rvu->hw->mcam;
3291 int index, blkaddr, nixlf, rc = 0;
3292 u16 pcifunc = req->hdr.pcifunc;
3293 struct rvu_pfvf *pfvf;
3294 u8 intf, enable;
3295
3296 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
3297 if (blkaddr < 0)
3298 return NPC_MCAM_INVALID_REQ;
3299
3300 /* Return the channel number in case of PF */
3301 if (!(pcifunc & RVU_PFVF_FUNC_MASK)) {
3302 pfvf = rvu_get_pfvf(rvu, pcifunc);
3303 rsp->entry.kw[0] = pfvf->rx_chan_base;
3304 rsp->entry.kw_mask[0] = 0xFFFULL;
3305 goto out;
3306 }
3307
3308 /* Find the pkt steering rule installed by PF to this VF */
3309 mutex_lock(&mcam->lock);
3310 for (index = 0; index < mcam->bmap_entries; index++) {
3311 if (mcam->entry2target_pffunc[index] == pcifunc)
3312 goto read_entry;
3313 }
3314
3315 rc = nix_get_nixlf(rvu, pcifunc, &nixlf, NULL);
3316 if (rc < 0) {
3317 mutex_unlock(&mcam->lock);
3318 goto out;
3319 }
3320 /* Read the default ucast entry if there is no pkt steering rule */
3321 index = npc_get_nixlf_mcam_index(mcam, pcifunc, nixlf,
3322 NIXLF_UCAST_ENTRY);
3323 read_entry:
3324 /* Read the mcam entry */
3325 npc_read_mcam_entry(rvu, mcam, blkaddr, index, &rsp->entry, &intf,
3326 &enable);
3327 mutex_unlock(&mcam->lock);
3328 out:
3329 return rc;
3330 }
3331
rvu_mbox_handler_npc_mcam_entry_stats(struct rvu * rvu,struct npc_mcam_get_stats_req * req,struct npc_mcam_get_stats_rsp * rsp)3332 int rvu_mbox_handler_npc_mcam_entry_stats(struct rvu *rvu,
3333 struct npc_mcam_get_stats_req *req,
3334 struct npc_mcam_get_stats_rsp *rsp)
3335 {
3336 struct npc_mcam *mcam = &rvu->hw->mcam;
3337 u16 index, cntr;
3338 int blkaddr;
3339 u64 regval;
3340 u32 bank;
3341
3342 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
3343 if (blkaddr < 0)
3344 return NPC_MCAM_INVALID_REQ;
3345
3346 mutex_lock(&mcam->lock);
3347
3348 index = req->entry & (mcam->banksize - 1);
3349 bank = npc_get_bank(mcam, req->entry);
3350
3351 /* read MCAM entry STAT_ACT register */
3352 regval = rvu_read64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_STAT_ACT(index, bank));
3353
3354 if (!(regval & rvu->hw->npc_stat_ena)) {
3355 rsp->stat_ena = 0;
3356 mutex_unlock(&mcam->lock);
3357 return 0;
3358 }
3359
3360 cntr = regval & 0x1FF;
3361
3362 rsp->stat_ena = 1;
3363 rsp->stat = rvu_read64(rvu, blkaddr, NPC_AF_MATCH_STATX(cntr));
3364 rsp->stat &= BIT_ULL(48) - 1;
3365
3366 mutex_unlock(&mcam->lock);
3367
3368 return 0;
3369 }
3370