/linux-5.19.10/drivers/mtd/nand/raw/ |
D | denali_dt.c | 28 struct reset_control *rst_reg; /* register reset */ member 165 dt->rst_reg = devm_reset_control_get_optional_shared(dev, "reg"); in denali_dt_probe() 166 if (IS_ERR(dt->rst_reg)) in denali_dt_probe() 167 return PTR_ERR(dt->rst_reg); in denali_dt_probe() 189 ret = reset_control_deassert(dt->rst_reg); in denali_dt_probe() 225 reset_control_assert(dt->rst_reg); in denali_dt_probe() 242 reset_control_assert(dt->rst_reg); in denali_dt_remove()
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/linux-5.19.10/drivers/clk/tegra/ |
D | clk.c | 45 .rst_reg = RST_DEVICES_L, 53 .rst_reg = RST_DEVICES_H, 61 .rst_reg = RST_DEVICES_U, 69 .rst_reg = RST_DEVICES_V, 77 .rst_reg = RST_DEVICES_W, 85 .rst_reg = RST_DEVICES_X, 93 .rst_reg = RST_DEVICES_Y, 188 readl_relaxed(clk_base + periph_regs[i].rst_reg); in tegra_clk_periph_suspend() 208 clk_base + periph_regs[i].rst_reg); in tegra_clk_periph_resume()
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D | clk-periph-fixed.c | 24 value = readl(fixed->base + fixed->regs->rst_reg); in tegra_clk_periph_fixed_is_enabled()
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D | clk-periph-gate.c | 27 readl_relaxed(gate->clk_base + (gate->regs->rst_reg))
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D | clk.h | 537 u32 rst_reg; member
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/linux-5.19.10/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
D | vegam_smumgr.c | 109 SMC_SYSCON_RESET_CNTL, rst_reg, 1); in vegam_start_smu_in_protection_mode() 123 SMC_SYSCON_RESET_CNTL, rst_reg, 0); in vegam_start_smu_in_protection_mode() 144 SMC_SYSCON_RESET_CNTL, rst_reg, 1); in vegam_start_smu_in_protection_mode() 147 SMC_SYSCON_RESET_CNTL, rst_reg, 0); in vegam_start_smu_in_protection_mode() 169 rst_reg, 1); in vegam_start_smu_in_non_protection_mode() 182 SMC_SYSCON_RESET_CNTL, rst_reg, 0); in vegam_start_smu_in_non_protection_mode()
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D | polaris10_smumgr.c | 209 SMC_SYSCON_RESET_CNTL, rst_reg, 1); in polaris10_start_smu_in_protection_mode() 223 SMC_SYSCON_RESET_CNTL, rst_reg, 0); in polaris10_start_smu_in_protection_mode() 244 SMC_SYSCON_RESET_CNTL, rst_reg, 1); in polaris10_start_smu_in_protection_mode() 247 SMC_SYSCON_RESET_CNTL, rst_reg, 0); in polaris10_start_smu_in_protection_mode() 269 rst_reg, 1); in polaris10_start_smu_in_non_protection_mode() 282 SMC_SYSCON_RESET_CNTL, rst_reg, 0); in polaris10_start_smu_in_non_protection_mode()
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D | fiji_smumgr.c | 108 SMC_SYSCON_RESET_CNTL, rst_reg, 1); in fiji_start_smu_in_protection_mode() 123 SMC_SYSCON_RESET_CNTL, rst_reg, 0); in fiji_start_smu_in_protection_mode() 174 SMC_SYSCON_RESET_CNTL, rst_reg, 1); in fiji_start_smu_in_non_protection_mode() 189 SMC_SYSCON_RESET_CNTL, rst_reg, 0); in fiji_start_smu_in_non_protection_mode()
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D | tonga_smumgr.c | 103 SMC_SYSCON_RESET_CNTL, rst_reg, 1); in tonga_start_in_protection_mode() 119 SMC_SYSCON_RESET_CNTL, rst_reg, 0); in tonga_start_in_protection_mode() 169 SMC_SYSCON_RESET_CNTL, rst_reg, 1); in tonga_start_in_non_protection_mode() 185 SMC_SYSCON_RESET_CNTL, rst_reg, 0); in tonga_start_in_non_protection_mode()
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D | ci_smumgr.c | 1904 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 0); in ci_start_smc() 2364 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 1); in ci_upload_firmware() 2945 rst_reg, 1); in ci_reset_smc()
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D | iceland_smumgr.c | 112 SMC_SYSCON_RESET_CNTL, rst_reg, 0); in iceland_start_smc() 121 rst_reg, 1); in iceland_reset_smc()
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/linux-5.19.10/drivers/net/ethernet/marvell/octeontx2/af/ |
D | rvu.c | 513 static void rvu_block_reset(struct rvu *rvu, int blkaddr, u64 rst_reg) in rvu_block_reset() argument 521 rvu_write64(rvu, blkaddr, rst_reg, BIT_ULL(0)); in rvu_block_reset() 522 err = rvu_poll_reg(rvu, blkaddr, rst_reg, BIT_ULL(63), true); in rvu_block_reset() 525 while (rvu_poll_reg(rvu, blkaddr, rst_reg, BIT_ULL(63), true) == -EBUSY) in rvu_block_reset()
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/linux-5.19.10/drivers/net/ethernet/qlogic/qed/ |
D | qed_debug.c | 1386 const struct dbg_reset_reg *rst_reg; in qed_update_blocks_reset_state() local 1390 rst_reg = qed_get_dbg_reset_reg(p_hwfn, rst_reg_id); in qed_update_blocks_reset_state() 1391 rst_reg_removed = GET_FIELD(rst_reg->data, in qed_update_blocks_reset_state() 1393 rst_reg_addr = DWORDS_TO_BYTES(GET_FIELD(rst_reg->data, in qed_update_blocks_reset_state()
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