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/linux-5.19.10/sound/soc/ux500/
Dux500_msp_i2s.c141 writel(temp_reg, msp->registers + MSP_TCF); in set_prot_desc_tx()
169 writel(temp_reg, msp->registers + MSP_RCF); in set_prot_desc_rx()
206 temp_reg = readl(msp->registers + MSP_GCR) & ~TX_CLK_POL_RISING; in configure_protocol()
208 writel(temp_reg, msp->registers + MSP_GCR); in configure_protocol()
209 temp_reg = readl(msp->registers + MSP_GCR) & ~RX_CLK_POL_RISING; in configure_protocol()
211 writel(temp_reg, msp->registers + MSP_GCR); in configure_protocol()
225 reg_val_GCR = readl(msp->registers + MSP_GCR); in setup_bitclk()
226 writel(reg_val_GCR & ~SRG_ENABLE, msp->registers + MSP_GCR); in setup_bitclk()
258 writel(temp_reg, msp->registers + MSP_SRG); in setup_bitclk()
264 reg_val_GCR = readl(msp->registers + MSP_GCR); in setup_bitclk()
[all …]
/linux-5.19.10/drivers/media/usb/cpia2/
Dcpia2_core.c247 cmd.buffer.registers[0].index = CPIA2_VC_ST_CTRL; in cpia2_do_command()
248 cmd.buffer.registers[0].value = CPIA2_VC_ST_CTRL_SRC_VC | in cpia2_do_command()
250 cmd.buffer.registers[1].index = CPIA2_VC_ST_CTRL; in cpia2_do_command()
251 cmd.buffer.registers[1].value = CPIA2_VC_ST_CTRL_SRC_VC | in cpia2_do_command()
260 cmd.buffer.registers[0].index = in cpia2_do_command()
262 cmd.buffer.registers[1].index = in cpia2_do_command()
264 cmd.buffer.registers[0].value = CPIA2_SYSTEM_CONTROL_CLEAR_ERR; in cpia2_do_command()
265 cmd.buffer.registers[1].value = in cpia2_do_command()
380 cmd.buffer.registers[0].index = CPIA2_VC_VC_TARGET_KB; in cpia2_do_command()
381 cmd.buffer.registers[0].value = param; in cpia2_do_command()
[all …]
/linux-5.19.10/drivers/media/radio/si470x/
Dradio-si470x-common.c185 radio->registers[SYSCONFIG2] &= ~SYSCONFIG2_BAND; in si470x_set_band()
186 radio->registers[SYSCONFIG2] |= radio->band << 6; in si470x_set_band()
203 if ((radio->registers[POWERCFG] & (POWERCFG_ENABLE|POWERCFG_DMUTE)) in si470x_set_chan()
209 radio->registers[CHANNEL] &= ~CHANNEL_CHAN; in si470x_set_chan()
210 radio->registers[CHANNEL] |= CHANNEL_TUNE | chan; in si470x_set_chan()
222 if ((radio->registers[STATUSRSSI] & STATUSRSSI_STC) == 0) in si470x_set_chan()
229 radio->registers[CHANNEL] &= ~CHANNEL_TUNE; in si470x_set_chan()
242 switch ((radio->registers[SYSCONFIG2] & SYSCONFIG2_SPACE) >> 4) { in si470x_get_step()
265 chan = radio->registers[READCHAN] & READCHAN_READCHAN; in si470x_get_freq()
327 radio->registers[POWERCFG] |= POWERCFG_SEEK; in si470x_set_seek()
[all …]
Dradio-si470x-i2c.c99 radio->registers[regnr] = __be16_to_cpu(buf[READ_INDEX(regnr)]); in si470x_get_register()
121 buf[i] = __cpu_to_be16(radio->registers[WRITE_INDEX(i)]); in si470x_set_register()
155 radio->registers[i] = __be16_to_cpu(buf[READ_INDEX(i)]); in si470x_get_all_registers()
184 radio->registers[SYSCONFIG1] |= SYSCONFIG1_RDSIEN; in si470x_fops_open()
185 radio->registers[SYSCONFIG1] |= SYSCONFIG1_STCIEN; in si470x_fops_open()
186 radio->registers[SYSCONFIG1] &= ~SYSCONFIG1_GPIO2; in si470x_fops_open()
187 radio->registers[SYSCONFIG1] |= 0x1 << 2; in si470x_fops_open()
253 if (radio->registers[STATUSRSSI] & STATUSRSSI_STC) in si470x_i2c_interrupt()
257 if ((radio->registers[SYSCONFIG1] & SYSCONFIG1_RDS) == 0) in si470x_i2c_interrupt()
268 if ((radio->registers[STATUSRSSI] & STATUSRSSI_RDSR) == 0) in si470x_i2c_interrupt()
[all …]
Dradio-si470x-usb.c253 radio->registers[regnr] = get_unaligned_be16(&radio->usb_buf[1]); in si470x_get_register()
267 put_unaligned_be16(radio->registers[regnr], &radio->usb_buf[1]); in si470x_set_register()
294 radio->registers[regnr] = get_unaligned_be16( in si470x_get_all_registers()
388 radio->registers[STATUSRSSI] = in si470x_int_in_callback()
391 if (radio->registers[STATUSRSSI] & STATUSRSSI_STC) in si470x_int_in_callback()
394 if ((radio->registers[SYSCONFIG1] & SYSCONFIG1_RDS)) { in si470x_int_in_callback()
397 radio->registers[STATUSRSSI + regnr] = in si470x_int_in_callback()
401 if ((radio->registers[STATUSRSSI] & STATUSRSSI_RDSR) == 0) { in si470x_int_in_callback()
405 if ((radio->registers[STATUSRSSI] & STATUSRSSI_RDSS) == 0) { in si470x_int_in_callback()
412 bler = (radio->registers[STATUSRSSI] & in si470x_int_in_callback()
[all …]
/linux-5.19.10/drivers/scsi/smartpqi/
Dsmartpqi_sis.c98 status = readl(&ctrl_info->registers->sis_firmware_status); in sis_wait_for_ctrl_ready_with_timeout()
104 &ctrl_info->registers->sis_mailbox[7])); in sis_wait_for_ctrl_ready_with_timeout()
139 status = readl(&ctrl_info->registers->sis_firmware_status); in sis_is_firmware_running()
149 readl(&ctrl_info->registers->sis_mailbox[7])); in sis_is_firmware_running()
156 return readl(&ctrl_info->registers->sis_firmware_status) & in sis_is_kernel_up()
162 return readl(&ctrl_info->registers->sis_product_identifier); in sis_get_product_id()
173 struct pqi_ctrl_registers __iomem *registers; in sis_send_sync_cmd() local
179 registers = ctrl_info->registers; in sis_send_sync_cmd()
182 writel(cmd, &registers->sis_mailbox[0]); in sis_send_sync_cmd()
189 writel(params->mailbox[i], &registers->sis_mailbox[i]); in sis_send_sync_cmd()
[all …]
/linux-5.19.10/Documentation/driver-api/media/drivers/ccs/
Dccs-regs.asc18 # general status registers
51 # frame format description registers
91 # analog gain description registers
110 # data format description registers
122 # general set-up registers
170 # integration time registers
174 # analog gain registers
179 # digital gain registers
182 # hdr control registers
203 # clock set-up registers
[all …]
/linux-5.19.10/Documentation/devicetree/bindings/pci/
Dsnps,dw-pcie-ep.yaml27 It should contain Data Bus Interface (dbi) and config registers for all
52 automatic checking of CDM (Configuration Dependent Module) registers
53 for data corruption. CDM registers include standard PCIe configuration
54 space registers, Port Logic registers, DMA and iATU (internal Address
55 Translation Unit) registers.
83 reg = <0xdfc00000 0x0001000>, /* IP registers 1 */
84 <0xdfc01000 0x0001000>, /* IP registers 2 */
Dsnps,dw-pcie.yaml27 It should contain Data Bus Interface (dbi) and config registers for all
65 automatic checking of CDM (Configuration Dependent Module) registers
66 for data corruption. CDM registers include standard PCIe configuration
67 space registers, Port Logic registers, DMA and iATU (internal Address
68 Translation Unit) registers.
93 reg = <0xdfc00000 0x0001000>, /* IP registers */
/linux-5.19.10/Documentation/devicetree/bindings/mips/
Dmscc.txt14 The SoC has a few registers (DEVCPU_GCB:CHIP_REGS) handling miscellaneous
20 - reg : Should contain registers location and length
31 The SoC has a few registers (ICPU_CFG:CPU_SYSTEM_CTRL) handling configuration of
32 the CPU: 8 general purpose registers, reset control, CPU en/disabling, CPU
37 - reg : Should contain registers location and length
47 The SoC has a few registers (HSIO) handling miscellaneous functionalities:
53 - reg : Should contain registers location and length
/linux-5.19.10/drivers/gpio/
Dgpio-74x164.c24 u32 registers; member
38 chip->registers); in __gen_74x164_write_config()
44 u8 bank = chip->registers - 1 - offset / 8; in gen_74x164_get_value()
59 u8 bank = chip->registers - 1 - offset / 8; in gen_74x164_set_value()
82 for_each_set_clump8(offset, bankmask, mask, chip->registers * 8) { in gen_74x164_set_multiple()
83 bank = chip->registers - 1 - offset / 8; in gen_74x164_set_multiple()
141 chip->registers = nregs; in gen_74x164_probe()
142 chip->gpio_chip.ngpio = GEN_74X164_NUMBER_GPIOS * chip->registers; in gen_74x164_probe()
/linux-5.19.10/drivers/char/agp/
Damd-k7-agp.c32 volatile u8 __iomem *registers; member
216 if (!amd_irongate_private.registers) { in amd_irongate_configure()
219 amd_irongate_private.registers = (volatile u8 __iomem *) ioremap(reg, 4096); in amd_irongate_configure()
220 if (!amd_irongate_private.registers) in amd_irongate_configure()
225 writel(agp_bridge->gatt_bus_addr, amd_irongate_private.registers+AMD_ATTBASE); in amd_irongate_configure()
226 readl(amd_irongate_private.registers+AMD_ATTBASE); /* PCI Posting. */ in amd_irongate_configure()
235 enable_reg = readw(amd_irongate_private.registers+AMD_GARTENABLE); in amd_irongate_configure()
237 writew(enable_reg, amd_irongate_private.registers+AMD_GARTENABLE); in amd_irongate_configure()
238 readw(amd_irongate_private.registers+AMD_GARTENABLE); /* PCI Posting. */ in amd_irongate_configure()
246 writel(1, amd_irongate_private.registers+AMD_TLBFLUSH); in amd_irongate_configure()
[all …]
Dsworks-agp.c39 volatile u8 __iomem *registers; member
240 writeb(1, serverworks_private.registers+SVWRKS_POSTFLUSH); in serverworks_tlbflush()
242 while (readb(serverworks_private.registers+SVWRKS_POSTFLUSH) == 1) { in serverworks_tlbflush()
251 writel(1, serverworks_private.registers+SVWRKS_DIRFLUSH); in serverworks_tlbflush()
253 while (readl(serverworks_private.registers+SVWRKS_DIRFLUSH) == 1) { in serverworks_tlbflush()
272 serverworks_private.registers = (volatile u8 __iomem *) ioremap(temp, 4096); in serverworks_configure()
273 if (!serverworks_private.registers) { in serverworks_configure()
278 writeb(0xA, serverworks_private.registers+SVWRKS_GART_CACHE); in serverworks_configure()
279 readb(serverworks_private.registers+SVWRKS_GART_CACHE); /* PCI Posting. */ in serverworks_configure()
281 writel(agp_bridge->gatt_bus_addr, serverworks_private.registers+SVWRKS_GATTBASE); in serverworks_configure()
[all …]
Dintel-gtt.c67 u8 __iomem *registers; member
187 intel_private.registers = ioremap(reg_addr, KB(64)); in i810_setup()
188 if (!intel_private.registers) in i810_setup()
192 intel_private.registers+I810_PGETBL_CTL); in i810_setup()
196 if ((readl(intel_private.registers+I810_DRAM_CTL) in i810_setup()
208 writel(0, intel_private.registers+I810_PGETBL_CTL); in i810_cleanup()
366 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); in intel_gtt_stolen_size()
439 pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2); in i965_adjust_pgetbl_size()
441 writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2); in i965_adjust_pgetbl_size()
444 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); in i965_adjust_pgetbl_size()
[all …]
/linux-5.19.10/Documentation/devicetree/bindings/thermal/
Drcar-gen3-thermal.yaml71 - description: TSC1 registers
72 - description: TSC2 registers
73 - description: TSC3 registers
80 - description: TSC0 registers
81 - description: TSC1 registers
82 - description: TSC2 registers
83 - description: TSC3 registers
84 - description: TSC4 registers
/linux-5.19.10/Documentation/devicetree/bindings/powerpc/nintendo/
Dwii.txt31 - reg : should contain the VI registers location and length
42 - reg : should contain the PI registers location and length
64 - reg : should contain the DSP registers location and length
76 - reg : should contain the SI registers location and length
87 - reg : should contain the AI registers location and length
97 - reg : should contain the EXI registers location and length
107 - reg : should contain the OHCI registers location and length
117 - reg : should contain the EHCI registers location and length
127 - reg : should contain the SDHCI registers location and length
136 - reg : should contain the IPC registers location and length
[all …]
/linux-5.19.10/Documentation/devicetree/bindings/spmi/
Dqcom,spmi-pmic-arb.yaml30 - description: core registers
31 - description: interrupt controller registers
32 - description: configuration registers
34 - description: core registers
36 - description: rx-channel (called observer) per virtual slave registers
37 - description: interrupt controller registers
38 - description: configuration registers
/linux-5.19.10/Documentation/sh/
Dregister-banks.rst17 In the case of this type of banking, banked registers are mapped directly to
19 can still be used to reference the banked registers (as r0_bank ... r7_bank)
21 in mind when writing code that utilizes these banked registers, for obvious
23 be used rather effectively as scratch registers by the kernel.
25 Presently the kernel uses several of these registers.
28 registers when doing exception handling).
/linux-5.19.10/drivers/gpu/drm/msm/adreno/
Da6xx_gpu_state.c22 struct a6xx_gpu_state_obj *registers; member
472 int count = RANGE(dbgahb->registers, j); in a6xx_get_dbgahb_cluster()
474 dbgahb->registers[j] - (dbgahb->base >> 2); in a6xx_get_dbgahb_cluster()
544 int count = RANGE(cluster->registers, j); in a6xx_get_cluster()
546 in += CRASHDUMP_READ(in, cluster->registers[j], in a6xx_get_cluster()
656 u32 count = RANGE(regs->registers, i); in a6xx_get_crashdumper_hlsq_registers()
658 regs->registers[i] - (regs->val0 >> 2); in a6xx_get_crashdumper_hlsq_registers()
696 u32 count = RANGE(regs->registers, i); in a6xx_get_crashdumper_registers()
698 in += CRASHDUMP_READ(in, regs->registers[i], count, out); in a6xx_get_crashdumper_registers()
726 regcount += RANGE(regs->registers, i); in a6xx_get_ahb_gpu_registers()
[all …]
/linux-5.19.10/Documentation/devicetree/bindings/i2c/
Dmellanox,i2c-mlxbf.yaml24 - description: Smbus block registers
25 - description: Cause master registers
26 - description: Cause slave registers
27 - description: Cause coalesce registers
35 bus frequency used to configure timing registers;
/linux-5.19.10/Documentation/devicetree/bindings/arm/marvell/
Dcoherency-fabric.txt18 - reg: Should contain coherency fabric registers location and
22 fabric registers, second pair for the per-CPU fabric registers.
25 for the per-CPU fabric registers.
28 for the per-CPU fabric registers.
/linux-5.19.10/Documentation/devicetree/bindings/powerpc/4xx/
Dppc440spe-adma.txt16 - reg : <registers mapping>
17 - dcr-reg : <DCR registers range>
35 - reg : <registers mapping>
36 - dcr-reg : <DCR registers range>
65 - reg : <registers mapping>
83 - dcr-reg : <DCR registers range>
/linux-5.19.10/Documentation/devicetree/bindings/interrupt-controller/
Dmarvell,armada-370-xp-mpic.txt12 - reg: Should contain PMIC registers location and length. First pair
13 for the main interrupt registers, second pair for the per-CPU
14 interrupt registers. For this last pair, to be compliant with SMP
15 support, the "virtual" must be use (For the record, these registers
16 automatically map to the interrupt controller registers of the
/linux-5.19.10/Documentation/driver-api/media/drivers/
Dcpia2_devel.rst35 The cameras appear externally as three sets of registers. Setting register
42 registers that control housekeeping functions such as powering up the video
43 processor. The video processor is the VP block. These registers control
44 how the video from the sensor is processed. Examples are timing registers,
49 of these registers and the possible values for most of them.
51 One or more registers can be set or read by sending a usb control message to
53 of contiguous registers. Random mode reads or writes random registers with
/linux-5.19.10/Documentation/devicetree/bindings/phy/
Dintel,combo-phy.yaml30 - description: ComboPhy core registers
31 - description: PCIe app core control registers
52 - description: phandle to Chip configuration registers
54 description: Chip configuration registers handle and ComboPhy instance id
60 - description: phandle to HSIO registers
62 description: HSIO registers handle and ComboPhy instance id on NOC

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