Searched refs:reg_access_ctrl (Results 1 – 5 of 5) sorted by relevance
/linux-5.19.10/drivers/gpu/drm/amd/amdgpu/ |
D | amdgpu_virt.c | 871 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; in amdgpu_virt_rlcg_reg_rw() local 887 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl; in amdgpu_virt_rlcg_reg_rw() 888 scratch_reg0 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg0; in amdgpu_virt_rlcg_reg_rw() 889 scratch_reg1 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg1; in amdgpu_virt_rlcg_reg_rw() 890 scratch_reg2 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg2; in amdgpu_virt_rlcg_reg_rw() 891 scratch_reg3 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg3; in amdgpu_virt_rlcg_reg_rw() 892 if (reg_access_ctrl->spare_int) in amdgpu_virt_rlcg_reg_rw() 893 spare_int = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->spare_int; in amdgpu_virt_rlcg_reg_rw() 895 if (offset == reg_access_ctrl->grbm_cntl) { in amdgpu_virt_rlcg_reg_rw() 899 } else if (offset == reg_access_ctrl->grbm_idx) { in amdgpu_virt_rlcg_reg_rw() [all …]
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D | amdgpu_rlc.h | 250 struct amdgpu_rlcg_reg_access_ctrl reg_access_ctrl; member
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D | gfx_v11_0.c | 964 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; in gfx_v11_0_init_rlcg_reg_access_ctrl() local 966 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl; in gfx_v11_0_init_rlcg_reg_access_ctrl() 967 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); in gfx_v11_0_init_rlcg_reg_access_ctrl() 968 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); in gfx_v11_0_init_rlcg_reg_access_ctrl() 969 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); in gfx_v11_0_init_rlcg_reg_access_ctrl() 970 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); in gfx_v11_0_init_rlcg_reg_access_ctrl() 971 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); in gfx_v11_0_init_rlcg_reg_access_ctrl() 972 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); in gfx_v11_0_init_rlcg_reg_access_ctrl() 973 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); in gfx_v11_0_init_rlcg_reg_access_ctrl()
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D | gfx_v9_0.c | 1871 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; in gfx_v9_0_init_rlcg_reg_access_ctrl() local 1873 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl; in gfx_v9_0_init_rlcg_reg_access_ctrl() 1874 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); in gfx_v9_0_init_rlcg_reg_access_ctrl() 1875 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1); in gfx_v9_0_init_rlcg_reg_access_ctrl() 1876 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2); in gfx_v9_0_init_rlcg_reg_access_ctrl() 1877 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3); in gfx_v9_0_init_rlcg_reg_access_ctrl() 1878 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL); in gfx_v9_0_init_rlcg_reg_access_ctrl() 1879 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX); in gfx_v9_0_init_rlcg_reg_access_ctrl() 1880 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT); in gfx_v9_0_init_rlcg_reg_access_ctrl()
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D | gfx_v10_0.c | 4408 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; in gfx_v10_0_init_rlcg_reg_access_ctrl() local 4410 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl; in gfx_v10_0_init_rlcg_reg_access_ctrl() 4411 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); in gfx_v10_0_init_rlcg_reg_access_ctrl() 4412 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1); in gfx_v10_0_init_rlcg_reg_access_ctrl() 4413 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2); in gfx_v10_0_init_rlcg_reg_access_ctrl() 4414 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3); in gfx_v10_0_init_rlcg_reg_access_ctrl() 4415 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL); in gfx_v10_0_init_rlcg_reg_access_ctrl() 4416 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX); in gfx_v10_0_init_rlcg_reg_access_ctrl() 4419 reg_access_ctrl->spare_int = in gfx_v10_0_init_rlcg_reg_access_ctrl() 4423 reg_access_ctrl->spare_int = in gfx_v10_0_init_rlcg_reg_access_ctrl()
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