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Searched refs:regPWRSEQ1_PANEL_PWRSEQ_CNTL (Results 1 – 6 of 6) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/dpcs/
Ddpcs_4_2_0_offset.h110 #define regPWRSEQ1_PANEL_PWRSEQ_CNTL … macro
Ddpcs_4_2_2_offset.h97 #define regPWRSEQ1_PANEL_PWRSEQ_CNTL … macro
Ddpcs_4_2_3_offset.h114 #define regPWRSEQ1_PANEL_PWRSEQ_CNTL … macro
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_1_2_offset.h12445 #define regPWRSEQ1_PANEL_PWRSEQ_CNTL … macro
Ddcn_3_1_5_offset.h12310 #define regPWRSEQ1_PANEL_PWRSEQ_CNTL … macro
Ddcn_3_1_6_offset.h13041 #define regPWRSEQ1_PANEL_PWRSEQ_CNTL … macro