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Searched refs:regPWRSEQ1_BL_PWM_CNTL2_BASE_IDX (Results 1 – 6 of 6) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/dpcs/
Ddpcs_4_2_0_offset.h123 #define regPWRSEQ1_BL_PWM_CNTL2_BASE_IDX … macro
Ddpcs_4_2_2_offset.h110 #define regPWRSEQ1_BL_PWM_CNTL2_BASE_IDX … macro
Ddpcs_4_2_3_offset.h127 #define regPWRSEQ1_BL_PWM_CNTL2_BASE_IDX … macro
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_1_2_offset.h12458 #define regPWRSEQ1_BL_PWM_CNTL2_BASE_IDX … macro
Ddcn_3_1_5_offset.h12323 #define regPWRSEQ1_BL_PWM_CNTL2_BASE_IDX … macro
Ddcn_3_1_6_offset.h13054 #define regPWRSEQ1_BL_PWM_CNTL2_BASE_IDX … macro