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Searched refs:regDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX (Results 1 – 3 of 3) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_1_2_offset.h394 #define regDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX … macro
Ddcn_3_1_5_offset.h181 #define regDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX … macro
Ddcn_3_1_6_offset.h594 #define regDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX … macro