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/linux-5.19.10/arch/nios2/include/asm/
Dasm-macros.h19 .macro ANDI32 reg1, reg2, mask
22 movhi \reg1, %hi(\mask)
23 movui \reg1, %lo(\mask)
24 and \reg1, \reg1, \reg2
26 andi \reg1, \reg2, %lo(\mask)
29 andhi \reg1, \reg2, %hi(\mask)
39 .macro ORI32 reg1, reg2, mask
42 orhi \reg1, \reg2, %hi(\mask)
43 ori \reg1, \reg2, %lo(\mask)
45 ori \reg1, \reg2, %lo(\mask)
[all …]
/linux-5.19.10/arch/arm64/include/asm/
Dkvm_ptrauth.h26 .macro ptrauth_save_state base, reg1, reg2
27 mrs_s \reg1, SYS_APIAKEYLO_EL1
29 stp \reg1, \reg2, [\base, #PTRAUTH_REG_OFFSET(CPU_APIAKEYLO_EL1)]
30 mrs_s \reg1, SYS_APIBKEYLO_EL1
32 stp \reg1, \reg2, [\base, #PTRAUTH_REG_OFFSET(CPU_APIBKEYLO_EL1)]
33 mrs_s \reg1, SYS_APDAKEYLO_EL1
35 stp \reg1, \reg2, [\base, #PTRAUTH_REG_OFFSET(CPU_APDAKEYLO_EL1)]
36 mrs_s \reg1, SYS_APDBKEYLO_EL1
38 stp \reg1, \reg2, [\base, #PTRAUTH_REG_OFFSET(CPU_APDBKEYLO_EL1)]
39 mrs_s \reg1, SYS_APGAKEYLO_EL1
[all …]
Dkvm_mte.h14 .macro mte_switch_to_guest g_ctxt, h_ctxt, reg1
18 mrs \reg1, hcr_el2
19 tbz \reg1, #(HCR_ATA_SHIFT), .L__skip_switch\@
21 mrs_s \reg1, SYS_RGSR_EL1
22 str \reg1, [\h_ctxt, #CPU_RGSR_EL1]
23 mrs_s \reg1, SYS_GCR_EL1
24 str \reg1, [\h_ctxt, #CPU_GCR_EL1]
26 ldr \reg1, [\g_ctxt, #CPU_RGSR_EL1]
27 msr_s SYS_RGSR_EL1, \reg1
28 ldr \reg1, [\g_ctxt, #CPU_GCR_EL1]
[all …]
/linux-5.19.10/arch/s390/include/asm/
Dap.h60 unsigned long reg1 = 0; in ap_instructions_available() local
70 : [reg1] "+&d" (reg1) in ap_instructions_available()
73 return reg1 != 0; in ap_instructions_available()
85 struct ap_queue_status reg1; in ap_tapq() local
94 : [reg1] "=&d" (reg1), [reg2] "=&d" (reg2) in ap_tapq()
99 return reg1; in ap_tapq()
128 struct ap_queue_status reg1; in ap_rapq() local
134 : [reg1] "=&d" (reg1) in ap_rapq()
137 return reg1; in ap_rapq()
149 struct ap_queue_status reg1; in ap_zapq() local
[all …]
/linux-5.19.10/arch/arm/probes/kprobes/
Dtest-core.h239 #define TEST_RR(code1, reg1, val1, code2, reg2, val2, code3) \ argument
240 TESTCASE_START(code1 #reg1 code2 #reg2 code3) \
241 TEST_ARG_REG(reg1, val1) \
244 TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3) \
247 #define TEST_RRR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4)\ argument
248 TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4) \
249 TEST_ARG_REG(reg1, val1) \
253 TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3 #reg3 code4) \
256 #define TEST_RRRR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4, reg4, val4) \ argument
257 TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4 #reg4) \
[all …]
/linux-5.19.10/arch/x86/events/intel/
Duncore_nhmex.c353 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; in nhmex_bbox_hw_config() local
368 reg1->reg = NHMEX_B0_MSR_MATCH; in nhmex_bbox_hw_config()
370 reg1->reg = NHMEX_B1_MSR_MATCH; in nhmex_bbox_hw_config()
371 reg1->idx = 0; in nhmex_bbox_hw_config()
372 reg1->config = event->attr.config1; in nhmex_bbox_hw_config()
380 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; in nhmex_bbox_msr_enable_event() local
383 if (reg1->idx != EXTRA_REG_NONE) { in nhmex_bbox_msr_enable_event()
384 wrmsrl(reg1->reg, reg1->config); in nhmex_bbox_msr_enable_event()
385 wrmsrl(reg1->reg + 1, reg2->config); in nhmex_bbox_msr_enable_event()
444 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; in nhmex_sbox_hw_config() local
[all …]
Duncore_snbep.c638 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; in snbep_uncore_msr_enable_event() local
640 if (reg1->idx != EXTRA_REG_NONE) in snbep_uncore_msr_enable_event()
641 wrmsrl(reg1->reg, uncore_shared_reg_config(box, 0)); in snbep_uncore_msr_enable_event()
929 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; in snbep_cbox_put_constraint() local
937 if (reg1->alloc & (0x1 << i)) in snbep_cbox_put_constraint()
940 reg1->alloc = 0; in snbep_cbox_put_constraint()
947 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; in __snbep_cbox_get_constraint() local
953 if (reg1->idx == EXTRA_REG_NONE) in __snbep_cbox_get_constraint()
958 if (!(reg1->idx & (0x1 << i))) in __snbep_cbox_get_constraint()
960 if (!uncore_box_is_fake(box) && (reg1->alloc & (0x1 << i))) in __snbep_cbox_get_constraint()
[all …]
/linux-5.19.10/arch/arm/kernel/
Dhyp-stub.S29 .macro store_primary_cpu_mode reg1, reg2
30 mrs \reg1, cpsr
31 and \reg1, \reg1, #MODE_MASK
32 str_l \reg1, __boot_cpu_mode, \reg2
41 .macro compare_cpu_mode_with_primary mode, reg1, reg2
43 ldr \reg1, [\reg2]
44 cmp \mode, \reg1 @ matches primary CPU boot mode?
45 orrne \reg1, \reg1, #BOOT_CPU_MODE_MISMATCH
46 strne \reg1, [\reg2] @ record what happened and give up
51 .macro store_primary_cpu_mode reg1:req, reg2:req
[all …]
/linux-5.19.10/arch/arm/lib/
Dcsumpartialcopy.S25 .macro load1b, reg1 argument
26 ldrb \reg1, [r0], #1
29 .macro load2b, reg1, reg2
30 ldrb \reg1, [r0], #1
34 .macro load1l, reg1 argument
35 ldr \reg1, [r0], #4
38 .macro load2l, reg1, reg2
39 ldr \reg1, [r0], #4
43 .macro load4l, reg1, reg2, reg3, reg4
44 ldmia r0!, {\reg1, \reg2, \reg3, \reg4}
Dcsumpartialcopyuser.S38 .macro load1b, reg1 argument
39 ldrusr \reg1, r0, 1
42 .macro load2b, reg1, reg2
43 ldrusr \reg1, r0, 1
47 .macro load1l, reg1 argument
48 ldrusr \reg1, r0, 4
51 .macro load2l, reg1, reg2
52 ldrusr \reg1, r0, 4
56 .macro load4l, reg1, reg2, reg3, reg4
57 ldrusr \reg1, r0, 4
Dcopy_from_user.S46 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
47 ldr1w \ptr, \reg1, \abort
53 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
54 ldr4w \ptr, \reg1, \reg2, \reg3, \reg4, \abort
66 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
67 USERL(\abort, ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4})
70 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
71 USERL(\abort, ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8})
86 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
87 stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
Dcopy_to_user.S40 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
41 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
44 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
45 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
64 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
65 str1w \ptr, \reg1, \abort
83 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
84 USERL(\abort, stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8})
Dmemcpy.S21 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
22 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
25 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
26 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
37 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
38 stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
/linux-5.19.10/sound/pci/ice1712/
Dwm8776.c137 .reg1 = WM8776_REG_DACLVOL,
147 .reg1 = WM8776_REG_DACCTRL1,
156 .reg1 = WM8776_REG_DACCTRL1,
163 .reg1 = WM8776_REG_HPLVOL,
174 .reg1 = WM8776_REG_PWRDOWN,
181 .reg1 = WM8776_REG_HPLVOL,
190 .reg1 = WM8776_REG_OUTMUX,
196 .reg1 = WM8776_REG_OUTMUX,
202 .reg1 = WM8776_REG_DACCTRL1,
208 .reg1 = WM8776_REG_PHASESWAP,
[all …]
Dwm8766.c34 .reg1 = WM8766_REG_DACL1,
45 .reg1 = WM8766_REG_DACL2,
56 .reg1 = WM8766_REG_DACL3,
66 .reg1 = WM8766_REG_DACCTRL2,
73 .reg1 = WM8766_REG_DACCTRL2,
80 .reg1 = WM8766_REG_DACCTRL2,
87 .reg1 = WM8766_REG_IFCTRL,
93 .reg1 = WM8766_REG_IFCTRL,
99 .reg1 = WM8766_REG_IFCTRL,
105 .reg1 = WM8766_REG_DACCTRL2,
[all …]
/linux-5.19.10/arch/arm64/crypto/
Daes-cipher-core.S20 .macro __pair1, sz, op, reg0, reg1, in0, in1e, in1d, shift
23 ubfiz \reg1, \in1e, #2, #8
26 ubfx \reg1, \in1e, #\shift, #8
38 ldr \reg1, [tt, \reg1, uxtw #2]
42 lsl \reg1, \reg1, #2
45 ldrb \reg1, [tt, \reg1, uxtw]
49 .macro __pair0, sz, op, reg0, reg1, in0, in1e, in1d, shift
51 ubfx \reg1, \in1d, #\shift, #8
53 ldr\op \reg1, [tt, \reg1, uxtw #\sz]
/linux-5.19.10/drivers/rtc/
Drtc-aspeed.c26 u32 reg1, reg2; in aspeed_rtc_read_time() local
35 reg1 = readl(rtc->base + RTC_TIME); in aspeed_rtc_read_time()
38 tm->tm_mday = (reg1 >> 24) & 0x1f; in aspeed_rtc_read_time()
39 tm->tm_hour = (reg1 >> 16) & 0x1f; in aspeed_rtc_read_time()
40 tm->tm_min = (reg1 >> 8) & 0x3f; in aspeed_rtc_read_time()
41 tm->tm_sec = (reg1 >> 0) & 0x3f; in aspeed_rtc_read_time()
56 u32 reg1, reg2, ctrl; in aspeed_rtc_set_time() local
62 reg1 = (tm->tm_mday << 24) | (tm->tm_hour << 16) | (tm->tm_min << 8) | in aspeed_rtc_set_time()
71 writel(reg1, rtc->base + RTC_TIME); in aspeed_rtc_set_time()
/linux-5.19.10/drivers/media/dvb-frontends/
Dtua6100.c64 u8 reg1[] = { 0x01, 0x00, 0x00, 0x00 }; in tua6100_set_params() local
67 struct i2c_msg msg1 = { .addr = priv->i2c_address, .flags = 0, .buf = reg1, .len = 4 }; in tua6100_set_params()
82 reg1[1] = 0x2c; in tua6100_set_params()
84 reg1[1] = 0x0c; in tua6100_set_params()
87 reg1[1] |= 0x40; in tua6100_set_params()
89 reg1[1] |= 0x80; in tua6100_set_params()
107 reg1[1] |= (div >> 9) & 0x03; in tua6100_set_params()
108 reg1[2] = div >> 1; in tua6100_set_params()
109 reg1[3] = (div << 7); in tua6100_set_params()
113 reg1[3] |= (prediv - (div*_P_VAL)) & 0x7f; in tua6100_set_params()
Da8293.c21 u8 reg0, reg1; in a8293_set_voltage() local
50 reg1 = 0x82; in a8293_set_voltage()
51 if (reg1 != dev->reg[1]) { in a8293_set_voltage()
52 ret = i2c_master_send(client, &reg1, 1); in a8293_set_voltage()
55 dev->reg[1] = reg1; in a8293_set_voltage()
/linux-5.19.10/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dnv04.c49 nv04_clk_pll_prog(struct nvkm_clk *clk, u32 reg1, struct nvkm_pll_vals *pv) in nv04_clk_pll_prog() argument
57 if (reg1 > 0x405c) in nv04_clk_pll_prog()
58 setPLL_double_highregs(devinit, reg1, pv); in nv04_clk_pll_prog()
60 setPLL_double_lowregs(devinit, reg1, pv); in nv04_clk_pll_prog()
62 setPLL_single(devinit, reg1, pv); in nv04_clk_pll_prog()
/linux-5.19.10/arch/s390/kvm/
Dpriv.c261 int reg1, reg2; in handle_iske() local
274 kvm_s390_get_regs_rre(vcpu, &reg1, &reg2); in handle_iske()
300 vcpu->run->s.regs.gprs[reg1] &= ~0xff; in handle_iske()
301 vcpu->run->s.regs.gprs[reg1] |= key; in handle_iske()
308 int reg1, reg2; in handle_rrbe() local
321 kvm_s390_get_regs_rre(vcpu, &reg1, &reg2); in handle_rrbe()
359 int reg1, reg2; in handle_sske() local
379 kvm_s390_get_regs_rre(vcpu, &reg1, &reg2); in handle_sske()
381 key = vcpu->run->s.regs.gprs[reg1] & 0xfe; in handle_sske()
425 vcpu->run->s.regs.gprs[reg1] &= ~0xff00UL; in handle_sske()
[all …]
Dtrace.h287 TP_PROTO(VCPU_PROTO_COMMON, int g, int reg1, int reg3, u64 addr),
288 TP_ARGS(VCPU_ARGS_COMMON, g, reg1, reg3, addr),
293 __field(int, reg1)
301 __entry->reg1 = reg1;
308 __entry->reg1, __entry->reg3, __entry->addr)
312 TP_PROTO(VCPU_PROTO_COMMON, int g, int reg1, int reg3, u64 addr),
313 TP_ARGS(VCPU_ARGS_COMMON, g, reg1, reg3, addr),
318 __field(int, reg1)
326 __entry->reg1 = reg1;
333 __entry->reg1, __entry->reg3, __entry->addr)
/linux-5.19.10/arch/s390/boot/
Dmem_detect.c69 unsigned long reg1, reg2, ry; in __diag260() local
89 : [reg1] "=&d" (reg1), in __diag260()
123 unsigned long reg1, reg2; in tprot() local
138 : [reg1] "=&d" (reg1), in tprot()
/linux-5.19.10/drivers/mcb/
Dmcb-parse.c47 __le32 reg1; in chameleon_parse_gdd() local
54 reg1 = readl(&gdd->reg1); in chameleon_parse_gdd()
59 mdev->id = GDD_DEV(reg1); in chameleon_parse_gdd()
60 mdev->rev = GDD_REV(reg1); in chameleon_parse_gdd()
61 mdev->var = GDD_VAR(reg1); in chameleon_parse_gdd()
93 mdev->irq.start = GDD_IRQ(reg1); in chameleon_parse_gdd()
94 mdev->irq.end = GDD_IRQ(reg1); in chameleon_parse_gdd()
/linux-5.19.10/drivers/gpu/drm/amd/display/dc/irq/dcn21/
Dirq_service_dcn21.c215 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
216 .enable_reg = SRI(reg1, block, reg_num),\
218 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
220 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
221 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
229 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
230 .enable_reg = SRI_DMUB(reg1),\
232 reg1 ## __ ## mask1 ## _MASK,\
234 reg1 ## __ ## mask1 ## _MASK,\
235 ~reg1 ## __ ## mask1 ## _MASK \

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