Searched refs:ref_and_mask_cp0 (Results 1 – 11 of 11) sorted by relevance
30 u32 ref_and_mask_cp0; member
195 .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,
260 .ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK,
318 .ref_and_mask_cp0 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP0_MASK,
249 .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,
355 .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,
317 .ref_and_mask_cp0 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP0_MASK,
328 .ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK,
5366 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; in gfx_v11_0_ring_emit_hdp_flush()
5301 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; in gfx_v9_0_ring_emit_hdp_flush()
8571 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; in gfx_v10_0_ring_emit_hdp_flush()