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Searched refs:rFPGA0_TxGainStage (Results 1 – 10 of 10) sorted by relevance

/linux-5.19.10/drivers/staging/rtl8723bs/hal/
Dodm_NoiseMonitor.c58 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_TxGainStage, BIT25, 1); in odm_InbandNoise_Monitor_NSeries()
68 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_TxGainStage, BIT25, 0); in odm_InbandNoise_Monitor_NSeries()
/linux-5.19.10/drivers/staging/rtl8192u/
Dr819xU_phyreg.h9 #define rFPGA0_TxGainStage 0x80c macro
Dr819xU_phy.c601 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; in rtl8192_InitBBRFRegDef()
602 priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; in rtl8192_InitBBRFRegDef()
603 priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; in rtl8192_InitBBRFRegDef()
604 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; in rtl8192_InitBBRFRegDef()
803 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC), in rtl8192_BB_Config_ParaFile()
/linux-5.19.10/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_phy.c412 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; in _rtl92e_init_bb_rf_reg_def()
413 priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; in _rtl92e_init_bb_rf_reg_def()
414 priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; in _rtl92e_init_bb_rf_reg_def()
415 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; in _rtl92e_init_bb_rf_reg_def()
567 rtl92e_set_bb_reg(dev, rFPGA0_TxGainStage, in _rtl92e_bb_config_para_file()
650 rtl92e_set_bb_reg(dev, rFPGA0_TxGainStage, in rtl92e_set_tx_power()
Dr8192E_phyreg.h50 #define rFPGA0_TxGainStage 0x80c macro
/linux-5.19.10/drivers/staging/r8188eu/hal/
Drtl8188e_phycfg.c387 pHalData->PHYRegDef.rfTxGainStage = rFPGA0_TxGainStage; /* Tx gain stage */ in phy_InitBBRFRegisterDefinition()
/linux-5.19.10/drivers/staging/rtl8712/
Drtl871x_mp_phy_regdef.h89 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ macro
Drtl871x_mp.c319 set_bb_reg(pAdapter, rFPGA0_TxGainStage, in r8712_SetTxAGCOffset()
/linux-5.19.10/drivers/staging/r8188eu/include/
DHal8188EPhyReg.h59 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ macro
/linux-5.19.10/drivers/staging/rtl8723bs/include/
DHal8192CPhyReg.h97 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ macro