1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2007 - 2011 Realtek Corporation. */ 3 4 #ifndef __INC_HAL8188EPHYREG_H__ 5 #define __INC_HAL8188EPHYREG_H__ 6 /*--------------------------Define Parameters-------------------------------*/ 7 /* */ 8 /* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */ 9 /* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF */ 10 /* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */ 11 /* 3. RF register 0x00-2E */ 12 /* 4. Bit Mask for BB/RF register */ 13 /* 5. Other definition for BB/RF R/W */ 14 /* */ 15 16 /* */ 17 /* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF */ 18 /* 1. Page1(0x100) */ 19 /* */ 20 #define rPMAC_Reset 0x100 21 #define rPMAC_TxStart 0x104 22 #define rPMAC_TxLegacySIG 0x108 23 #define rPMAC_TxHTSIG1 0x10c 24 #define rPMAC_TxHTSIG2 0x110 25 #define rPMAC_PHYDebug 0x114 26 #define rPMAC_TxPacketNum 0x118 27 #define rPMAC_TxIdle 0x11c 28 #define rPMAC_TxMACHeader0 0x120 29 #define rPMAC_TxMACHeader1 0x124 30 #define rPMAC_TxMACHeader2 0x128 31 #define rPMAC_TxMACHeader3 0x12c 32 #define rPMAC_TxMACHeader4 0x130 33 #define rPMAC_TxMACHeader5 0x134 34 #define rPMAC_TxDataType 0x138 35 #define rPMAC_TxRandomSeed 0x13c 36 #define rPMAC_CCKPLCPPreamble 0x140 37 #define rPMAC_CCKPLCPHeader 0x144 38 #define rPMAC_CCKCRC16 0x148 39 #define rPMAC_OFDMRxCRC32OK 0x170 40 #define rPMAC_OFDMRxCRC32Er 0x174 41 #define rPMAC_OFDMRxParityEr 0x178 42 #define rPMAC_OFDMRxCRC8Er 0x17c 43 #define rPMAC_CCKCRxRC16Er 0x180 44 #define rPMAC_CCKCRxRC32Er 0x184 45 #define rPMAC_CCKCRxRC32OK 0x188 46 #define rPMAC_TxStatus 0x18c 47 48 /* 2. Page2(0x200) */ 49 /* The following two definition are only used for USB interface. */ 50 #define RF_BB_CMD_ADDR 0x02c0 /* RF/BB r/w cmd address. */ 51 #define RF_BB_CMD_DATA 0x02c4 /* RF/BB r/w cmd data. */ 52 53 /* 3. Page8(0x800) */ 54 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC RF BW Setting */ 55 56 #define rFPGA0_TxInfo 0x804 /* Status report?? */ 57 #define rFPGA0_PSDFunction 0x808 58 59 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ 60 61 #define rFPGA0_RFTiming1 0x810 /* Useless now */ 62 #define rFPGA0_RFTiming2 0x814 63 64 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ 65 #define rFPGA0_XA_HSSIParameter2 0x824 66 #define rFPGA0_XB_HSSIParameter1 0x828 67 #define rFPGA0_XB_HSSIParameter2 0x82c 68 69 #define rFPGA0_XA_LSSIParameter 0x840 70 #define rFPGA0_XB_LSSIParameter 0x844 71 72 #define rFPGA0_RFWakeUpParameter 0x850 /* Useless now */ 73 #define rFPGA0_RFSleepUpParameter 0x854 74 75 #define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */ 76 #define rFPGA0_XCD_SwitchControl 0x85c 77 78 #define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */ 79 #define rFPGA0_XB_RFInterfaceOE 0x864 80 81 #define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Iface Software Control */ 82 #define rFPGA0_XCD_RFInterfaceSW 0x874 83 84 #define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */ 85 #define rFPGA0_XCD_RFParameter 0x87c 86 87 /* Crystal cap setting RF-R/W protection for parameter4?? */ 88 #define rFPGA0_AnalogParameter1 0x880 89 #define rFPGA0_AnalogParameter2 0x884 90 #define rFPGA0_AnalogParameter3 0x888 91 /* enable ad/da clock1 for dual-phy */ 92 #define rFPGA0_AdDaClockEn 0x888 93 #define rFPGA0_AnalogParameter4 0x88c 94 95 #define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */ 96 #define rFPGA0_XB_LSSIReadBack 0x8a4 97 #define rFPGA0_XC_LSSIReadBack 0x8a8 98 #define rFPGA0_XD_LSSIReadBack 0x8ac 99 100 #define rFPGA0_PSDReport 0x8b4 /* Useless now */ 101 /* Transceiver A HSPI Readback */ 102 #define TransceiverA_HSPI_Readback 0x8b8 103 /* Transceiver B HSPI Readback */ 104 #define TransceiverB_HSPI_Readback 0x8bc 105 /* Useless now RF Interface Readback Value */ 106 #define rFPGA0_XAB_RFInterfaceRB 0x8e0 107 #define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */ 108 109 /* 4. Page9(0x900) */ 110 /* RF mode & OFDM TxSC RF BW Setting?? */ 111 #define rFPGA1_RFMOD 0x900 112 113 #define rFPGA1_TxBlock 0x904 /* Useless now */ 114 #define rFPGA1_DebugSelect 0x908 /* Useless now */ 115 #define rFPGA1_TxInfo 0x90c /* Useless now Status report */ 116 117 /* 5. PageA(0xA00) */ 118 /* Set Control channel to upper or lower - required only for 40MHz */ 119 #define rCCK0_System 0xa00 120 121 /* Disable init gain now Select RX path by RSSI */ 122 #define rCCK0_AFESetting 0xa04 123 /* Disable init gain now Init gain */ 124 #define rCCK0_CCA 0xa08 125 126 /* AGC default value, saturation level Antenna Diversity, RX AGC, LNA Threshold, 127 * RX LNA Threshold useless now. Not the same as 90 series */ 128 #define rCCK0_RxAGC1 0xa0c 129 #define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */ 130 131 #define rCCK0_RxHP 0xa14 132 133 /* Timing recovery & Channel estimation threshold */ 134 #define rCCK0_DSPParameter1 0xa18 135 #define rCCK0_DSPParameter2 0xa1c /* SQ threshold */ 136 137 #define rCCK0_TxFilter1 0xa20 138 #define rCCK0_TxFilter2 0xa24 139 #define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */ 140 #define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now */ 141 #define rCCK0_TRSSIReport 0xa50 142 #define rCCK0_RxReport 0xa54 /* 0xa57 */ 143 #define rCCK0_FACounterLower 0xa5c /* 0xa5b */ 144 #define rCCK0_FACounterUpper 0xa58 /* 0xa5c */ 145 146 /* */ 147 /* PageB(0xB00) */ 148 /* */ 149 #define rPdp_AntA 0xb00 150 #define rPdp_AntA_4 0xb04 151 #define rConfig_Pmpd_AntA 0xb28 152 #define rConfig_AntA 0xb68 153 #define rConfig_AntB 0xb6c 154 #define rPdp_AntB 0xb70 155 #define rPdp_AntB_4 0xb74 156 #define rConfig_Pmpd_AntB 0xb98 157 #define rAPK 0xbd8 158 159 /* */ 160 /* 6. PageC(0xC00) */ 161 /* */ 162 #define rOFDM0_LSTF 0xc00 163 164 #define rOFDM0_TRxPathEnable 0xc04 165 #define rOFDM0_TRMuxPar 0xc08 166 #define rOFDM0_TRSWIsolation 0xc0c 167 168 /* RxIQ DC offset, Rx digital filter, DC notch filter */ 169 #define rOFDM0_XARxAFE 0xc10 170 #define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */ 171 #define rOFDM0_XBRxAFE 0xc18 172 #define rOFDM0_XBRxIQImbalance 0xc1c 173 #define rOFDM0_XCRxAFE 0xc20 174 #define rOFDM0_XCRxIQImbalance 0xc24 175 #define rOFDM0_XDRxAFE 0xc28 176 #define rOFDM0_XDRxIQImbalance 0xc2c 177 178 #define rOFDM0_RxDetector1 0xc30 /*PD,BW & SBD DM tune init gain*/ 179 #define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */ 180 #define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */ 181 #define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */ 182 183 #define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */ 184 #define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */ 185 #define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */ 186 #define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */ 187 188 #define rOFDM0_XAAGCCore1 0xc50 /* DIG */ 189 #define rOFDM0_XAAGCCore2 0xc54 190 #define rOFDM0_XBAGCCore1 0xc58 191 #define rOFDM0_XBAGCCore2 0xc5c 192 #define rOFDM0_XCAGCCore1 0xc60 193 #define rOFDM0_XCAGCCore2 0xc64 194 #define rOFDM0_XDAGCCore1 0xc68 195 #define rOFDM0_XDAGCCore2 0xc6c 196 197 #define rOFDM0_AGCParameter1 0xc70 198 #define rOFDM0_AGCParameter2 0xc74 199 #define rOFDM0_AGCRSSITable 0xc78 200 #define rOFDM0_HTSTFAGC 0xc7c 201 202 #define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */ 203 #define rOFDM0_XATxAFE 0xc84 204 #define rOFDM0_XBTxIQImbalance 0xc88 205 #define rOFDM0_XBTxAFE 0xc8c 206 #define rOFDM0_XCTxIQImbalance 0xc90 207 #define rOFDM0_XCTxAFE 0xc94 208 #define rOFDM0_XDTxIQImbalance 0xc98 209 #define rOFDM0_XDTxAFE 0xc9c 210 211 #define rOFDM0_RxIQExtAnta 0xca0 212 #define rOFDM0_TxCoeff1 0xca4 213 #define rOFDM0_TxCoeff2 0xca8 214 #define rOFDM0_TxCoeff3 0xcac 215 #define rOFDM0_TxCoeff4 0xcb0 216 #define rOFDM0_TxCoeff5 0xcb4 217 #define rOFDM0_TxCoeff6 0xcb8 218 #define rOFDM0_RxHPParameter 0xce0 219 #define rOFDM0_TxPseudoNoiseWgt 0xce4 220 #define rOFDM0_FrameSync 0xcf0 221 #define rOFDM0_DFSReport 0xcf4 222 223 /* */ 224 /* 7. PageD(0xD00) */ 225 /* */ 226 #define rOFDM1_LSTF 0xd00 227 #define rOFDM1_TRxPathEnable 0xd04 228 229 #define rOFDM1_CFO 0xd08 /* No setting now */ 230 #define rOFDM1_CSI1 0xd10 231 #define rOFDM1_SBD 0xd14 232 #define rOFDM1_CSI2 0xd18 233 #define rOFDM1_CFOTracking 0xd2c 234 #define rOFDM1_TRxMesaure1 0xd34 235 #define rOFDM1_IntfDet 0xd3c 236 #define rOFDM1_PseudoNoiseStateAB 0xd50 237 #define rOFDM1_PseudoNoiseStateCD 0xd54 238 #define rOFDM1_RxPseudoNoiseWgt 0xd58 239 240 #define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */ 241 #define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */ 242 #define rOFDM_PHYCounter3 0xda8 /* MCS not support */ 243 244 #define rOFDM_ShortCFOAB 0xdac /* No setting now */ 245 #define rOFDM_ShortCFOCD 0xdb0 246 #define rOFDM_LongCFOAB 0xdb4 247 #define rOFDM_LongCFOCD 0xdb8 248 #define rOFDM_TailCFOAB 0xdbc 249 #define rOFDM_TailCFOCD 0xdc0 250 #define rOFDM_PWMeasure1 0xdc4 251 #define rOFDM_PWMeasure2 0xdc8 252 #define rOFDM_BWReport 0xdcc 253 #define rOFDM_AGCReport 0xdd0 254 #define rOFDM_RxSNR 0xdd4 255 #define rOFDM_RxEVMCSI 0xdd8 256 #define rOFDM_SIGReport 0xddc 257 258 /* */ 259 /* 8. PageE(0xE00) */ 260 /* */ 261 #define rTxAGC_A_Rate18_06 0xe00 262 #define rTxAGC_A_Rate54_24 0xe04 263 #define rTxAGC_A_CCK1_Mcs32 0xe08 264 #define rTxAGC_A_Mcs03_Mcs00 0xe10 265 #define rTxAGC_A_Mcs07_Mcs04 0xe14 266 #define rTxAGC_A_Mcs11_Mcs08 0xe18 267 #define rTxAGC_A_Mcs15_Mcs12 0xe1c 268 269 #define rTxAGC_B_Rate18_06 0x830 270 #define rTxAGC_B_Rate54_24 0x834 271 #define rTxAGC_B_CCK1_55_Mcs32 0x838 272 #define rTxAGC_B_Mcs03_Mcs00 0x83c 273 #define rTxAGC_B_Mcs07_Mcs04 0x848 274 #define rTxAGC_B_Mcs11_Mcs08 0x84c 275 #define rTxAGC_B_Mcs15_Mcs12 0x868 276 #define rTxAGC_B_CCK11_A_CCK2_11 0x86c 277 278 #define rFPGA0_IQK 0xe28 279 #define rTx_IQK_Tone_A 0xe30 280 #define rRx_IQK_Tone_A 0xe34 281 #define rTx_IQK_PI_A 0xe38 282 #define rRx_IQK_PI_A 0xe3c 283 284 #define rTx_IQK 0xe40 285 #define rRx_IQK 0xe44 286 #define rIQK_AGC_Pts 0xe48 287 #define rIQK_AGC_Rsp 0xe4c 288 #define rTx_IQK_Tone_B 0xe50 289 #define rRx_IQK_Tone_B 0xe54 290 #define rTx_IQK_PI_B 0xe58 291 #define rRx_IQK_PI_B 0xe5c 292 #define rIQK_AGC_Cont 0xe60 293 294 #define rBlue_Tooth 0xe6c 295 #define rRx_Wait_CCA 0xe70 296 #define rTx_CCK_RFON 0xe74 297 #define rTx_CCK_BBON 0xe78 298 #define rTx_OFDM_RFON 0xe7c 299 #define rTx_OFDM_BBON 0xe80 300 #define rTx_To_Rx 0xe84 301 #define rTx_To_Tx 0xe88 302 #define rRx_CCK 0xe8c 303 304 #define rTx_Power_Before_IQK_A 0xe94 305 #define rTx_Power_After_IQK_A 0xe9c 306 307 #define rRx_Power_Before_IQK_A 0xea0 308 #define rRx_Power_Before_IQK_A_2 0xea4 309 #define rRx_Power_After_IQK_A 0xea8 310 #define rRx_Power_After_IQK_A_2 0xeac 311 312 #define rTx_Power_Before_IQK_B 0xeb4 313 #define rTx_Power_After_IQK_B 0xebc 314 315 #define rRx_Power_Before_IQK_B 0xec0 316 #define rRx_Power_Before_IQK_B_2 0xec4 317 #define rRx_Power_After_IQK_B 0xec8 318 #define rRx_Power_After_IQK_B_2 0xecc 319 320 #define rRx_OFDM 0xed0 321 #define rRx_Wait_RIFS 0xed4 322 #define rRx_TO_Rx 0xed8 323 #define rStandby 0xedc 324 #define rSleep 0xee0 325 #define rPMPD_ANAEN 0xeec 326 327 /* */ 328 /* 7. RF Register 0x00-0x2E (RF 8256) */ 329 /* RF-0222D 0x00-3F */ 330 /* */ 331 /* Zebra1 */ 332 #define rZebra1_HSSIEnable 0x0 /* Useless now */ 333 #define rZebra1_TRxEnable1 0x1 334 #define rZebra1_TRxEnable2 0x2 335 #define rZebra1_AGC 0x4 336 #define rZebra1_ChargePump 0x5 337 #define rZebra1_Channel 0x7 /* RF channel switch */ 338 339 /* endif */ 340 #define rZebra1_TxGain 0x8 /* Useless now */ 341 #define rZebra1_TxLPF 0x9 342 #define rZebra1_RxLPF 0xb 343 #define rZebra1_RxHPFCorner 0xc 344 345 /* Zebra4 */ 346 #define rGlobalCtrl 0 /* Useless now */ 347 #define rRTL8256_TxLPF 19 348 #define rRTL8256_RxLPF 11 349 350 /* RTL8258 */ 351 #define rRTL8258_TxLPF 0x11 /* Useless now */ 352 #define rRTL8258_RxLPF 0x13 353 #define rRTL8258_RSSILPF 0xa 354 355 /* */ 356 /* RL6052 Register definition */ 357 /* */ 358 #define RF_AC 0x00 /* */ 359 360 #define RF_IQADJ_G1 0x01 /* */ 361 #define RF_IQADJ_G2 0x02 /* */ 362 363 #define RF_POW_TRSW 0x05 /* */ 364 365 #define RF_GAIN_RX 0x06 /* */ 366 #define RF_GAIN_TX 0x07 /* */ 367 368 #define RF_TXM_IDAC 0x08 /* */ 369 #define RF_IPA_G 0x09 /* */ 370 #define RF_TXBIAS_G 0x0A 371 #define RF_TXPA_AG 0x0B 372 #define RF_IPA_A 0x0C /* */ 373 #define RF_TXBIAS_A 0x0D 374 #define RF_BS_PA_APSET_G9_G11 0x0E 375 #define RF_BS_IQGEN 0x0F /* */ 376 377 #define RF_MODE1 0x10 /* */ 378 #define RF_MODE2 0x11 /* */ 379 380 #define RF_RX_AGC_HP 0x12 /* */ 381 #define RF_TX_AGC 0x13 /* */ 382 #define RF_BIAS 0x14 /* */ 383 #define RF_IPA 0x15 /* */ 384 #define RF_TXBIAS 0x16 385 #define RF_POW_ABILITY 0x17 /* */ 386 #define RF_CHNLBW 0x18 /* RF channel and BW switch */ 387 #define RF_TOP 0x19 /* */ 388 389 #define RF_RX_G1 0x1A /* */ 390 #define RF_RX_G2 0x1B /* */ 391 392 #define RF_RX_BB2 0x1C /* */ 393 #define RF_RX_BB1 0x1D /* */ 394 395 #define RF_RCK1 0x1E /* */ 396 #define RF_RCK2 0x1F /* */ 397 398 #define RF_TX_G1 0x20 /* */ 399 #define RF_TX_G2 0x21 /* */ 400 #define RF_TX_G3 0x22 /* */ 401 402 #define RF_TX_BB1 0x23 /* */ 403 404 #define RF_T_METER_92D 0x42 /* */ 405 #define RF_T_METER_88E 0x42 /* */ 406 #define RF_T_METER 0x24 /* */ 407 408 #define RF_SYN_G1 0x25 /* RF TX Power control */ 409 #define RF_SYN_G2 0x26 /* RF TX Power control */ 410 #define RF_SYN_G3 0x27 /* RF TX Power control */ 411 #define RF_SYN_G4 0x28 /* RF TX Power control */ 412 #define RF_SYN_G5 0x29 /* RF TX Power control */ 413 #define RF_SYN_G6 0x2A /* RF TX Power control */ 414 #define RF_SYN_G7 0x2B /* RF TX Power control */ 415 #define RF_SYN_G8 0x2C /* RF TX Power control */ 416 417 #define RF_RCK_OS 0x30 /* RF TX PA control */ 418 #define RF_TXPA_G1 0x31 /* RF TX PA control */ 419 #define RF_TXPA_G2 0x32 /* RF TX PA control */ 420 #define RF_TXPA_G3 0x33 /* RF TX PA control */ 421 #define RF_TX_BIAS_A 0x35 422 #define RF_TX_BIAS_D 0x36 423 #define RF_LOBF_9 0x38 424 #define RF_RXRF_A3 0x3C /* */ 425 #define RF_TRSW 0x3F 426 427 #define RF_TXRF_A2 0x41 428 #define RF_TXPA_G4 0x46 429 #define RF_TXPA_A4 0x4B 430 #define RF_0x52 0x52 431 #define RF_WE_LUT 0xEF 432 433 /* */ 434 /* Bit Mask */ 435 /* */ 436 /* 1. Page1(0x100) */ 437 #define bBBResetB 0x100 /* Useless now? */ 438 #define bGlobalResetB 0x200 439 #define bOFDMTxStart 0x4 440 #define bCCKTxStart 0x8 441 #define bCRC32Debug 0x100 442 #define bPMACLoopback 0x10 443 #define bTxLSIG 0xffffff 444 #define bOFDMTxRate 0xf 445 #define bOFDMTxReserved 0x10 446 #define bOFDMTxLength 0x1ffe0 447 #define bOFDMTxParity 0x20000 448 #define bTxHTSIG1 0xffffff 449 #define bTxHTMCSRate 0x7f 450 #define bTxHTBW 0x80 451 #define bTxHTLength 0xffff00 452 #define bTxHTSIG2 0xffffff 453 #define bTxHTSmoothing 0x1 454 #define bTxHTSounding 0x2 455 #define bTxHTReserved 0x4 456 #define bTxHTAggreation 0x8 457 #define bTxHTSTBC 0x30 458 #define bTxHTAdvanceCoding 0x40 459 #define bTxHTShortGI 0x80 460 #define bTxHTNumberHT_LTF 0x300 461 #define bTxHTCRC8 0x3fc00 462 #define bCounterReset 0x10000 463 #define bNumOfOFDMTx 0xffff 464 #define bNumOfCCKTx 0xffff0000 465 #define bTxIdleInterval 0xffff 466 #define bOFDMService 0xffff0000 467 #define bTxMACHeader 0xffffffff 468 #define bTxDataInit 0xff 469 #define bTxHTMode 0x100 470 #define bTxDataType 0x30000 471 #define bTxRandomSeed 0xffffffff 472 #define bCCKTxPreamble 0x1 473 #define bCCKTxSFD 0xffff0000 474 #define bCCKTxSIG 0xff 475 #define bCCKTxService 0xff00 476 #define bCCKLengthExt 0x8000 477 #define bCCKTxLength 0xffff0000 478 #define bCCKTxCRC16 0xffff 479 #define bCCKTxStatus 0x1 480 #define bOFDMTxStatus 0x2 481 482 #define IS_BB_REG_OFFSET_92S(_Offset) \ 483 ((_Offset >= 0x800) && (_Offset <= 0xfff)) 484 485 /* 2. Page8(0x800) */ 486 #define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */ 487 #define bJapanMode 0x2 488 #define bCCKTxSC 0x30 489 #define bCCKEn 0x1000000 490 #define bOFDMEn 0x2000000 491 492 #define bOFDMRxADCPhase 0x10000 /* Useless now */ 493 #define bOFDMTxDACPhase 0x40000 494 #define bXATxAGC 0x3f 495 496 #define bAntennaSelect 0x0300 497 498 #define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */ 499 #define bXCTxAGC 0xf000 500 #define bXDTxAGC 0xf0000 501 502 #define bPAStart 0xf0000000 /* Useless now */ 503 #define bTRStart 0x00f00000 504 #define bRFStart 0x0000f000 505 #define bBBStart 0x000000f0 506 #define bBBCCKStart 0x0000000f 507 #define bPAEnd 0xf /* Reg0x814 */ 508 #define bTREnd 0x0f000000 509 #define bRFEnd 0x000f0000 510 #define bCCAMask 0x000000f0 /* T2R */ 511 #define bR2RCCAMask 0x00000f00 512 #define bHSSI_R2TDelay 0xf8000000 513 #define bHSSI_T2RDelay 0xf80000 514 #define bContTxHSSI 0x400 /* change gain at continue Tx */ 515 #define bIGFromCCK 0x200 516 #define bAGCAddress 0x3f 517 #define bRxHPTx 0x7000 518 #define bRxHPT2R 0x38000 519 #define bRxHPCCKIni 0xc0000 520 #define bAGCTxCode 0xc00000 521 #define bAGCRxCode 0x300000 522 523 /* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */ 524 #define b3WireDataLength 0x800 525 #define b3WireAddressLength 0x400 526 527 #define b3WireRFPowerDown 0x1 /* Useless now */ 528 #define b5GPAPEPolarity 0x40000000 529 #define b2GPAPEPolarity 0x80000000 530 #define bRFSW_TxDefaultAnt 0x3 531 #define bRFSW_TxOptionAnt 0x30 532 #define bRFSW_RxDefaultAnt 0x300 533 #define bRFSW_RxOptionAnt 0x3000 534 #define bRFSI_3WireData 0x1 535 #define bRFSI_3WireClock 0x2 536 #define bRFSI_3WireLoad 0x4 537 #define bRFSI_3WireRW 0x8 538 #define bRFSI_3Wire 0xf 539 540 #define bRFSI_RFENV 0x10 /* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */ 541 542 #define bRFSI_TRSW 0x20 /* Useless now */ 543 #define bRFSI_TRSWB 0x40 544 #define bRFSI_ANTSW 0x100 545 #define bRFSI_ANTSWB 0x200 546 #define bRFSI_PAPE 0x400 547 #define bRFSI_PAPE5G 0x800 548 #define bBandSelect 0x1 549 #define bHTSIG2_GI 0x80 550 #define bHTSIG2_Smoothing 0x01 551 #define bHTSIG2_Sounding 0x02 552 #define bHTSIG2_Aggreaton 0x08 553 #define bHTSIG2_STBC 0x30 554 #define bHTSIG2_AdvCoding 0x40 555 #define bHTSIG2_NumOfHTLTF 0x300 556 #define bHTSIG2_CRC8 0x3fc 557 #define bHTSIG1_MCS 0x7f 558 #define bHTSIG1_BandWidth 0x80 559 #define bHTSIG1_HTLength 0xffff 560 #define bLSIG_Rate 0xf 561 #define bLSIG_Reserved 0x10 562 #define bLSIG_Length 0x1fffe 563 #define bLSIG_Parity 0x20 564 #define bCCKRxPhase 0x4 565 566 #define bLSSIReadAddress 0x7f800000 /* T65 RF */ 567 568 #define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */ 569 570 #define bLSSIReadBackData 0xfffff /* T65 RF */ 571 572 #define bLSSIReadOKFlag 0x1000 /* Useless now */ 573 #define bCCKSampleRate 0x8 /* 0: 44MHz, 1:88MHz */ 574 #define bRegulator0Standby 0x1 575 #define bRegulatorPLLStandby 0x2 576 #define bRegulator1Standby 0x4 577 #define bPLLPowerUp 0x8 578 #define bDPLLPowerUp 0x10 579 #define bDA10PowerUp 0x20 580 #define bAD7PowerUp 0x200 581 #define bDA6PowerUp 0x2000 582 #define bXtalPowerUp 0x4000 583 #define b40MDClkPowerUP 0x8000 584 #define bDA6DebugMode 0x20000 585 #define bDA6Swing 0x380000 586 587 /* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */ 588 #define bADClkPhase 0x4000000 589 590 #define b80MClkDelay 0x18000000 /* Useless */ 591 #define bAFEWatchDogEnable 0x20000000 592 593 /* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */ 594 #define bXtalCap01 0xc0000000 595 #define bXtalCap23 0x3 596 #define bXtalCap92x 0x0f000000 597 #define bXtalCap 0x0f000000 598 599 #define bIntDifClkEnable 0x400 /* Useless */ 600 #define bExtSigClkEnable 0x800 601 #define bBandgapMbiasPowerUp 0x10000 602 #define bAD11SHGain 0xc0000 603 #define bAD11InputRange 0x700000 604 #define bAD11OPCurrent 0x3800000 605 #define bIPathLoopback 0x4000000 606 #define bQPathLoopback 0x8000000 607 #define bAFELoopback 0x10000000 608 #define bDA10Swing 0x7e0 609 #define bDA10Reverse 0x800 610 #define bDAClkSource 0x1000 611 #define bAD7InputRange 0x6000 612 #define bAD7Gain 0x38000 613 #define bAD7OutputCMMode 0x40000 614 #define bAD7InputCMMode 0x380000 615 #define bAD7Current 0xc00000 616 #define bRegulatorAdjust 0x7000000 617 #define bAD11PowerUpAtTx 0x1 618 #define bDA10PSAtTx 0x10 619 #define bAD11PowerUpAtRx 0x100 620 #define bDA10PSAtRx 0x1000 621 #define bCCKRxAGCFormat 0x200 622 #define bPSDFFTSamplepPoint 0xc000 623 #define bPSDAverageNum 0x3000 624 #define bIQPathControl 0xc00 625 #define bPSDFreq 0x3ff 626 #define bPSDAntennaPath 0x30 627 #define bPSDIQSwitch 0x40 628 #define bPSDRxTrigger 0x400000 629 #define bPSDTxTrigger 0x80000000 630 #define bPSDSineToneScale 0x7f000000 631 #define bPSDReport 0xffff 632 633 /* 3. Page9(0x900) */ 634 #define bOFDMTxSC 0x30000000 /* Useless */ 635 #define bCCKTxOn 0x1 636 #define bOFDMTxOn 0x2 637 #define bDebugPage 0xfff /* reset debug page and HWord, LWord */ 638 #define bDebugItem 0xff /* reset debug page and LWord */ 639 #define bAntL 0x10 640 #define bAntNonHT 0x100 641 #define bAntHT1 0x1000 642 #define bAntHT2 0x10000 643 #define bAntHT1S1 0x100000 644 #define bAntNonHTS1 0x1000000 645 646 /* 4. PageA(0xA00) */ 647 #define bCCKBBMode 0x3 /* Useless */ 648 #define bCCKTxPowerSaving 0x80 649 #define bCCKRxPowerSaving 0x40 650 651 #define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 */ 652 653 #define bCCKScramble 0x8 /* Useless */ 654 #define bCCKAntDiversity 0x8000 655 #define bCCKCarrierRecovery 0x4000 656 #define bCCKTxRate 0x3000 657 #define bCCKDCCancel 0x0800 658 #define bCCKISICancel 0x0400 659 #define bCCKMatchFilter 0x0200 660 #define bCCKEqualizer 0x0100 661 #define bCCKPreambleDetect 0x800000 662 #define bCCKFastFalseCCA 0x400000 663 #define bCCKChEstStart 0x300000 664 #define bCCKCCACount 0x080000 665 #define bCCKcs_lim 0x070000 666 #define bCCKBistMode 0x80000000 667 #define bCCKCCAMask 0x40000000 668 #define bCCKTxDACPhase 0x4 669 #define bCCKRxADCPhase 0x20000000 /* r_rx_clk */ 670 #define bCCKr_cp_mode0 0x0100 671 #define bCCKTxDCOffset 0xf0 672 #define bCCKRxDCOffset 0xf 673 #define bCCKCCAMode 0xc000 674 #define bCCKFalseCS_lim 0x3f00 675 #define bCCKCS_ratio 0xc00000 676 #define bCCKCorgBit_sel 0x300000 677 #define bCCKPD_lim 0x0f0000 678 #define bCCKNewCCA 0x80000000 679 #define bCCKRxHPofIG 0x8000 680 #define bCCKRxIG 0x7f00 681 #define bCCKLNAPolarity 0x800000 682 #define bCCKRx1stGain 0x7f0000 683 #define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */ 684 #define bCCKRxAGCSatLevel 0x1f000000 685 #define bCCKRxAGCSatCount 0xe0 686 #define bCCKRxRFSettle 0x1f /* AGCsamp_dly */ 687 #define bCCKFixedRxAGC 0x8000 688 #define bCCKAntennaPolarity 0x2000 689 #define bCCKTxFilterType 0x0c00 690 #define bCCKRxAGCReportType 0x0300 691 #define bCCKRxDAGCEn 0x80000000 692 #define bCCKRxDAGCPeriod 0x20000000 693 #define bCCKRxDAGCSatLevel 0x1f000000 694 #define bCCKTimingRecovery 0x800000 695 #define bCCKTxC0 0x3f0000 696 #define bCCKTxC1 0x3f000000 697 #define bCCKTxC2 0x3f 698 #define bCCKTxC3 0x3f00 699 #define bCCKTxC4 0x3f0000 700 #define bCCKTxC5 0x3f000000 701 #define bCCKTxC6 0x3f 702 #define bCCKTxC7 0x3f00 703 #define bCCKDebugPort 0xff0000 704 #define bCCKDACDebug 0x0f000000 705 #define bCCKFalseAlarmEnable 0x8000 706 #define bCCKFalseAlarmRead 0x4000 707 #define bCCKTRSSI 0x7f 708 #define bCCKRxAGCReport 0xfe 709 #define bCCKRxReport_AntSel 0x80000000 710 #define bCCKRxReport_MFOff 0x40000000 711 #define bCCKRxRxReport_SQLoss 0x20000000 712 #define bCCKRxReport_Pktloss 0x10000000 713 #define bCCKRxReport_Lockedbit 0x08000000 714 #define bCCKRxReport_RateError 0x04000000 715 #define bCCKRxReport_RxRate 0x03000000 716 #define bCCKRxFACounterLower 0xff 717 #define bCCKRxFACounterUpper 0xff000000 718 #define bCCKRxHPAGCStart 0xe000 719 #define bCCKRxHPAGCFinal 0x1c00 720 #define bCCKRxFalseAlarmEnable 0x8000 721 #define bCCKFACounterFreeze 0x4000 722 #define bCCKTxPathSel 0x10000000 723 #define bCCKDefaultRxPath 0xc000000 724 #define bCCKOptionRxPath 0x3000000 725 726 /* 5. PageC(0xC00) */ 727 #define bNumOfSTF 0x3 /* Useless */ 728 #define bShift_L 0xc0 729 #define bGI_TH 0xc 730 #define bRxPathA 0x1 731 #define bRxPathB 0x2 732 #define bRxPathC 0x4 733 #define bRxPathD 0x8 734 #define bTxPathA 0x1 735 #define bTxPathB 0x2 736 #define bTxPathC 0x4 737 #define bTxPathD 0x8 738 #define bTRSSIFreq 0x200 739 #define bADCBackoff 0x3000 740 #define bDFIRBackoff 0xc000 741 #define bTRSSILatchPhase 0x10000 742 #define bRxIDCOffset 0xff 743 #define bRxQDCOffset 0xff00 744 #define bRxDFIRMode 0x1800000 745 #define bRxDCNFType 0xe000000 746 #define bRXIQImb_A 0x3ff 747 #define bRXIQImb_B 0xfc00 748 #define bRXIQImb_C 0x3f0000 749 #define bRXIQImb_D 0xffc00000 750 #define bDC_dc_Notch 0x60000 751 #define bRxNBINotch 0x1f000000 752 #define bPD_TH 0xf 753 #define bPD_TH_Opt2 0xc000 754 #define bPWED_TH 0x700 755 #define bIfMF_Win_L 0x800 756 #define bPD_Option 0x1000 757 #define bMF_Win_L 0xe000 758 #define bBW_Search_L 0x30000 759 #define bwin_enh_L 0xc0000 760 #define bBW_TH 0x700000 761 #define bED_TH2 0x3800000 762 #define bBW_option 0x4000000 763 #define bRatio_TH 0x18000000 764 #define bWindow_L 0xe0000000 765 #define bSBD_Option 0x1 766 #define bFrame_TH 0x1c 767 #define bFS_Option 0x60 768 #define bDC_Slope_check 0x80 769 #define bFGuard_Counter_DC_L 0xe00 770 #define bFrame_Weight_Short 0x7000 771 #define bSub_Tune 0xe00000 772 #define bFrame_DC_Length 0xe000000 773 #define bSBD_start_offset 0x30000000 774 #define bFrame_TH_2 0x7 775 #define bFrame_GI2_TH 0x38 776 #define bGI2_Sync_en 0x40 777 #define bSarch_Short_Early 0x300 778 #define bSarch_Short_Late 0xc00 779 #define bSarch_GI2_Late 0x70000 780 #define bCFOAntSum 0x1 781 #define bCFOAcc 0x2 782 #define bCFOStartOffset 0xc 783 #define bCFOLookBack 0x70 784 #define bCFOSumWeight 0x80 785 #define bDAGCEnable 0x10000 786 #define bTXIQImb_A 0x3ff 787 #define bTXIQImb_B 0xfc00 788 #define bTXIQImb_C 0x3f0000 789 #define bTXIQImb_D 0xffc00000 790 #define bTxIDCOffset 0xff 791 #define bTxQDCOffset 0xff00 792 #define bTxDFIRMode 0x10000 793 #define bTxPesudoNoiseOn 0x4000000 794 #define bTxPesudoNoise_A 0xff 795 #define bTxPesudoNoise_B 0xff00 796 #define bTxPesudoNoise_C 0xff0000 797 #define bTxPesudoNoise_D 0xff000000 798 #define bCCADropOption 0x20000 799 #define bCCADropThres 0xfff00000 800 #define bEDCCA_H 0xf 801 #define bEDCCA_L 0xf0 802 #define bLambda_ED 0x300 803 #define bRxInitialGain 0x7f 804 #define bRxAntDivEn 0x80 805 #define bRxAGCAddressForLNA 0x7f00 806 #define bRxHighPowerFlow 0x8000 807 #define bRxAGCFreezeThres 0xc0000 808 #define bRxFreezeStep_AGC1 0x300000 809 #define bRxFreezeStep_AGC2 0xc00000 810 #define bRxFreezeStep_AGC3 0x3000000 811 #define bRxFreezeStep_AGC0 0xc000000 812 #define bRxRssi_Cmp_En 0x10000000 813 #define bRxQuickAGCEn 0x20000000 814 #define bRxAGCFreezeThresMode 0x40000000 815 #define bRxOverFlowCheckType 0x80000000 816 #define bRxAGCShift 0x7f 817 #define bTRSW_Tri_Only 0x80 818 #define bPowerThres 0x300 819 #define bRxAGCEn 0x1 820 #define bRxAGCTogetherEn 0x2 821 #define bRxAGCMin 0x4 822 #define bRxHP_Ini 0x7 823 #define bRxHP_TRLNA 0x70 824 #define bRxHP_RSSI 0x700 825 #define bRxHP_BBP1 0x7000 826 #define bRxHP_BBP2 0x70000 827 #define bRxHP_BBP3 0x700000 828 #define bRSSI_H 0x7f0000 /* threshold for high power */ 829 #define bRSSI_Gen 0x7f000000 /* threshold for ant diversity */ 830 #define bRxSettle_TRSW 0x7 831 #define bRxSettle_LNA 0x38 832 #define bRxSettle_RSSI 0x1c0 833 #define bRxSettle_BBP 0xe00 834 #define bRxSettle_RxHP 0x7000 835 #define bRxSettle_AntSW_RSSI 0x38000 836 #define bRxSettle_AntSW 0xc0000 837 #define bRxProcessTime_DAGC 0x300000 838 #define bRxSettle_HSSI 0x400000 839 #define bRxProcessTime_BBPPW 0x800000 840 #define bRxAntennaPowerShift 0x3000000 841 #define bRSSITableSelect 0xc000000 842 #define bRxHP_Final 0x7000000 843 #define bRxHTSettle_BBP 0x7 844 #define bRxHTSettle_HSSI 0x8 845 #define bRxHTSettle_RxHP 0x70 846 #define bRxHTSettle_BBPPW 0x80 847 #define bRxHTSettle_Idle 0x300 848 #define bRxHTSettle_Reserved 0x1c00 849 #define bRxHTRxHPEn 0x8000 850 #define bRxHTAGCFreezeThres 0x30000 851 #define bRxHTAGCTogetherEn 0x40000 852 #define bRxHTAGCMin 0x80000 853 #define bRxHTAGCEn 0x100000 854 #define bRxHTDAGCEn 0x200000 855 #define bRxHTRxHP_BBP 0x1c00000 856 #define bRxHTRxHP_Final 0xe0000000 857 #define bRxPWRatioTH 0x3 858 #define bRxPWRatioEn 0x4 859 #define bRxMFHold 0x3800 860 #define bRxPD_Delay_TH1 0x38 861 #define bRxPD_Delay_TH2 0x1c0 862 #define bRxPD_DC_COUNT_MAX 0x600 863 #define bRxPD_Delay_TH 0x8000 864 #define bRxProcess_Delay 0xf0000 865 #define bRxSearchrange_GI2_Early 0x700000 866 #define bRxFrame_Guard_Counter_L 0x3800000 867 #define bRxSGI_Guard_L 0xc000000 868 #define bRxSGI_Search_L 0x30000000 869 #define bRxSGI_TH 0xc0000000 870 #define bDFSCnt0 0xff 871 #define bDFSCnt1 0xff00 872 #define bDFSFlag 0xf0000 873 #define bMFWeightSum 0x300000 874 #define bMinIdxTH 0x7f000000 875 #define bDAFormat 0x40000 876 #define bTxChEmuEnable 0x01000000 877 #define bTRSWIsolation_A 0x7f 878 #define bTRSWIsolation_B 0x7f00 879 #define bTRSWIsolation_C 0x7f0000 880 #define bTRSWIsolation_D 0x7f000000 881 #define bExtLNAGain 0x7c00 882 883 /* 6. PageE(0xE00) */ 884 #define bSTBCEn 0x4 /* Useless */ 885 #define bAntennaMapping 0x10 886 #define bNss 0x20 887 #define bCFOAntSumD 0x200 888 #define bPHYCounterReset 0x8000000 889 #define bCFOReportGet 0x4000000 890 #define bOFDMContinueTx 0x10000000 891 #define bOFDMSingleCarrier 0x20000000 892 #define bOFDMSingleTone 0x40000000 893 #define bHTDetect 0x100 894 #define bCFOEn 0x10000 895 #define bCFOValue 0xfff00000 896 #define bSigTone_Re 0x3f 897 #define bSigTone_Im 0x7f00 898 #define bCounter_CCA 0xffff 899 #define bCounter_ParityFail 0xffff0000 900 #define bCounter_RateIllegal 0xffff 901 #define bCounter_CRC8Fail 0xffff0000 902 #define bCounter_MCSNoSupport 0xffff 903 #define bCounter_FastSync 0xffff 904 #define bShortCFO 0xfff 905 #define bShortCFOTLength 12 /* total */ 906 #define bShortCFOFLength 11 /* fraction */ 907 #define bLongCFO 0x7ff 908 #define bLongCFOTLength 11 909 #define bLongCFOFLength 11 910 #define bTailCFO 0x1fff 911 #define bTailCFOTLength 13 912 #define bTailCFOFLength 12 913 #define bmax_en_pwdB 0xffff 914 #define bCC_power_dB 0xffff0000 915 #define bnoise_pwdB 0xffff 916 #define bPowerMeasTLength 10 917 #define bPowerMeasFLength 3 918 #define bRx_HT_BW 0x1 919 #define bRxSC 0x6 920 #define bRx_HT 0x8 921 #define bNB_intf_det_on 0x1 922 #define bIntf_win_len_cfg 0x30 923 #define bNB_Intf_TH_cfg 0x1c0 924 #define bRFGain 0x3f 925 #define bTableSel 0x40 926 #define bTRSW 0x80 927 #define bRxSNR_A 0xff 928 #define bRxSNR_B 0xff00 929 #define bRxSNR_C 0xff0000 930 #define bRxSNR_D 0xff000000 931 #define bSNREVMTLength 8 932 #define bSNREVMFLength 1 933 #define bCSI1st 0xff 934 #define bCSI2nd 0xff00 935 #define bRxEVM1st 0xff0000 936 #define bRxEVM2nd 0xff000000 937 #define bSIGEVM 0xff 938 #define bPWDB 0xff00 939 #define bSGIEN 0x10000 940 941 #define bSFactorQAM1 0xf /* Useless */ 942 #define bSFactorQAM2 0xf0 943 #define bSFactorQAM3 0xf00 944 #define bSFactorQAM4 0xf000 945 #define bSFactorQAM5 0xf0000 946 #define bSFactorQAM6 0xf0000 947 #define bSFactorQAM7 0xf00000 948 #define bSFactorQAM8 0xf000000 949 #define bSFactorQAM9 0xf0000000 950 #define bCSIScheme 0x100000 951 952 #define bNoiseLvlTopSet 0x3 /* Useless */ 953 #define bChSmooth 0x4 954 #define bChSmoothCfg1 0x38 955 #define bChSmoothCfg2 0x1c0 956 #define bChSmoothCfg3 0xe00 957 #define bChSmoothCfg4 0x7000 958 #define bMRCMode 0x800000 959 #define bTHEVMCfg 0x7000000 960 961 #define bLoopFitType 0x1 /* Useless */ 962 #define bUpdCFO 0x40 963 #define bUpdCFOOffData 0x80 964 #define bAdvUpdCFO 0x100 965 #define bAdvTimeCtrl 0x800 966 #define bUpdClko 0x1000 967 #define bFC 0x6000 968 #define bTrackingMode 0x8000 969 #define bPhCmpEnable 0x10000 970 #define bUpdClkoLTF 0x20000 971 #define bComChCFO 0x40000 972 #define bCSIEstiMode 0x80000 973 #define bAdvUpdEqz 0x100000 974 #define bUChCfg 0x7000000 975 #define bUpdEqz 0x8000000 976 977 /* Rx Pseduo noise */ 978 #define bRxPesudoNoiseOn 0x20000000 /* Useless */ 979 #define bRxPesudoNoise_A 0xff 980 #define bRxPesudoNoise_B 0xff00 981 #define bRxPesudoNoise_C 0xff0000 982 #define bRxPesudoNoise_D 0xff000000 983 #define bPesudoNoiseState_A 0xffff 984 #define bPesudoNoiseState_B 0xffff0000 985 #define bPesudoNoiseState_C 0xffff 986 #define bPesudoNoiseState_D 0xffff0000 987 988 /* 7. RF Register */ 989 /* Zebra1 */ 990 #define bZebra1_HSSIEnable 0x8 /* Useless */ 991 #define bZebra1_TRxControl 0xc00 992 #define bZebra1_TRxGainSetting 0x07f 993 #define bZebra1_RxCorner 0xc00 994 #define bZebra1_TxChargePump 0x38 995 #define bZebra1_RxChargePump 0x7 996 #define bZebra1_ChannelNum 0xf80 997 #define bZebra1_TxLPFBW 0x400 998 #define bZebra1_RxLPFBW 0x600 999 1000 /* Zebra4 */ 1001 #define bRTL8256RegModeCtrl1 0x100 /* Useless */ 1002 #define bRTL8256RegModeCtrl0 0x40 1003 #define bRTL8256_TxLPFBW 0x18 1004 #define bRTL8256_RxLPFBW 0x600 1005 1006 /* RTL8258 */ 1007 #define bRTL8258_TxLPFBW 0xc /* Useless */ 1008 #define bRTL8258_RxLPFBW 0xc00 1009 #define bRTL8258_RSSILPFBW 0xc0 1010 1011 /* */ 1012 /* Other Definition */ 1013 /* */ 1014 1015 /* byte endable for sb_write */ 1016 #define bByte0 0x1 /* Useless */ 1017 #define bByte1 0x2 1018 #define bByte2 0x4 1019 #define bByte3 0x8 1020 #define bWord0 0x3 1021 #define bWord1 0xc 1022 #define bDWord 0xf 1023 1024 /* for PutRegsetting & GetRegSetting BitMask */ 1025 #define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */ 1026 #define bMaskByte1 0xff00 1027 #define bMaskByte2 0xff0000 1028 #define bMaskByte3 0xff000000 1029 #define bMaskHWord 0xffff0000 1030 #define bMaskLWord 0x0000ffff 1031 #define bMaskDWord 0xffffffff 1032 #define bMask12Bits 0xfff 1033 #define bMaskH4Bits 0xf0000000 1034 #define bMaskOFDM_D 0xffc00000 1035 #define bMaskCCK 0x3f3f3f3f 1036 1037 /* for PutRFRegsetting & GetRFRegSetting BitMask */ 1038 #define bRFRegOffsetMask 0xfffff 1039 1040 #define bEnable 0x1 /* Useless */ 1041 #define bDisable 0x0 1042 1043 #define LeftAntenna 0x0 /* Useless */ 1044 #define RightAntenna 0x1 1045 1046 #define tCheckTxStatus 500 /* 500ms Useless */ 1047 #define tUpdateRxCounter 100 /* 100ms */ 1048 1049 #define rateCCK 0 /* Useless */ 1050 #define rateOFDM 1 1051 #define rateHT 2 1052 1053 /* define Register-End */ 1054 #define bPMAC_End 0x1ff /* Useless */ 1055 #define bFPGAPHY0_End 0x8ff 1056 #define bFPGAPHY1_End 0x9ff 1057 #define bCCKPHY0_End 0xaff 1058 #define bOFDMPHY0_End 0xcff 1059 #define bOFDMPHY1_End 0xdff 1060 1061 #define bPMACControl 0x0 /* Useless */ 1062 #define bWMACControl 0x1 1063 #define bWNICControl 0x2 1064 1065 #define PathA 0x0 /* Useless */ 1066 #define PathB 0x1 1067 #define PathC 0x2 1068 #define PathD 0x3 1069 1070 /*--------------------------Define Parameters-------------------------------*/ 1071 1072 #endif 1073