1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2007 - 2011 Realtek Corporation. */ 3 4 #ifndef __HALPWRSEQCMD_H__ 5 #define __HALPWRSEQCMD_H__ 6 7 #include "drv_types.h" 8 9 /*---------------------------------------------*/ 10 /* 3 The value of cmd: 4 bits */ 11 /*---------------------------------------------*/ 12 13 #define PWR_CMD_WRITE 0x01 14 /* offset: the read register offset */ 15 /* msk: the mask of the write bits */ 16 /* value: write value */ 17 /* note: driver shall implement this cmd by read & msk after write */ 18 19 #define PWR_CMD_POLLING 0x02 20 /* offset: the read register offset */ 21 /* msk: the mask of the polled value */ 22 /* value: the value to be polled, masked by the msd field. */ 23 /* note: driver shall implement this cmd by */ 24 /* do{ */ 25 /* if ( (Read(offset) & msk) == (value & msk) ) */ 26 /* break; */ 27 /* } while (not timeout); */ 28 29 #define PWR_CMD_DELAY 0x03 30 /* offset: the value to delay */ 31 /* msk: N/A */ 32 /* value: the unit of delay, 0: us, 1: ms */ 33 34 #define PWR_CMD_END 0x04 35 /* offset: N/A */ 36 /* msk: N/A */ 37 /* value: N/A */ 38 39 enum pwrseq_cmd_delat_unit { 40 PWRSEQ_DELAY_US, 41 PWRSEQ_DELAY_MS, 42 }; 43 44 struct wl_pwr_cfg { 45 u16 offset; 46 u8 cmd:4; 47 u8 msk; 48 u8 value; 49 }; 50 51 #define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset 52 #define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd 53 #define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk 54 #define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value 55 56 /* Prototype of protected function. */ 57 u8 HalPwrSeqCmdParsing(struct adapter *padapter, struct wl_pwr_cfg PwrCfgCmd[]); 58 59 #endif 60