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Searched refs:pll8 (Results 1 – 7 of 7) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/i915/display/
Dintel_dpll_mgr.h214 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; member
Dintel_dpll_mgr.c1915 temp |= pll->state.hw_state.pll8; in bxt_ddi_pll_enable()
2034 hw_state->pll8 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 8)); in bxt_ddi_pll_get_hw_state()
2035 hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK; in bxt_ddi_pll_get_hw_state()
2177 dpll_hw_state->pll8 = PORT_PLL_TARGET_CNT(targ_cnt); in bxt_ddi_set_dpll_hw_state()
2283 hw_state->pll8, in bxt_dump_hw_state()
Dintel_display.c6329 PIPE_CONF_CHECK_X(dpll_hw_state.pll8); in intel_pipe_config_compare()
/linux-5.19.10/drivers/clk/qcom/
Dgcc-mdm9615.c78 static struct clk_pll pll8 = { variable
1592 [PLL8] = &pll8.clkr,
Dgcc-ipq806x.c88 static struct clk_pll pll8 = { variable
110 &pll8.clkr.hw,
3069 [PLL8] = &pll8.clkr,
Dgcc-msm8960.c55 static struct clk_pll pll8 = { variable
3144 [PLL8] = &pll8.clkr,
3372 [PLL8] = &pll8.clkr,
Dgcc-msm8660.c27 static struct clk_pll pll8 = { variable
2449 [PLL8] = &pll8.clkr,