Searched refs:pll3 (Results 1 – 14 of 14) sorted by relevance
| /linux-5.19.10/Documentation/devicetree/bindings/clock/ |
| D | allwinner,sun4i-a10-pll3-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll3-clk.yaml#
20 const: allwinner,sun4i-a10-pll3-clk
44 compatible = "allwinner,sun4i-a10-pll3-clk";
47 clock-output-names = "pll3";
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| D | allwinner,sun4i-a10-tcon-ch0-clk.yaml | 64 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
73 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
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| D | allwinner,sun9i-a80-cpus-clk.yaml | 48 clocks = <&osc32k>, <&osc24M>, <&pll4>, <&pll3>;
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| D | allwinner,sun4i-a10-display-clk.yaml | 53 clocks = <&pll3>, <&pll7>, <&pll5 1>;
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| D | fixed-factor-clock.yaml | 16 - allwinner,sun4i-a10-pll3-2x-clk
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| D | renesas,cpg-clocks.yaml | 203 - const: pll3
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| /linux-5.19.10/drivers/clk/sunxi/ |
| D | Makefile | 18 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-sun4i-pll3.o
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| /linux-5.19.10/drivers/gpu/drm/i915/display/ |
| D | intel_dpll_mgr.h | 214 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; member
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| D | intel_dpll_mgr.c | 1901 temp |= pll->state.hw_state.pll3; in bxt_ddi_pll_enable()
2026 hw_state->pll3 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 3)); in bxt_ddi_pll_get_hw_state()
2027 hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE; in bxt_ddi_pll_get_hw_state()
2171 dpll_hw_state->pll3 = PORT_PLL_M2_FRAC_ENABLE; in bxt_ddi_set_dpll_hw_state()
2219 if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE) in bxt_ddi_pll_get_freq()
2281 hw_state->pll3, in bxt_dump_hw_state()
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| D | intel_display.c | 6327 PIPE_CONF_CHECK_X(dpll_hw_state.pll3); in intel_pipe_config_compare()
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| /linux-5.19.10/drivers/gpu/drm/tegra/ |
| D | sor.c | 368 unsigned int pll3; member
2292 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2294 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2512 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2521 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2775 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_dp_enable()
2777 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_dp_enable()
3294 .pll3 = 0x1a,
3466 .pll3 = 0x1a,
3527 .pll3 = 0x166,
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| /linux-5.19.10/drivers/clk/qcom/ |
| D | gcc-ipq806x.c | 61 static struct clk_pll pll3 = { variable
322 { .hw = &pll3.clkr.hw },
383 { .hw = &pll3.clkr.hw },
3067 [PLL3] = &pll3.clkr,
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| D | gcc-msm8960.c | 28 static struct clk_pll pll3 = { variable
3142 [PLL3] = &pll3.clkr,
3370 [PLL3] = &pll3.clkr,
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| /linux-5.19.10/arch/arm/boot/dts/ |
| D | sh73a0.dtsi | 652 "pll3", "dsi0phy", "dsi1phy",
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