1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Low-level parallel-port routines for 8255-based PC-style hardware.
3  *
4  * Authors: Phil Blundell <philb@gnu.org>
5  *          Tim Waugh <tim@cyberelk.demon.co.uk>
6  *	    Jose Renau <renau@acm.org>
7  *          David Campbell
8  *          Andrea Arcangeli
9  *
10  * based on work by Grant Guenther <grant@torque.net> and Phil Blundell.
11  *
12  * Cleaned up include files - Russell King <linux@arm.uk.linux.org>
13  * DMA support - Bert De Jonghe <bert@sophis.be>
14  * Many ECP bugs fixed.  Fred Barnes & Jamie Lokier, 1999
15  * More PCI support now conditional on CONFIG_PCI, 03/2001, Paul G.
16  * Various hacks, Fred Barnes, 04/2001
17  * Updated probing logic - Adam Belay <ambx1@neo.rr.com>
18  */
19 
20 /* This driver should work with any hardware that is broadly compatible
21  * with that in the IBM PC.  This applies to the majority of integrated
22  * I/O chipsets that are commonly available.  The expected register
23  * layout is:
24  *
25  *	base+0		data
26  *	base+1		status
27  *	base+2		control
28  *
29  * In addition, there are some optional registers:
30  *
31  *	base+3		EPP address
32  *	base+4		EPP data
33  *	base+0x400	ECP config A
34  *	base+0x401	ECP config B
35  *	base+0x402	ECP control
36  *
37  * All registers are 8 bits wide and read/write.  If your hardware differs
38  * only in register addresses (eg because your registers are on 32-bit
39  * word boundaries) then you can alter the constants in parport_pc.h to
40  * accommodate this.
41  *
42  * Note that the ECP registers may not start at offset 0x400 for PCI cards,
43  * but rather will start at port->base_hi.
44  */
45 
46 #include <linux/module.h>
47 #include <linux/init.h>
48 #include <linux/sched/signal.h>
49 #include <linux/delay.h>
50 #include <linux/errno.h>
51 #include <linux/interrupt.h>
52 #include <linux/ioport.h>
53 #include <linux/kernel.h>
54 #include <linux/slab.h>
55 #include <linux/dma-mapping.h>
56 #include <linux/pci.h>
57 #include <linux/pnp.h>
58 #include <linux/platform_device.h>
59 #include <linux/sysctl.h>
60 #include <linux/io.h>
61 #include <linux/uaccess.h>
62 
63 #include <asm/dma.h>
64 
65 #include <linux/parport.h>
66 #include <linux/parport_pc.h>
67 #include <linux/via.h>
68 #include <asm/parport.h>
69 
70 #define PARPORT_PC_MAX_PORTS PARPORT_MAX
71 
72 #ifdef CONFIG_ISA_DMA_API
73 #define HAS_DMA
74 #endif
75 
76 /* ECR modes */
77 #define ECR_SPP 00
78 #define ECR_PS2 01
79 #define ECR_PPF 02
80 #define ECR_ECP 03
81 #define ECR_EPP 04
82 #define ECR_VND 05
83 #define ECR_TST 06
84 #define ECR_CNF 07
85 #define ECR_MODE_MASK 0xe0
86 #define ECR_WRITE(p, v) frob_econtrol((p), 0xff, (v))
87 
88 #undef DEBUG
89 
90 #define NR_SUPERIOS 3
91 static struct superio_struct {	/* For Super-IO chips autodetection */
92 	int io;
93 	int irq;
94 	int dma;
95 } superios[NR_SUPERIOS] = { {0,},};
96 
97 static int user_specified;
98 #if defined(CONFIG_PARPORT_PC_SUPERIO) || \
99        (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
100 static int verbose_probing;
101 #endif
102 static int pci_registered_parport;
103 static int pnp_registered_parport;
104 
105 /* frob_control, but for ECR */
frob_econtrol(struct parport * pb,unsigned char m,unsigned char v)106 static void frob_econtrol(struct parport *pb, unsigned char m,
107 			   unsigned char v)
108 {
109 	unsigned char ectr = 0;
110 
111 	if (m != 0xff)
112 		ectr = inb(ECONTROL(pb));
113 
114 	pr_debug("frob_econtrol(%02x,%02x): %02x -> %02x\n",
115 		 m, v, ectr, (ectr & ~m) ^ v);
116 
117 	outb((ectr & ~m) ^ v, ECONTROL(pb));
118 }
119 
frob_set_mode(struct parport * p,int mode)120 static inline void frob_set_mode(struct parport *p, int mode)
121 {
122 	frob_econtrol(p, ECR_MODE_MASK, mode << 5);
123 }
124 
125 #ifdef CONFIG_PARPORT_PC_FIFO
126 /* Safely change the mode bits in the ECR
127    Returns:
128 	    0    : Success
129 	   -EBUSY: Could not drain FIFO in some finite amount of time,
130 		   mode not changed!
131  */
change_mode(struct parport * p,int m)132 static int change_mode(struct parport *p, int m)
133 {
134 	const struct parport_pc_private *priv = p->physport->private_data;
135 	unsigned char oecr;
136 	int mode;
137 
138 	pr_debug("parport change_mode ECP-ISA to mode 0x%02x\n", m);
139 
140 	if (!priv->ecr) {
141 		printk(KERN_DEBUG "change_mode: but there's no ECR!\n");
142 		return 0;
143 	}
144 
145 	/* Bits <7:5> contain the mode. */
146 	oecr = inb(ECONTROL(p));
147 	mode = (oecr >> 5) & 0x7;
148 	if (mode == m)
149 		return 0;
150 
151 	if (mode >= 2 && !(priv->ctr & 0x20)) {
152 		/* This mode resets the FIFO, so we may
153 		 * have to wait for it to drain first. */
154 		unsigned long expire = jiffies + p->physport->cad->timeout;
155 		int counter;
156 		switch (mode) {
157 		case ECR_PPF: /* Parallel Port FIFO mode */
158 		case ECR_ECP: /* ECP Parallel Port mode */
159 			/* Busy wait for 200us */
160 			for (counter = 0; counter < 40; counter++) {
161 				if (inb(ECONTROL(p)) & 0x01)
162 					break;
163 				if (signal_pending(current))
164 					break;
165 				udelay(5);
166 			}
167 
168 			/* Poll slowly. */
169 			while (!(inb(ECONTROL(p)) & 0x01)) {
170 				if (time_after_eq(jiffies, expire))
171 					/* The FIFO is stuck. */
172 					return -EBUSY;
173 				schedule_timeout_interruptible(
174 							msecs_to_jiffies(10));
175 				if (signal_pending(current))
176 					break;
177 			}
178 		}
179 	}
180 
181 	if (mode >= 2 && m >= 2) {
182 		/* We have to go through mode 001 */
183 		oecr &= ~(7 << 5);
184 		oecr |= ECR_PS2 << 5;
185 		ECR_WRITE(p, oecr);
186 	}
187 
188 	/* Set the mode. */
189 	oecr &= ~(7 << 5);
190 	oecr |= m << 5;
191 	ECR_WRITE(p, oecr);
192 	return 0;
193 }
194 #endif /* FIFO support */
195 
196 /*
197  * Clear TIMEOUT BIT in EPP MODE
198  *
199  * This is also used in SPP detection.
200  */
clear_epp_timeout(struct parport * pb)201 static int clear_epp_timeout(struct parport *pb)
202 {
203 	unsigned char r;
204 
205 	if (!(parport_pc_read_status(pb) & 0x01))
206 		return 1;
207 
208 	/* To clear timeout some chips require double read */
209 	parport_pc_read_status(pb);
210 	r = parport_pc_read_status(pb);
211 	outb(r | 0x01, STATUS(pb)); /* Some reset by writing 1 */
212 	outb(r & 0xfe, STATUS(pb)); /* Others by writing 0 */
213 	r = parport_pc_read_status(pb);
214 
215 	return !(r & 0x01);
216 }
217 
218 /*
219  * Access functions.
220  *
221  * Most of these aren't static because they may be used by the
222  * parport_xxx_yyy macros.  extern __inline__ versions of several
223  * of these are in parport_pc.h.
224  */
225 
parport_pc_init_state(struct pardevice * dev,struct parport_state * s)226 static void parport_pc_init_state(struct pardevice *dev,
227 						struct parport_state *s)
228 {
229 	s->u.pc.ctr = 0xc;
230 	if (dev->irq_func &&
231 	    dev->port->irq != PARPORT_IRQ_NONE)
232 		/* Set ackIntEn */
233 		s->u.pc.ctr |= 0x10;
234 
235 	s->u.pc.ecr = 0x34; /* NetMos chip can cause problems 0x24;
236 			     * D.Gruszka VScom */
237 }
238 
parport_pc_save_state(struct parport * p,struct parport_state * s)239 static void parport_pc_save_state(struct parport *p, struct parport_state *s)
240 {
241 	const struct parport_pc_private *priv = p->physport->private_data;
242 	s->u.pc.ctr = priv->ctr;
243 	if (priv->ecr)
244 		s->u.pc.ecr = inb(ECONTROL(p));
245 }
246 
parport_pc_restore_state(struct parport * p,struct parport_state * s)247 static void parport_pc_restore_state(struct parport *p,
248 						struct parport_state *s)
249 {
250 	struct parport_pc_private *priv = p->physport->private_data;
251 	register unsigned char c = s->u.pc.ctr & priv->ctr_writable;
252 	outb(c, CONTROL(p));
253 	priv->ctr = c;
254 	if (priv->ecr)
255 		ECR_WRITE(p, s->u.pc.ecr);
256 }
257 
258 #ifdef CONFIG_PARPORT_1284
parport_pc_epp_read_data(struct parport * port,void * buf,size_t length,int flags)259 static size_t parport_pc_epp_read_data(struct parport *port, void *buf,
260 				       size_t length, int flags)
261 {
262 	size_t got = 0;
263 
264 	if (flags & PARPORT_W91284PIC) {
265 		unsigned char status;
266 		size_t left = length;
267 
268 		/* use knowledge about data lines..:
269 		 *  nFault is 0 if there is at least 1 byte in the Warp's FIFO
270 		 *  pError is 1 if there are 16 bytes in the Warp's FIFO
271 		 */
272 		status = inb(STATUS(port));
273 
274 		while (!(status & 0x08) && got < length) {
275 			if (left >= 16 && (status & 0x20) && !(status & 0x08)) {
276 				/* can grab 16 bytes from warp fifo */
277 				if (!((long)buf & 0x03))
278 					insl(EPPDATA(port), buf, 4);
279 				else
280 					insb(EPPDATA(port), buf, 16);
281 				buf += 16;
282 				got += 16;
283 				left -= 16;
284 			} else {
285 				/* grab single byte from the warp fifo */
286 				*((char *)buf) = inb(EPPDATA(port));
287 				buf++;
288 				got++;
289 				left--;
290 			}
291 			status = inb(STATUS(port));
292 			if (status & 0x01) {
293 				/* EPP timeout should never occur... */
294 				printk(KERN_DEBUG "%s: EPP timeout occurred while talking to w91284pic (should not have done)\n",
295 				       port->name);
296 				clear_epp_timeout(port);
297 			}
298 		}
299 		return got;
300 	}
301 	if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
302 		if (!(((long)buf | length) & 0x03))
303 			insl(EPPDATA(port), buf, (length >> 2));
304 		else
305 			insb(EPPDATA(port), buf, length);
306 		if (inb(STATUS(port)) & 0x01) {
307 			clear_epp_timeout(port);
308 			return -EIO;
309 		}
310 		return length;
311 	}
312 	for (; got < length; got++) {
313 		*((char *)buf) = inb(EPPDATA(port));
314 		buf++;
315 		if (inb(STATUS(port)) & 0x01) {
316 			/* EPP timeout */
317 			clear_epp_timeout(port);
318 			break;
319 		}
320 	}
321 
322 	return got;
323 }
324 
parport_pc_epp_write_data(struct parport * port,const void * buf,size_t length,int flags)325 static size_t parport_pc_epp_write_data(struct parport *port, const void *buf,
326 					size_t length, int flags)
327 {
328 	size_t written = 0;
329 
330 	if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
331 		if (!(((long)buf | length) & 0x03))
332 			outsl(EPPDATA(port), buf, (length >> 2));
333 		else
334 			outsb(EPPDATA(port), buf, length);
335 		if (inb(STATUS(port)) & 0x01) {
336 			clear_epp_timeout(port);
337 			return -EIO;
338 		}
339 		return length;
340 	}
341 	for (; written < length; written++) {
342 		outb(*((char *)buf), EPPDATA(port));
343 		buf++;
344 		if (inb(STATUS(port)) & 0x01) {
345 			clear_epp_timeout(port);
346 			break;
347 		}
348 	}
349 
350 	return written;
351 }
352 
parport_pc_epp_read_addr(struct parport * port,void * buf,size_t length,int flags)353 static size_t parport_pc_epp_read_addr(struct parport *port, void *buf,
354 					size_t length, int flags)
355 {
356 	size_t got = 0;
357 
358 	if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
359 		insb(EPPADDR(port), buf, length);
360 		if (inb(STATUS(port)) & 0x01) {
361 			clear_epp_timeout(port);
362 			return -EIO;
363 		}
364 		return length;
365 	}
366 	for (; got < length; got++) {
367 		*((char *)buf) = inb(EPPADDR(port));
368 		buf++;
369 		if (inb(STATUS(port)) & 0x01) {
370 			clear_epp_timeout(port);
371 			break;
372 		}
373 	}
374 
375 	return got;
376 }
377 
parport_pc_epp_write_addr(struct parport * port,const void * buf,size_t length,int flags)378 static size_t parport_pc_epp_write_addr(struct parport *port,
379 					 const void *buf, size_t length,
380 					 int flags)
381 {
382 	size_t written = 0;
383 
384 	if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
385 		outsb(EPPADDR(port), buf, length);
386 		if (inb(STATUS(port)) & 0x01) {
387 			clear_epp_timeout(port);
388 			return -EIO;
389 		}
390 		return length;
391 	}
392 	for (; written < length; written++) {
393 		outb(*((char *)buf), EPPADDR(port));
394 		buf++;
395 		if (inb(STATUS(port)) & 0x01) {
396 			clear_epp_timeout(port);
397 			break;
398 		}
399 	}
400 
401 	return written;
402 }
403 
parport_pc_ecpepp_read_data(struct parport * port,void * buf,size_t length,int flags)404 static size_t parport_pc_ecpepp_read_data(struct parport *port, void *buf,
405 					  size_t length, int flags)
406 {
407 	size_t got;
408 
409 	frob_set_mode(port, ECR_EPP);
410 	parport_pc_data_reverse(port);
411 	parport_pc_write_control(port, 0x4);
412 	got = parport_pc_epp_read_data(port, buf, length, flags);
413 	frob_set_mode(port, ECR_PS2);
414 
415 	return got;
416 }
417 
parport_pc_ecpepp_write_data(struct parport * port,const void * buf,size_t length,int flags)418 static size_t parport_pc_ecpepp_write_data(struct parport *port,
419 					   const void *buf, size_t length,
420 					   int flags)
421 {
422 	size_t written;
423 
424 	frob_set_mode(port, ECR_EPP);
425 	parport_pc_write_control(port, 0x4);
426 	parport_pc_data_forward(port);
427 	written = parport_pc_epp_write_data(port, buf, length, flags);
428 	frob_set_mode(port, ECR_PS2);
429 
430 	return written;
431 }
432 
parport_pc_ecpepp_read_addr(struct parport * port,void * buf,size_t length,int flags)433 static size_t parport_pc_ecpepp_read_addr(struct parport *port, void *buf,
434 					  size_t length, int flags)
435 {
436 	size_t got;
437 
438 	frob_set_mode(port, ECR_EPP);
439 	parport_pc_data_reverse(port);
440 	parport_pc_write_control(port, 0x4);
441 	got = parport_pc_epp_read_addr(port, buf, length, flags);
442 	frob_set_mode(port, ECR_PS2);
443 
444 	return got;
445 }
446 
parport_pc_ecpepp_write_addr(struct parport * port,const void * buf,size_t length,int flags)447 static size_t parport_pc_ecpepp_write_addr(struct parport *port,
448 					    const void *buf, size_t length,
449 					    int flags)
450 {
451 	size_t written;
452 
453 	frob_set_mode(port, ECR_EPP);
454 	parport_pc_write_control(port, 0x4);
455 	parport_pc_data_forward(port);
456 	written = parport_pc_epp_write_addr(port, buf, length, flags);
457 	frob_set_mode(port, ECR_PS2);
458 
459 	return written;
460 }
461 #endif /* IEEE 1284 support */
462 
463 #ifdef CONFIG_PARPORT_PC_FIFO
parport_pc_fifo_write_block_pio(struct parport * port,const void * buf,size_t length)464 static size_t parport_pc_fifo_write_block_pio(struct parport *port,
465 					       const void *buf, size_t length)
466 {
467 	int ret = 0;
468 	const unsigned char *bufp = buf;
469 	size_t left = length;
470 	unsigned long expire = jiffies + port->physport->cad->timeout;
471 	const int fifo = FIFO(port);
472 	int poll_for = 8; /* 80 usecs */
473 	const struct parport_pc_private *priv = port->physport->private_data;
474 	const int fifo_depth = priv->fifo_depth;
475 
476 	port = port->physport;
477 
478 	/* We don't want to be interrupted every character. */
479 	parport_pc_disable_irq(port);
480 	/* set nErrIntrEn and serviceIntr */
481 	frob_econtrol(port, (1<<4) | (1<<2), (1<<4) | (1<<2));
482 
483 	/* Forward mode. */
484 	parport_pc_data_forward(port); /* Must be in PS2 mode */
485 
486 	while (left) {
487 		unsigned char byte;
488 		unsigned char ecrval = inb(ECONTROL(port));
489 		int i = 0;
490 
491 		if (need_resched() && time_before(jiffies, expire))
492 			/* Can't yield the port. */
493 			schedule();
494 
495 		/* Anyone else waiting for the port? */
496 		if (port->waithead) {
497 			printk(KERN_DEBUG "Somebody wants the port\n");
498 			break;
499 		}
500 
501 		if (ecrval & 0x02) {
502 			/* FIFO is full. Wait for interrupt. */
503 
504 			/* Clear serviceIntr */
505 			ECR_WRITE(port, ecrval & ~(1<<2));
506 false_alarm:
507 			ret = parport_wait_event(port, HZ);
508 			if (ret < 0)
509 				break;
510 			ret = 0;
511 			if (!time_before(jiffies, expire)) {
512 				/* Timed out. */
513 				printk(KERN_DEBUG "FIFO write timed out\n");
514 				break;
515 			}
516 			ecrval = inb(ECONTROL(port));
517 			if (!(ecrval & (1<<2))) {
518 				if (need_resched() &&
519 				    time_before(jiffies, expire))
520 					schedule();
521 
522 				goto false_alarm;
523 			}
524 
525 			continue;
526 		}
527 
528 		/* Can't fail now. */
529 		expire = jiffies + port->cad->timeout;
530 
531 poll:
532 		if (signal_pending(current))
533 			break;
534 
535 		if (ecrval & 0x01) {
536 			/* FIFO is empty. Blast it full. */
537 			const int n = left < fifo_depth ? left : fifo_depth;
538 			outsb(fifo, bufp, n);
539 			bufp += n;
540 			left -= n;
541 
542 			/* Adjust the poll time. */
543 			if (i < (poll_for - 2))
544 				poll_for--;
545 			continue;
546 		} else if (i++ < poll_for) {
547 			udelay(10);
548 			ecrval = inb(ECONTROL(port));
549 			goto poll;
550 		}
551 
552 		/* Half-full(call me an optimist) */
553 		byte = *bufp++;
554 		outb(byte, fifo);
555 		left--;
556 	}
557 	dump_parport_state("leave fifo_write_block_pio", port);
558 	return length - left;
559 }
560 
561 #ifdef HAS_DMA
parport_pc_fifo_write_block_dma(struct parport * port,const void * buf,size_t length)562 static size_t parport_pc_fifo_write_block_dma(struct parport *port,
563 					       const void *buf, size_t length)
564 {
565 	int ret = 0;
566 	unsigned long dmaflag;
567 	size_t left = length;
568 	const struct parport_pc_private *priv = port->physport->private_data;
569 	struct device *dev = port->physport->dev;
570 	dma_addr_t dma_addr, dma_handle;
571 	size_t maxlen = 0x10000; /* max 64k per DMA transfer */
572 	unsigned long start = (unsigned long) buf;
573 	unsigned long end = (unsigned long) buf + length - 1;
574 
575 	dump_parport_state("enter fifo_write_block_dma", port);
576 	if (end < MAX_DMA_ADDRESS) {
577 		/* If it would cross a 64k boundary, cap it at the end. */
578 		if ((start ^ end) & ~0xffffUL)
579 			maxlen = 0x10000 - (start & 0xffff);
580 
581 		dma_addr = dma_handle = dma_map_single(dev, (void *)buf, length,
582 						       DMA_TO_DEVICE);
583 	} else {
584 		/* above 16 MB we use a bounce buffer as ISA-DMA
585 		   is not possible */
586 		maxlen   = PAGE_SIZE;          /* sizeof(priv->dma_buf) */
587 		dma_addr = priv->dma_handle;
588 		dma_handle = 0;
589 	}
590 
591 	port = port->physport;
592 
593 	/* We don't want to be interrupted every character. */
594 	parport_pc_disable_irq(port);
595 	/* set nErrIntrEn and serviceIntr */
596 	frob_econtrol(port, (1<<4) | (1<<2), (1<<4) | (1<<2));
597 
598 	/* Forward mode. */
599 	parport_pc_data_forward(port); /* Must be in PS2 mode */
600 
601 	while (left) {
602 		unsigned long expire = jiffies + port->physport->cad->timeout;
603 
604 		size_t count = left;
605 
606 		if (count > maxlen)
607 			count = maxlen;
608 
609 		if (!dma_handle)   /* bounce buffer ! */
610 			memcpy(priv->dma_buf, buf, count);
611 
612 		dmaflag = claim_dma_lock();
613 		disable_dma(port->dma);
614 		clear_dma_ff(port->dma);
615 		set_dma_mode(port->dma, DMA_MODE_WRITE);
616 		set_dma_addr(port->dma, dma_addr);
617 		set_dma_count(port->dma, count);
618 
619 		/* Set DMA mode */
620 		frob_econtrol(port, 1<<3, 1<<3);
621 
622 		/* Clear serviceIntr */
623 		frob_econtrol(port, 1<<2, 0);
624 
625 		enable_dma(port->dma);
626 		release_dma_lock(dmaflag);
627 
628 		/* assume DMA will be successful */
629 		left -= count;
630 		buf  += count;
631 		if (dma_handle)
632 			dma_addr += count;
633 
634 		/* Wait for interrupt. */
635 false_alarm:
636 		ret = parport_wait_event(port, HZ);
637 		if (ret < 0)
638 			break;
639 		ret = 0;
640 		if (!time_before(jiffies, expire)) {
641 			/* Timed out. */
642 			printk(KERN_DEBUG "DMA write timed out\n");
643 			break;
644 		}
645 		/* Is serviceIntr set? */
646 		if (!(inb(ECONTROL(port)) & (1<<2))) {
647 			cond_resched();
648 
649 			goto false_alarm;
650 		}
651 
652 		dmaflag = claim_dma_lock();
653 		disable_dma(port->dma);
654 		clear_dma_ff(port->dma);
655 		count = get_dma_residue(port->dma);
656 		release_dma_lock(dmaflag);
657 
658 		cond_resched(); /* Can't yield the port. */
659 
660 		/* Anyone else waiting for the port? */
661 		if (port->waithead) {
662 			printk(KERN_DEBUG "Somebody wants the port\n");
663 			break;
664 		}
665 
666 		/* update for possible DMA residue ! */
667 		buf  -= count;
668 		left += count;
669 		if (dma_handle)
670 			dma_addr -= count;
671 	}
672 
673 	/* Maybe got here through break, so adjust for DMA residue! */
674 	dmaflag = claim_dma_lock();
675 	disable_dma(port->dma);
676 	clear_dma_ff(port->dma);
677 	left += get_dma_residue(port->dma);
678 	release_dma_lock(dmaflag);
679 
680 	/* Turn off DMA mode */
681 	frob_econtrol(port, 1<<3, 0);
682 
683 	if (dma_handle)
684 		dma_unmap_single(dev, dma_handle, length, DMA_TO_DEVICE);
685 
686 	dump_parport_state("leave fifo_write_block_dma", port);
687 	return length - left;
688 }
689 #endif
690 
parport_pc_fifo_write_block(struct parport * port,const void * buf,size_t length)691 static inline size_t parport_pc_fifo_write_block(struct parport *port,
692 					       const void *buf, size_t length)
693 {
694 #ifdef HAS_DMA
695 	if (port->dma != PARPORT_DMA_NONE)
696 		return parport_pc_fifo_write_block_dma(port, buf, length);
697 #endif
698 	return parport_pc_fifo_write_block_pio(port, buf, length);
699 }
700 
701 /* Parallel Port FIFO mode (ECP chipsets) */
parport_pc_compat_write_block_pio(struct parport * port,const void * buf,size_t length,int flags)702 static size_t parport_pc_compat_write_block_pio(struct parport *port,
703 						 const void *buf, size_t length,
704 						 int flags)
705 {
706 	size_t written;
707 	int r;
708 	unsigned long expire;
709 	const struct parport_pc_private *priv = port->physport->private_data;
710 
711 	/* Special case: a timeout of zero means we cannot call schedule().
712 	 * Also if O_NONBLOCK is set then use the default implementation. */
713 	if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
714 		return parport_ieee1284_write_compat(port, buf,
715 						      length, flags);
716 
717 	/* Set up parallel port FIFO mode.*/
718 	parport_pc_data_forward(port); /* Must be in PS2 mode */
719 	parport_pc_frob_control(port, PARPORT_CONTROL_STROBE, 0);
720 	r = change_mode(port, ECR_PPF); /* Parallel port FIFO */
721 	if (r)
722 		printk(KERN_DEBUG "%s: Warning change_mode ECR_PPF failed\n",
723 		       port->name);
724 
725 	port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
726 
727 	/* Write the data to the FIFO. */
728 	written = parport_pc_fifo_write_block(port, buf, length);
729 
730 	/* Finish up. */
731 	/* For some hardware we don't want to touch the mode until
732 	 * the FIFO is empty, so allow 4 seconds for each position
733 	 * in the fifo.
734 	 */
735 	expire = jiffies + (priv->fifo_depth * HZ * 4);
736 	do {
737 		/* Wait for the FIFO to empty */
738 		r = change_mode(port, ECR_PS2);
739 		if (r != -EBUSY)
740 			break;
741 	} while (time_before(jiffies, expire));
742 	if (r == -EBUSY) {
743 
744 		printk(KERN_DEBUG "%s: FIFO is stuck\n", port->name);
745 
746 		/* Prevent further data transfer. */
747 		frob_set_mode(port, ECR_TST);
748 
749 		/* Adjust for the contents of the FIFO. */
750 		for (written -= priv->fifo_depth; ; written++) {
751 			if (inb(ECONTROL(port)) & 0x2) {
752 				/* Full up. */
753 				break;
754 			}
755 			outb(0, FIFO(port));
756 		}
757 
758 		/* Reset the FIFO and return to PS2 mode. */
759 		frob_set_mode(port, ECR_PS2);
760 	}
761 
762 	r = parport_wait_peripheral(port,
763 				     PARPORT_STATUS_BUSY,
764 				     PARPORT_STATUS_BUSY);
765 	if (r)
766 		printk(KERN_DEBUG "%s: BUSY timeout (%d) in compat_write_block_pio\n",
767 		       port->name, r);
768 
769 	port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
770 
771 	return written;
772 }
773 
774 /* ECP */
775 #ifdef CONFIG_PARPORT_1284
parport_pc_ecp_write_block_pio(struct parport * port,const void * buf,size_t length,int flags)776 static size_t parport_pc_ecp_write_block_pio(struct parport *port,
777 					      const void *buf, size_t length,
778 					      int flags)
779 {
780 	size_t written;
781 	int r;
782 	unsigned long expire;
783 	const struct parport_pc_private *priv = port->physport->private_data;
784 
785 	/* Special case: a timeout of zero means we cannot call schedule().
786 	 * Also if O_NONBLOCK is set then use the default implementation. */
787 	if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
788 		return parport_ieee1284_ecp_write_data(port, buf,
789 							length, flags);
790 
791 	/* Switch to forward mode if necessary. */
792 	if (port->physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) {
793 		/* Event 47: Set nInit high. */
794 		parport_frob_control(port,
795 				      PARPORT_CONTROL_INIT
796 				      | PARPORT_CONTROL_AUTOFD,
797 				      PARPORT_CONTROL_INIT
798 				      | PARPORT_CONTROL_AUTOFD);
799 
800 		/* Event 49: PError goes high. */
801 		r = parport_wait_peripheral(port,
802 					     PARPORT_STATUS_PAPEROUT,
803 					     PARPORT_STATUS_PAPEROUT);
804 		if (r) {
805 			printk(KERN_DEBUG "%s: PError timeout (%d) in ecp_write_block_pio\n",
806 			       port->name, r);
807 		}
808 	}
809 
810 	/* Set up ECP parallel port mode.*/
811 	parport_pc_data_forward(port); /* Must be in PS2 mode */
812 	parport_pc_frob_control(port,
813 				 PARPORT_CONTROL_STROBE |
814 				 PARPORT_CONTROL_AUTOFD,
815 				 0);
816 	r = change_mode(port, ECR_ECP); /* ECP FIFO */
817 	if (r)
818 		printk(KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n",
819 		       port->name);
820 	port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
821 
822 	/* Write the data to the FIFO. */
823 	written = parport_pc_fifo_write_block(port, buf, length);
824 
825 	/* Finish up. */
826 	/* For some hardware we don't want to touch the mode until
827 	 * the FIFO is empty, so allow 4 seconds for each position
828 	 * in the fifo.
829 	 */
830 	expire = jiffies + (priv->fifo_depth * (HZ * 4));
831 	do {
832 		/* Wait for the FIFO to empty */
833 		r = change_mode(port, ECR_PS2);
834 		if (r != -EBUSY)
835 			break;
836 	} while (time_before(jiffies, expire));
837 	if (r == -EBUSY) {
838 
839 		printk(KERN_DEBUG "%s: FIFO is stuck\n", port->name);
840 
841 		/* Prevent further data transfer. */
842 		frob_set_mode(port, ECR_TST);
843 
844 		/* Adjust for the contents of the FIFO. */
845 		for (written -= priv->fifo_depth; ; written++) {
846 			if (inb(ECONTROL(port)) & 0x2) {
847 				/* Full up. */
848 				break;
849 			}
850 			outb(0, FIFO(port));
851 		}
852 
853 		/* Reset the FIFO and return to PS2 mode. */
854 		frob_set_mode(port, ECR_PS2);
855 
856 		/* Host transfer recovery. */
857 		parport_pc_data_reverse(port); /* Must be in PS2 mode */
858 		udelay(5);
859 		parport_frob_control(port, PARPORT_CONTROL_INIT, 0);
860 		r = parport_wait_peripheral(port, PARPORT_STATUS_PAPEROUT, 0);
861 		if (r)
862 			printk(KERN_DEBUG "%s: PE,1 timeout (%d) in ecp_write_block_pio\n",
863 			       port->name, r);
864 
865 		parport_frob_control(port,
866 				      PARPORT_CONTROL_INIT,
867 				      PARPORT_CONTROL_INIT);
868 		r = parport_wait_peripheral(port,
869 					     PARPORT_STATUS_PAPEROUT,
870 					     PARPORT_STATUS_PAPEROUT);
871 		if (r)
872 			printk(KERN_DEBUG "%s: PE,2 timeout (%d) in ecp_write_block_pio\n",
873 			       port->name, r);
874 	}
875 
876 	r = parport_wait_peripheral(port,
877 				     PARPORT_STATUS_BUSY,
878 				     PARPORT_STATUS_BUSY);
879 	if (r)
880 		printk(KERN_DEBUG "%s: BUSY timeout (%d) in ecp_write_block_pio\n",
881 		       port->name, r);
882 
883 	port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
884 
885 	return written;
886 }
887 #endif /* IEEE 1284 support */
888 #endif /* Allowed to use FIFO/DMA */
889 
890 
891 /*
892  *	******************************************
893  *	INITIALISATION AND MODULE STUFF BELOW HERE
894  *	******************************************
895  */
896 
897 /* GCC is not inlining extern inline function later overwritten to non-inline,
898    so we use outlined_ variants here.  */
899 static const struct parport_operations parport_pc_ops = {
900 	.write_data	= parport_pc_write_data,
901 	.read_data	= parport_pc_read_data,
902 
903 	.write_control	= parport_pc_write_control,
904 	.read_control	= parport_pc_read_control,
905 	.frob_control	= parport_pc_frob_control,
906 
907 	.read_status	= parport_pc_read_status,
908 
909 	.enable_irq	= parport_pc_enable_irq,
910 	.disable_irq	= parport_pc_disable_irq,
911 
912 	.data_forward	= parport_pc_data_forward,
913 	.data_reverse	= parport_pc_data_reverse,
914 
915 	.init_state	= parport_pc_init_state,
916 	.save_state	= parport_pc_save_state,
917 	.restore_state	= parport_pc_restore_state,
918 
919 	.epp_write_data	= parport_ieee1284_epp_write_data,
920 	.epp_read_data	= parport_ieee1284_epp_read_data,
921 	.epp_write_addr	= parport_ieee1284_epp_write_addr,
922 	.epp_read_addr	= parport_ieee1284_epp_read_addr,
923 
924 	.ecp_write_data	= parport_ieee1284_ecp_write_data,
925 	.ecp_read_data	= parport_ieee1284_ecp_read_data,
926 	.ecp_write_addr	= parport_ieee1284_ecp_write_addr,
927 
928 	.compat_write_data	= parport_ieee1284_write_compat,
929 	.nibble_read_data	= parport_ieee1284_read_nibble,
930 	.byte_read_data		= parport_ieee1284_read_byte,
931 
932 	.owner		= THIS_MODULE,
933 };
934 
935 #ifdef CONFIG_PARPORT_PC_SUPERIO
936 
find_free_superio(void)937 static struct superio_struct *find_free_superio(void)
938 {
939 	int i;
940 	for (i = 0; i < NR_SUPERIOS; i++)
941 		if (superios[i].io == 0)
942 			return &superios[i];
943 	return NULL;
944 }
945 
946 
947 /* Super-IO chipset detection, Winbond, SMSC */
show_parconfig_smsc37c669(int io,int key)948 static void show_parconfig_smsc37c669(int io, int key)
949 {
950 	int cr1, cr4, cra, cr23, cr26, cr27;
951 	struct superio_struct *s;
952 
953 	static const char *const modes[] = {
954 		"SPP and Bidirectional (PS/2)",
955 		"EPP and SPP",
956 		"ECP",
957 		"ECP and EPP" };
958 
959 	outb(key, io);
960 	outb(key, io);
961 	outb(1, io);
962 	cr1 = inb(io + 1);
963 	outb(4, io);
964 	cr4 = inb(io + 1);
965 	outb(0x0a, io);
966 	cra = inb(io + 1);
967 	outb(0x23, io);
968 	cr23 = inb(io + 1);
969 	outb(0x26, io);
970 	cr26 = inb(io + 1);
971 	outb(0x27, io);
972 	cr27 = inb(io + 1);
973 	outb(0xaa, io);
974 
975 	if (verbose_probing) {
976 		pr_info("SMSC 37c669 LPT Config: cr_1=0x%02x, 4=0x%02x, A=0x%2x, 23=0x%02x, 26=0x%02x, 27=0x%02x\n",
977 			cr1, cr4, cra, cr23, cr26, cr27);
978 
979 		/* The documentation calls DMA and IRQ-Lines by letters, so
980 		   the board maker can/will wire them
981 		   appropriately/randomly...  G=reserved H=IDE-irq, */
982 		pr_info("SMSC LPT Config: io=0x%04x, irq=%c, dma=%c, fifo threshold=%d\n",
983 			cr23 * 4,
984 			(cr27 & 0x0f) ? 'A' - 1 + (cr27 & 0x0f) : '-',
985 			(cr26 & 0x0f) ? 'A' - 1 + (cr26 & 0x0f) : '-',
986 			cra & 0x0f);
987 		pr_info("SMSC LPT Config: enabled=%s power=%s\n",
988 			(cr23 * 4 >= 0x100) ? "yes" : "no",
989 			(cr1 & 4) ? "yes" : "no");
990 		pr_info("SMSC LPT Config: Port mode=%s, EPP version =%s\n",
991 			(cr1 & 0x08) ? "Standard mode only (SPP)"
992 			: modes[cr4 & 0x03],
993 			(cr4 & 0x40) ? "1.7" : "1.9");
994 	}
995 
996 	/* Heuristics !  BIOS setup for this mainboard device limits
997 	   the choices to standard settings, i.e. io-address and IRQ
998 	   are related, however DMA can be 1 or 3, assume DMA_A=DMA1,
999 	   DMA_C=DMA3 (this is true e.g. for TYAN 1564D Tomcat IV) */
1000 	if (cr23 * 4 >= 0x100) { /* if active */
1001 		s = find_free_superio();
1002 		if (s == NULL)
1003 			pr_info("Super-IO: too many chips!\n");
1004 		else {
1005 			int d;
1006 			switch (cr23 * 4) {
1007 			case 0x3bc:
1008 				s->io = 0x3bc;
1009 				s->irq = 7;
1010 				break;
1011 			case 0x378:
1012 				s->io = 0x378;
1013 				s->irq = 7;
1014 				break;
1015 			case 0x278:
1016 				s->io = 0x278;
1017 				s->irq = 5;
1018 			}
1019 			d = (cr26 & 0x0f);
1020 			if (d == 1 || d == 3)
1021 				s->dma = d;
1022 			else
1023 				s->dma = PARPORT_DMA_NONE;
1024 		}
1025 	}
1026 }
1027 
1028 
show_parconfig_winbond(int io,int key)1029 static void show_parconfig_winbond(int io, int key)
1030 {
1031 	int cr30, cr60, cr61, cr70, cr74, crf0;
1032 	struct superio_struct *s;
1033 	static const char *const modes[] = {
1034 		"Standard (SPP) and Bidirectional(PS/2)", /* 0 */
1035 		"EPP-1.9 and SPP",
1036 		"ECP",
1037 		"ECP and EPP-1.9",
1038 		"Standard (SPP)",
1039 		"EPP-1.7 and SPP",		/* 5 */
1040 		"undefined!",
1041 		"ECP and EPP-1.7" };
1042 	static char *const irqtypes[] = {
1043 		"pulsed low, high-Z",
1044 		"follows nACK" };
1045 
1046 	/* The registers are called compatible-PnP because the
1047 	   register layout is modelled after ISA-PnP, the access
1048 	   method is just another ... */
1049 	outb(key, io);
1050 	outb(key, io);
1051 	outb(0x07, io);   /* Register 7: Select Logical Device */
1052 	outb(0x01, io + 1); /* LD1 is Parallel Port */
1053 	outb(0x30, io);
1054 	cr30 = inb(io + 1);
1055 	outb(0x60, io);
1056 	cr60 = inb(io + 1);
1057 	outb(0x61, io);
1058 	cr61 = inb(io + 1);
1059 	outb(0x70, io);
1060 	cr70 = inb(io + 1);
1061 	outb(0x74, io);
1062 	cr74 = inb(io + 1);
1063 	outb(0xf0, io);
1064 	crf0 = inb(io + 1);
1065 	outb(0xaa, io);
1066 
1067 	if (verbose_probing) {
1068 		pr_info("Winbond LPT Config: cr_30=%02x 60,61=%02x%02x 70=%02x 74=%02x, f0=%02x\n",
1069 			cr30, cr60, cr61, cr70, cr74, crf0);
1070 		pr_info("Winbond LPT Config: active=%s, io=0x%02x%02x irq=%d, ",
1071 			(cr30 & 0x01) ? "yes" : "no", cr60, cr61, cr70 & 0x0f);
1072 		if ((cr74 & 0x07) > 3)
1073 			pr_cont("dma=none\n");
1074 		else
1075 			pr_cont("dma=%d\n", cr74 & 0x07);
1076 		pr_info("Winbond LPT Config: irqtype=%s, ECP fifo threshold=%d\n",
1077 			irqtypes[crf0 >> 7], (crf0 >> 3) & 0x0f);
1078 		pr_info("Winbond LPT Config: Port mode=%s\n",
1079 			modes[crf0 & 0x07]);
1080 	}
1081 
1082 	if (cr30 & 0x01) { /* the settings can be interrogated later ... */
1083 		s = find_free_superio();
1084 		if (s == NULL)
1085 			pr_info("Super-IO: too many chips!\n");
1086 		else {
1087 			s->io = (cr60 << 8) | cr61;
1088 			s->irq = cr70 & 0x0f;
1089 			s->dma = (((cr74 & 0x07) > 3) ?
1090 					   PARPORT_DMA_NONE : (cr74 & 0x07));
1091 		}
1092 	}
1093 }
1094 
decode_winbond(int efer,int key,int devid,int devrev,int oldid)1095 static void decode_winbond(int efer, int key, int devid, int devrev, int oldid)
1096 {
1097 	const char *type = "unknown";
1098 	int id, progif = 2;
1099 
1100 	if (devid == devrev)
1101 		/* simple heuristics, we happened to read some
1102 		   non-winbond register */
1103 		return;
1104 
1105 	id = (devid << 8) | devrev;
1106 
1107 	/* Values are from public data sheets pdf files, I can just
1108 	   confirm 83977TF is correct :-) */
1109 	if (id == 0x9771)
1110 		type = "83977F/AF";
1111 	else if (id == 0x9773)
1112 		type = "83977TF / SMSC 97w33x/97w34x";
1113 	else if (id == 0x9774)
1114 		type = "83977ATF";
1115 	else if ((id & ~0x0f) == 0x5270)
1116 		type = "83977CTF / SMSC 97w36x";
1117 	else if ((id & ~0x0f) == 0x52f0)
1118 		type = "83977EF / SMSC 97w35x";
1119 	else if ((id & ~0x0f) == 0x5210)
1120 		type = "83627";
1121 	else if ((id & ~0x0f) == 0x6010)
1122 		type = "83697HF";
1123 	else if ((oldid & 0x0f) == 0x0a) {
1124 		type = "83877F";
1125 		progif = 1;
1126 	} else if ((oldid & 0x0f) == 0x0b) {
1127 		type = "83877AF";
1128 		progif = 1;
1129 	} else if ((oldid & 0x0f) == 0x0c) {
1130 		type = "83877TF";
1131 		progif = 1;
1132 	} else if ((oldid & 0x0f) == 0x0d) {
1133 		type = "83877ATF";
1134 		progif = 1;
1135 	} else
1136 		progif = 0;
1137 
1138 	if (verbose_probing)
1139 		pr_info("Winbond chip at EFER=0x%x key=0x%02x devid=%02x devrev=%02x oldid=%02x type=%s\n",
1140 			efer, key, devid, devrev, oldid, type);
1141 
1142 	if (progif == 2)
1143 		show_parconfig_winbond(efer, key);
1144 }
1145 
decode_smsc(int efer,int key,int devid,int devrev)1146 static void decode_smsc(int efer, int key, int devid, int devrev)
1147 {
1148 	const char *type = "unknown";
1149 	void (*func)(int io, int key);
1150 	int id;
1151 
1152 	if (devid == devrev)
1153 		/* simple heuristics, we happened to read some
1154 		   non-smsc register */
1155 		return;
1156 
1157 	func = NULL;
1158 	id = (devid << 8) | devrev;
1159 
1160 	if (id == 0x0302) {
1161 		type = "37c669";
1162 		func = show_parconfig_smsc37c669;
1163 	} else if (id == 0x6582)
1164 		type = "37c665IR";
1165 	else if	(devid == 0x65)
1166 		type = "37c665GT";
1167 	else if	(devid == 0x66)
1168 		type = "37c666GT";
1169 
1170 	if (verbose_probing)
1171 		pr_info("SMSC chip at EFER=0x%x key=0x%02x devid=%02x devrev=%02x type=%s\n",
1172 			efer, key, devid, devrev, type);
1173 
1174 	if (func)
1175 		func(efer, key);
1176 }
1177 
1178 
winbond_check(int io,int key)1179 static void winbond_check(int io, int key)
1180 {
1181 	int origval, devid, devrev, oldid, x_devid, x_devrev, x_oldid;
1182 
1183 	if (!request_region(io, 3, __func__))
1184 		return;
1185 
1186 	origval = inb(io); /* Save original value */
1187 
1188 	/* First probe without key */
1189 	outb(0x20, io);
1190 	x_devid = inb(io + 1);
1191 	outb(0x21, io);
1192 	x_devrev = inb(io + 1);
1193 	outb(0x09, io);
1194 	x_oldid = inb(io + 1);
1195 
1196 	outb(key, io);
1197 	outb(key, io);     /* Write Magic Sequence to EFER, extended
1198 			      function enable register */
1199 	outb(0x20, io);    /* Write EFIR, extended function index register */
1200 	devid = inb(io + 1);  /* Read EFDR, extended function data register */
1201 	outb(0x21, io);
1202 	devrev = inb(io + 1);
1203 	outb(0x09, io);
1204 	oldid = inb(io + 1);
1205 	outb(0xaa, io);    /* Magic Seal */
1206 
1207 	outb(origval, io); /* in case we poked some entirely different hardware */
1208 
1209 	if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid))
1210 		goto out; /* protection against false positives */
1211 
1212 	decode_winbond(io, key, devid, devrev, oldid);
1213 out:
1214 	release_region(io, 3);
1215 }
1216 
winbond_check2(int io,int key)1217 static void winbond_check2(int io, int key)
1218 {
1219 	int origval[3], devid, devrev, oldid, x_devid, x_devrev, x_oldid;
1220 
1221 	if (!request_region(io, 3, __func__))
1222 		return;
1223 
1224 	origval[0] = inb(io); /* Save original values */
1225 	origval[1] = inb(io + 1);
1226 	origval[2] = inb(io + 2);
1227 
1228 	/* First probe without the key */
1229 	outb(0x20, io + 2);
1230 	x_devid = inb(io + 2);
1231 	outb(0x21, io + 1);
1232 	x_devrev = inb(io + 2);
1233 	outb(0x09, io + 1);
1234 	x_oldid = inb(io + 2);
1235 
1236 	outb(key, io);     /* Write Magic Byte to EFER, extended
1237 			      function enable register */
1238 	outb(0x20, io + 2);  /* Write EFIR, extended function index register */
1239 	devid = inb(io + 2);  /* Read EFDR, extended function data register */
1240 	outb(0x21, io + 1);
1241 	devrev = inb(io + 2);
1242 	outb(0x09, io + 1);
1243 	oldid = inb(io + 2);
1244 	outb(0xaa, io);    /* Magic Seal */
1245 
1246 	outb(origval[0], io); /* in case we poked some entirely different hardware */
1247 	outb(origval[1], io + 1);
1248 	outb(origval[2], io + 2);
1249 
1250 	if (x_devid == devid && x_devrev == devrev && x_oldid == oldid)
1251 		goto out; /* protection against false positives */
1252 
1253 	decode_winbond(io, key, devid, devrev, oldid);
1254 out:
1255 	release_region(io, 3);
1256 }
1257 
smsc_check(int io,int key)1258 static void smsc_check(int io, int key)
1259 {
1260 	int origval, id, rev, oldid, oldrev, x_id, x_rev, x_oldid, x_oldrev;
1261 
1262 	if (!request_region(io, 3, __func__))
1263 		return;
1264 
1265 	origval = inb(io); /* Save original value */
1266 
1267 	/* First probe without the key */
1268 	outb(0x0d, io);
1269 	x_oldid = inb(io + 1);
1270 	outb(0x0e, io);
1271 	x_oldrev = inb(io + 1);
1272 	outb(0x20, io);
1273 	x_id = inb(io + 1);
1274 	outb(0x21, io);
1275 	x_rev = inb(io + 1);
1276 
1277 	outb(key, io);
1278 	outb(key, io);     /* Write Magic Sequence to EFER, extended
1279 			      function enable register */
1280 	outb(0x0d, io);    /* Write EFIR, extended function index register */
1281 	oldid = inb(io + 1);  /* Read EFDR, extended function data register */
1282 	outb(0x0e, io);
1283 	oldrev = inb(io + 1);
1284 	outb(0x20, io);
1285 	id = inb(io + 1);
1286 	outb(0x21, io);
1287 	rev = inb(io + 1);
1288 	outb(0xaa, io);    /* Magic Seal */
1289 
1290 	outb(origval, io); /* in case we poked some entirely different hardware */
1291 
1292 	if (x_id == id && x_oldrev == oldrev &&
1293 	    x_oldid == oldid && x_rev == rev)
1294 		goto out; /* protection against false positives */
1295 
1296 	decode_smsc(io, key, oldid, oldrev);
1297 out:
1298 	release_region(io, 3);
1299 }
1300 
1301 
detect_and_report_winbond(void)1302 static void detect_and_report_winbond(void)
1303 {
1304 	if (verbose_probing)
1305 		printk(KERN_DEBUG "Winbond Super-IO detection, now testing ports 3F0,370,250,4E,2E ...\n");
1306 	winbond_check(0x3f0, 0x87);
1307 	winbond_check(0x370, 0x87);
1308 	winbond_check(0x2e , 0x87);
1309 	winbond_check(0x4e , 0x87);
1310 	winbond_check(0x3f0, 0x86);
1311 	winbond_check2(0x250, 0x88);
1312 	winbond_check2(0x250, 0x89);
1313 }
1314 
detect_and_report_smsc(void)1315 static void detect_and_report_smsc(void)
1316 {
1317 	if (verbose_probing)
1318 		printk(KERN_DEBUG "SMSC Super-IO detection, now testing Ports 2F0, 370 ...\n");
1319 	smsc_check(0x3f0, 0x55);
1320 	smsc_check(0x370, 0x55);
1321 	smsc_check(0x3f0, 0x44);
1322 	smsc_check(0x370, 0x44);
1323 }
1324 
detect_and_report_it87(void)1325 static void detect_and_report_it87(void)
1326 {
1327 	u16 dev;
1328 	u8 origval, r;
1329 	if (verbose_probing)
1330 		printk(KERN_DEBUG "IT8705 Super-IO detection, now testing port 2E ...\n");
1331 	if (!request_muxed_region(0x2e, 2, __func__))
1332 		return;
1333 	origval = inb(0x2e);		/* Save original value */
1334 	outb(0x87, 0x2e);
1335 	outb(0x01, 0x2e);
1336 	outb(0x55, 0x2e);
1337 	outb(0x55, 0x2e);
1338 	outb(0x20, 0x2e);
1339 	dev = inb(0x2f) << 8;
1340 	outb(0x21, 0x2e);
1341 	dev |= inb(0x2f);
1342 	if (dev == 0x8712 || dev == 0x8705 || dev == 0x8715 ||
1343 	    dev == 0x8716 || dev == 0x8718 || dev == 0x8726) {
1344 		pr_info("IT%04X SuperIO detected\n", dev);
1345 		outb(0x07, 0x2E);	/* Parallel Port */
1346 		outb(0x03, 0x2F);
1347 		outb(0xF0, 0x2E);	/* BOOT 0x80 off */
1348 		r = inb(0x2f);
1349 		outb(0xF0, 0x2E);
1350 		outb(r | 8, 0x2F);
1351 		outb(0x02, 0x2E);	/* Lock */
1352 		outb(0x02, 0x2F);
1353 	} else {
1354 		outb(origval, 0x2e);	/* Oops, sorry to disturb */
1355 	}
1356 	release_region(0x2e, 2);
1357 }
1358 #endif /* CONFIG_PARPORT_PC_SUPERIO */
1359 
find_superio(struct parport * p)1360 static struct superio_struct *find_superio(struct parport *p)
1361 {
1362 	int i;
1363 	for (i = 0; i < NR_SUPERIOS; i++)
1364 		if (superios[i].io == p->base)
1365 			return &superios[i];
1366 	return NULL;
1367 }
1368 
get_superio_dma(struct parport * p)1369 static int get_superio_dma(struct parport *p)
1370 {
1371 	struct superio_struct *s = find_superio(p);
1372 	if (s)
1373 		return s->dma;
1374 	return PARPORT_DMA_NONE;
1375 }
1376 
get_superio_irq(struct parport * p)1377 static int get_superio_irq(struct parport *p)
1378 {
1379 	struct superio_struct *s = find_superio(p);
1380 	if (s)
1381 		return s->irq;
1382 	return PARPORT_IRQ_NONE;
1383 }
1384 
1385 
1386 /* --- Mode detection ------------------------------------- */
1387 
1388 /*
1389  * Checks for port existence, all ports support SPP MODE
1390  * Returns:
1391  *         0           :  No parallel port at this address
1392  *  PARPORT_MODE_PCSPP :  SPP port detected
1393  *                        (if the user specified an ioport himself,
1394  *                         this shall always be the case!)
1395  *
1396  */
parport_SPP_supported(struct parport * pb)1397 static int parport_SPP_supported(struct parport *pb)
1398 {
1399 	unsigned char r, w;
1400 
1401 	/*
1402 	 * first clear an eventually pending EPP timeout
1403 	 * I (sailer@ife.ee.ethz.ch) have an SMSC chipset
1404 	 * that does not even respond to SPP cycles if an EPP
1405 	 * timeout is pending
1406 	 */
1407 	clear_epp_timeout(pb);
1408 
1409 	/* Do a simple read-write test to make sure the port exists. */
1410 	w = 0xc;
1411 	outb(w, CONTROL(pb));
1412 
1413 	/* Is there a control register that we can read from?  Some
1414 	 * ports don't allow reads, so read_control just returns a
1415 	 * software copy. Some ports _do_ allow reads, so bypass the
1416 	 * software copy here.  In addition, some bits aren't
1417 	 * writable. */
1418 	r = inb(CONTROL(pb));
1419 	if ((r & 0xf) == w) {
1420 		w = 0xe;
1421 		outb(w, CONTROL(pb));
1422 		r = inb(CONTROL(pb));
1423 		outb(0xc, CONTROL(pb));
1424 		if ((r & 0xf) == w)
1425 			return PARPORT_MODE_PCSPP;
1426 	}
1427 
1428 	if (user_specified)
1429 		/* That didn't work, but the user thinks there's a
1430 		 * port here. */
1431 		pr_info("parport 0x%lx (WARNING): CTR: wrote 0x%02x, read 0x%02x\n",
1432 			pb->base, w, r);
1433 
1434 	/* Try the data register.  The data lines aren't tri-stated at
1435 	 * this stage, so we expect back what we wrote. */
1436 	w = 0xaa;
1437 	parport_pc_write_data(pb, w);
1438 	r = parport_pc_read_data(pb);
1439 	if (r == w) {
1440 		w = 0x55;
1441 		parport_pc_write_data(pb, w);
1442 		r = parport_pc_read_data(pb);
1443 		if (r == w)
1444 			return PARPORT_MODE_PCSPP;
1445 	}
1446 
1447 	if (user_specified) {
1448 		/* Didn't work, but the user is convinced this is the
1449 		 * place. */
1450 		pr_info("parport 0x%lx (WARNING): DATA: wrote 0x%02x, read 0x%02x\n",
1451 			pb->base, w, r);
1452 		pr_info("parport 0x%lx: You gave this address, but there is probably no parallel port there!\n",
1453 			pb->base);
1454 	}
1455 
1456 	/* It's possible that we can't read the control register or
1457 	 * the data register.  In that case just believe the user. */
1458 	if (user_specified)
1459 		return PARPORT_MODE_PCSPP;
1460 
1461 	return 0;
1462 }
1463 
1464 /* Check for ECR
1465  *
1466  * Old style XT ports alias io ports every 0x400, hence accessing ECR
1467  * on these cards actually accesses the CTR.
1468  *
1469  * Modern cards don't do this but reading from ECR will return 0xff
1470  * regardless of what is written here if the card does NOT support
1471  * ECP.
1472  *
1473  * We first check to see if ECR is the same as CTR.  If not, the low
1474  * two bits of ECR aren't writable, so we check by writing ECR and
1475  * reading it back to see if it's what we expect.
1476  */
parport_ECR_present(struct parport * pb)1477 static int parport_ECR_present(struct parport *pb)
1478 {
1479 	struct parport_pc_private *priv = pb->private_data;
1480 	unsigned char r = 0xc;
1481 
1482 	outb(r, CONTROL(pb));
1483 	if ((inb(ECONTROL(pb)) & 0x3) == (r & 0x3)) {
1484 		outb(r ^ 0x2, CONTROL(pb)); /* Toggle bit 1 */
1485 
1486 		r = inb(CONTROL(pb));
1487 		if ((inb(ECONTROL(pb)) & 0x2) == (r & 0x2))
1488 			goto no_reg; /* Sure that no ECR register exists */
1489 	}
1490 
1491 	if ((inb(ECONTROL(pb)) & 0x3) != 0x1)
1492 		goto no_reg;
1493 
1494 	ECR_WRITE(pb, 0x34);
1495 	if (inb(ECONTROL(pb)) != 0x35)
1496 		goto no_reg;
1497 
1498 	priv->ecr = 1;
1499 	outb(0xc, CONTROL(pb));
1500 
1501 	/* Go to mode 000 */
1502 	frob_set_mode(pb, ECR_SPP);
1503 
1504 	return 1;
1505 
1506  no_reg:
1507 	outb(0xc, CONTROL(pb));
1508 	return 0;
1509 }
1510 
1511 #ifdef CONFIG_PARPORT_1284
1512 /* Detect PS/2 support.
1513  *
1514  * Bit 5 (0x20) sets the PS/2 data direction; setting this high
1515  * allows us to read data from the data lines.  In theory we would get back
1516  * 0xff but any peripheral attached to the port may drag some or all of the
1517  * lines down to zero.  So if we get back anything that isn't the contents
1518  * of the data register we deem PS/2 support to be present.
1519  *
1520  * Some SPP ports have "half PS/2" ability - you can't turn off the line
1521  * drivers, but an external peripheral with sufficiently beefy drivers of
1522  * its own can overpower them and assert its own levels onto the bus, from
1523  * where they can then be read back as normal.  Ports with this property
1524  * and the right type of device attached are likely to fail the SPP test,
1525  * (as they will appear to have stuck bits) and so the fact that they might
1526  * be misdetected here is rather academic.
1527  */
1528 
parport_PS2_supported(struct parport * pb)1529 static int parport_PS2_supported(struct parport *pb)
1530 {
1531 	int ok = 0;
1532 
1533 	clear_epp_timeout(pb);
1534 
1535 	/* try to tri-state the buffer */
1536 	parport_pc_data_reverse(pb);
1537 
1538 	parport_pc_write_data(pb, 0x55);
1539 	if (parport_pc_read_data(pb) != 0x55)
1540 		ok++;
1541 
1542 	parport_pc_write_data(pb, 0xaa);
1543 	if (parport_pc_read_data(pb) != 0xaa)
1544 		ok++;
1545 
1546 	/* cancel input mode */
1547 	parport_pc_data_forward(pb);
1548 
1549 	if (ok) {
1550 		pb->modes |= PARPORT_MODE_TRISTATE;
1551 	} else {
1552 		struct parport_pc_private *priv = pb->private_data;
1553 		priv->ctr_writable &= ~0x20;
1554 	}
1555 
1556 	return ok;
1557 }
1558 
1559 #ifdef CONFIG_PARPORT_PC_FIFO
parport_ECP_supported(struct parport * pb)1560 static int parport_ECP_supported(struct parport *pb)
1561 {
1562 	int i;
1563 	int config, configb;
1564 	int pword;
1565 	struct parport_pc_private *priv = pb->private_data;
1566 	/* Translate ECP intrLine to ISA irq value */
1567 	static const int intrline[] = { 0, 7, 9, 10, 11, 14, 15, 5 };
1568 
1569 	/* If there is no ECR, we have no hope of supporting ECP. */
1570 	if (!priv->ecr)
1571 		return 0;
1572 
1573 	/* Find out FIFO depth */
1574 	ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */
1575 	ECR_WRITE(pb, ECR_TST << 5); /* TEST FIFO */
1576 	for (i = 0; i < 1024 && !(inb(ECONTROL(pb)) & 0x02); i++)
1577 		outb(0xaa, FIFO(pb));
1578 
1579 	/*
1580 	 * Using LGS chipset it uses ECR register, but
1581 	 * it doesn't support ECP or FIFO MODE
1582 	 */
1583 	if (i == 1024) {
1584 		ECR_WRITE(pb, ECR_SPP << 5);
1585 		return 0;
1586 	}
1587 
1588 	priv->fifo_depth = i;
1589 	if (verbose_probing)
1590 		printk(KERN_DEBUG "0x%lx: FIFO is %d bytes\n", pb->base, i);
1591 
1592 	/* Find out writeIntrThreshold */
1593 	frob_econtrol(pb, 1<<2, 1<<2);
1594 	frob_econtrol(pb, 1<<2, 0);
1595 	for (i = 1; i <= priv->fifo_depth; i++) {
1596 		inb(FIFO(pb));
1597 		udelay(50);
1598 		if (inb(ECONTROL(pb)) & (1<<2))
1599 			break;
1600 	}
1601 
1602 	if (i <= priv->fifo_depth) {
1603 		if (verbose_probing)
1604 			printk(KERN_DEBUG "0x%lx: writeIntrThreshold is %d\n",
1605 			       pb->base, i);
1606 	} else
1607 		/* Number of bytes we know we can write if we get an
1608 		   interrupt. */
1609 		i = 0;
1610 
1611 	priv->writeIntrThreshold = i;
1612 
1613 	/* Find out readIntrThreshold */
1614 	frob_set_mode(pb, ECR_PS2); /* Reset FIFO and enable PS2 */
1615 	parport_pc_data_reverse(pb); /* Must be in PS2 mode */
1616 	frob_set_mode(pb, ECR_TST); /* Test FIFO */
1617 	frob_econtrol(pb, 1<<2, 1<<2);
1618 	frob_econtrol(pb, 1<<2, 0);
1619 	for (i = 1; i <= priv->fifo_depth; i++) {
1620 		outb(0xaa, FIFO(pb));
1621 		if (inb(ECONTROL(pb)) & (1<<2))
1622 			break;
1623 	}
1624 
1625 	if (i <= priv->fifo_depth) {
1626 		if (verbose_probing)
1627 			pr_info("0x%lx: readIntrThreshold is %d\n",
1628 				pb->base, i);
1629 	} else
1630 		/* Number of bytes we can read if we get an interrupt. */
1631 		i = 0;
1632 
1633 	priv->readIntrThreshold = i;
1634 
1635 	ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */
1636 	ECR_WRITE(pb, 0xf4); /* Configuration mode */
1637 	config = inb(CONFIGA(pb));
1638 	pword = (config >> 4) & 0x7;
1639 	switch (pword) {
1640 	case 0:
1641 		pword = 2;
1642 		pr_warn("0x%lx: Unsupported pword size!\n", pb->base);
1643 		break;
1644 	case 2:
1645 		pword = 4;
1646 		pr_warn("0x%lx: Unsupported pword size!\n", pb->base);
1647 		break;
1648 	default:
1649 		pr_warn("0x%lx: Unknown implementation ID\n", pb->base);
1650 		fallthrough;	/* Assume 1 */
1651 	case 1:
1652 		pword = 1;
1653 	}
1654 	priv->pword = pword;
1655 
1656 	if (verbose_probing) {
1657 		printk(KERN_DEBUG "0x%lx: PWord is %d bits\n",
1658 		       pb->base, 8 * pword);
1659 
1660 		printk(KERN_DEBUG "0x%lx: Interrupts are ISA-%s\n",
1661 		       pb->base, config & 0x80 ? "Level" : "Pulses");
1662 
1663 		configb = inb(CONFIGB(pb));
1664 		printk(KERN_DEBUG "0x%lx: ECP port cfgA=0x%02x cfgB=0x%02x\n",
1665 		       pb->base, config, configb);
1666 		printk(KERN_DEBUG "0x%lx: ECP settings irq=", pb->base);
1667 		if ((configb >> 3) & 0x07)
1668 			pr_cont("%d", intrline[(configb >> 3) & 0x07]);
1669 		else
1670 			pr_cont("<none or set by other means>");
1671 		pr_cont(" dma=");
1672 		if ((configb & 0x03) == 0x00)
1673 			pr_cont("<none or set by other means>\n");
1674 		else
1675 			pr_cont("%d\n", configb & 0x07);
1676 	}
1677 
1678 	/* Go back to mode 000 */
1679 	frob_set_mode(pb, ECR_SPP);
1680 
1681 	return 1;
1682 }
1683 #endif
1684 
1685 #ifdef CONFIG_X86_32
intel_bug_present_check_epp(struct parport * pb)1686 static int intel_bug_present_check_epp(struct parport *pb)
1687 {
1688 	const struct parport_pc_private *priv = pb->private_data;
1689 	int bug_present = 0;
1690 
1691 	if (priv->ecr) {
1692 		/* store value of ECR */
1693 		unsigned char ecr = inb(ECONTROL(pb));
1694 		unsigned char i;
1695 		for (i = 0x00; i < 0x80; i += 0x20) {
1696 			ECR_WRITE(pb, i);
1697 			if (clear_epp_timeout(pb)) {
1698 				/* Phony EPP in ECP. */
1699 				bug_present = 1;
1700 				break;
1701 			}
1702 		}
1703 		/* return ECR into the inital state */
1704 		ECR_WRITE(pb, ecr);
1705 	}
1706 
1707 	return bug_present;
1708 }
intel_bug_present(struct parport * pb)1709 static int intel_bug_present(struct parport *pb)
1710 {
1711 /* Check whether the device is legacy, not PCI or PCMCIA. Only legacy is known to be affected. */
1712 	if (pb->dev != NULL) {
1713 		return 0;
1714 	}
1715 
1716 	return intel_bug_present_check_epp(pb);
1717 }
1718 #else
intel_bug_present(struct parport * pb)1719 static int intel_bug_present(struct parport *pb)
1720 {
1721 	return 0;
1722 }
1723 #endif /* CONFIG_X86_32 */
1724 
parport_ECPPS2_supported(struct parport * pb)1725 static int parport_ECPPS2_supported(struct parport *pb)
1726 {
1727 	const struct parport_pc_private *priv = pb->private_data;
1728 	int result;
1729 	unsigned char oecr;
1730 
1731 	if (!priv->ecr)
1732 		return 0;
1733 
1734 	oecr = inb(ECONTROL(pb));
1735 	ECR_WRITE(pb, ECR_PS2 << 5);
1736 	result = parport_PS2_supported(pb);
1737 	ECR_WRITE(pb, oecr);
1738 	return result;
1739 }
1740 
1741 /* EPP mode detection  */
1742 
parport_EPP_supported(struct parport * pb)1743 static int parport_EPP_supported(struct parport *pb)
1744 {
1745 	/*
1746 	 * Theory:
1747 	 *	Bit 0 of STR is the EPP timeout bit, this bit is 0
1748 	 *	when EPP is possible and is set high when an EPP timeout
1749 	 *	occurs (EPP uses the HALT line to stop the CPU while it does
1750 	 *	the byte transfer, an EPP timeout occurs if the attached
1751 	 *	device fails to respond after 10 micro seconds).
1752 	 *
1753 	 *	This bit is cleared by either reading it (National Semi)
1754 	 *	or writing a 1 to the bit (SMC, UMC, WinBond), others ???
1755 	 *	This bit is always high in non EPP modes.
1756 	 */
1757 
1758 	/* If EPP timeout bit clear then EPP available */
1759 	if (!clear_epp_timeout(pb))
1760 		return 0;  /* No way to clear timeout */
1761 
1762 	/* Check for Intel bug. */
1763 	if (intel_bug_present(pb))
1764 		return 0;
1765 
1766 	pb->modes |= PARPORT_MODE_EPP;
1767 
1768 	/* Set up access functions to use EPP hardware. */
1769 	pb->ops->epp_read_data = parport_pc_epp_read_data;
1770 	pb->ops->epp_write_data = parport_pc_epp_write_data;
1771 	pb->ops->epp_read_addr = parport_pc_epp_read_addr;
1772 	pb->ops->epp_write_addr = parport_pc_epp_write_addr;
1773 
1774 	return 1;
1775 }
1776 
parport_ECPEPP_supported(struct parport * pb)1777 static int parport_ECPEPP_supported(struct parport *pb)
1778 {
1779 	struct parport_pc_private *priv = pb->private_data;
1780 	int result;
1781 	unsigned char oecr;
1782 
1783 	if (!priv->ecr)
1784 		return 0;
1785 
1786 	oecr = inb(ECONTROL(pb));
1787 	/* Search for SMC style EPP+ECP mode */
1788 	ECR_WRITE(pb, 0x80);
1789 	outb(0x04, CONTROL(pb));
1790 	result = parport_EPP_supported(pb);
1791 
1792 	ECR_WRITE(pb, oecr);
1793 
1794 	if (result) {
1795 		/* Set up access functions to use ECP+EPP hardware. */
1796 		pb->ops->epp_read_data = parport_pc_ecpepp_read_data;
1797 		pb->ops->epp_write_data = parport_pc_ecpepp_write_data;
1798 		pb->ops->epp_read_addr = parport_pc_ecpepp_read_addr;
1799 		pb->ops->epp_write_addr = parport_pc_ecpepp_write_addr;
1800 	}
1801 
1802 	return result;
1803 }
1804 
1805 #else /* No IEEE 1284 support */
1806 
1807 /* Don't bother probing for modes we know we won't use. */
parport_PS2_supported(struct parport * pb)1808 static int parport_PS2_supported(struct parport *pb) { return 0; }
1809 #ifdef CONFIG_PARPORT_PC_FIFO
parport_ECP_supported(struct parport * pb)1810 static int parport_ECP_supported(struct parport *pb)
1811 {
1812 	return 0;
1813 }
1814 #endif
parport_EPP_supported(struct parport * pb)1815 static int parport_EPP_supported(struct parport *pb)
1816 {
1817 	return 0;
1818 }
1819 
parport_ECPEPP_supported(struct parport * pb)1820 static int parport_ECPEPP_supported(struct parport *pb)
1821 {
1822 	return 0;
1823 }
1824 
parport_ECPPS2_supported(struct parport * pb)1825 static int parport_ECPPS2_supported(struct parport *pb)
1826 {
1827 	return 0;
1828 }
1829 
1830 #endif /* No IEEE 1284 support */
1831 
1832 /* --- IRQ detection -------------------------------------- */
1833 
1834 /* Only if supports ECP mode */
programmable_irq_support(struct parport * pb)1835 static int programmable_irq_support(struct parport *pb)
1836 {
1837 	int irq, intrLine;
1838 	unsigned char oecr = inb(ECONTROL(pb));
1839 	static const int lookup[8] = {
1840 		PARPORT_IRQ_NONE, 7, 9, 10, 11, 14, 15, 5
1841 	};
1842 
1843 	ECR_WRITE(pb, ECR_CNF << 5); /* Configuration MODE */
1844 
1845 	intrLine = (inb(CONFIGB(pb)) >> 3) & 0x07;
1846 	irq = lookup[intrLine];
1847 
1848 	ECR_WRITE(pb, oecr);
1849 	return irq;
1850 }
1851 
irq_probe_ECP(struct parport * pb)1852 static int irq_probe_ECP(struct parport *pb)
1853 {
1854 	int i;
1855 	unsigned long irqs;
1856 
1857 	irqs = probe_irq_on();
1858 
1859 	ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */
1860 	ECR_WRITE(pb, (ECR_TST << 5) | 0x04);
1861 	ECR_WRITE(pb, ECR_TST << 5);
1862 
1863 	/* If Full FIFO sure that writeIntrThreshold is generated */
1864 	for (i = 0; i < 1024 && !(inb(ECONTROL(pb)) & 0x02) ; i++)
1865 		outb(0xaa, FIFO(pb));
1866 
1867 	pb->irq = probe_irq_off(irqs);
1868 	ECR_WRITE(pb, ECR_SPP << 5);
1869 
1870 	if (pb->irq <= 0)
1871 		pb->irq = PARPORT_IRQ_NONE;
1872 
1873 	return pb->irq;
1874 }
1875 
1876 /*
1877  * This detection seems that only works in National Semiconductors
1878  * This doesn't work in SMC, LGS, and Winbond
1879  */
irq_probe_EPP(struct parport * pb)1880 static int irq_probe_EPP(struct parport *pb)
1881 {
1882 #ifndef ADVANCED_DETECT
1883 	return PARPORT_IRQ_NONE;
1884 #else
1885 	int irqs;
1886 	unsigned char oecr;
1887 
1888 	if (pb->modes & PARPORT_MODE_PCECR)
1889 		oecr = inb(ECONTROL(pb));
1890 
1891 	irqs = probe_irq_on();
1892 
1893 	if (pb->modes & PARPORT_MODE_PCECR)
1894 		frob_econtrol(pb, 0x10, 0x10);
1895 
1896 	clear_epp_timeout(pb);
1897 	parport_pc_frob_control(pb, 0x20, 0x20);
1898 	parport_pc_frob_control(pb, 0x10, 0x10);
1899 	clear_epp_timeout(pb);
1900 
1901 	/* Device isn't expecting an EPP read
1902 	 * and generates an IRQ.
1903 	 */
1904 	parport_pc_read_epp(pb);
1905 	udelay(20);
1906 
1907 	pb->irq = probe_irq_off(irqs);
1908 	if (pb->modes & PARPORT_MODE_PCECR)
1909 		ECR_WRITE(pb, oecr);
1910 	parport_pc_write_control(pb, 0xc);
1911 
1912 	if (pb->irq <= 0)
1913 		pb->irq = PARPORT_IRQ_NONE;
1914 
1915 	return pb->irq;
1916 #endif /* Advanced detection */
1917 }
1918 
irq_probe_SPP(struct parport * pb)1919 static int irq_probe_SPP(struct parport *pb)
1920 {
1921 	/* Don't even try to do this. */
1922 	return PARPORT_IRQ_NONE;
1923 }
1924 
1925 /* We will attempt to share interrupt requests since other devices
1926  * such as sound cards and network cards seem to like using the
1927  * printer IRQs.
1928  *
1929  * When ECP is available we can autoprobe for IRQs.
1930  * NOTE: If we can autoprobe it, we can register the IRQ.
1931  */
parport_irq_probe(struct parport * pb)1932 static int parport_irq_probe(struct parport *pb)
1933 {
1934 	struct parport_pc_private *priv = pb->private_data;
1935 
1936 	if (priv->ecr) {
1937 		pb->irq = programmable_irq_support(pb);
1938 
1939 		if (pb->irq == PARPORT_IRQ_NONE)
1940 			pb->irq = irq_probe_ECP(pb);
1941 	}
1942 
1943 	if ((pb->irq == PARPORT_IRQ_NONE) && priv->ecr &&
1944 	    (pb->modes & PARPORT_MODE_EPP))
1945 		pb->irq = irq_probe_EPP(pb);
1946 
1947 	clear_epp_timeout(pb);
1948 
1949 	if (pb->irq == PARPORT_IRQ_NONE && (pb->modes & PARPORT_MODE_EPP))
1950 		pb->irq = irq_probe_EPP(pb);
1951 
1952 	clear_epp_timeout(pb);
1953 
1954 	if (pb->irq == PARPORT_IRQ_NONE)
1955 		pb->irq = irq_probe_SPP(pb);
1956 
1957 	if (pb->irq == PARPORT_IRQ_NONE)
1958 		pb->irq = get_superio_irq(pb);
1959 
1960 	return pb->irq;
1961 }
1962 
1963 /* --- DMA detection -------------------------------------- */
1964 
1965 /* Only if chipset conforms to ECP ISA Interface Standard */
programmable_dma_support(struct parport * p)1966 static int programmable_dma_support(struct parport *p)
1967 {
1968 	unsigned char oecr = inb(ECONTROL(p));
1969 	int dma;
1970 
1971 	frob_set_mode(p, ECR_CNF);
1972 
1973 	dma = inb(CONFIGB(p)) & 0x07;
1974 	/* 000: Indicates jumpered 8-bit DMA if read-only.
1975 	   100: Indicates jumpered 16-bit DMA if read-only. */
1976 	if ((dma & 0x03) == 0)
1977 		dma = PARPORT_DMA_NONE;
1978 
1979 	ECR_WRITE(p, oecr);
1980 	return dma;
1981 }
1982 
parport_dma_probe(struct parport * p)1983 static int parport_dma_probe(struct parport *p)
1984 {
1985 	const struct parport_pc_private *priv = p->private_data;
1986 	if (priv->ecr)		/* ask ECP chipset first */
1987 		p->dma = programmable_dma_support(p);
1988 	if (p->dma == PARPORT_DMA_NONE) {
1989 		/* ask known Super-IO chips proper, although these
1990 		   claim ECP compatible, some don't report their DMA
1991 		   conforming to ECP standards */
1992 		p->dma = get_superio_dma(p);
1993 	}
1994 
1995 	return p->dma;
1996 }
1997 
1998 /* --- Initialisation code -------------------------------- */
1999 
2000 static LIST_HEAD(ports_list);
2001 static DEFINE_SPINLOCK(ports_lock);
2002 
parport_pc_probe_port(unsigned long int base,unsigned long int base_hi,int irq,int dma,struct device * dev,int irqflags)2003 struct parport *parport_pc_probe_port(unsigned long int base,
2004 				      unsigned long int base_hi,
2005 				      int irq, int dma,
2006 				      struct device *dev,
2007 				      int irqflags)
2008 {
2009 	struct parport_pc_private *priv;
2010 	struct parport_operations *ops;
2011 	struct parport *p;
2012 	int probedirq = PARPORT_IRQ_NONE;
2013 	struct resource *base_res;
2014 	struct resource	*ECR_res = NULL;
2015 	struct resource	*EPP_res = NULL;
2016 	struct platform_device *pdev = NULL;
2017 	int ret;
2018 
2019 	if (!dev) {
2020 		/* We need a physical device to attach to, but none was
2021 		 * provided. Create our own. */
2022 		pdev = platform_device_register_simple("parport_pc",
2023 						       base, NULL, 0);
2024 		if (IS_ERR(pdev))
2025 			return NULL;
2026 		dev = &pdev->dev;
2027 
2028 		ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(24));
2029 		if (ret) {
2030 			dev_err(dev, "Unable to set coherent dma mask: disabling DMA\n");
2031 			dma = PARPORT_DMA_NONE;
2032 		}
2033 	}
2034 
2035 	ops = kmalloc(sizeof(struct parport_operations), GFP_KERNEL);
2036 	if (!ops)
2037 		goto out1;
2038 
2039 	priv = kmalloc(sizeof(struct parport_pc_private), GFP_KERNEL);
2040 	if (!priv)
2041 		goto out2;
2042 
2043 	/* a misnomer, actually - it's allocate and reserve parport number */
2044 	p = parport_register_port(base, irq, dma, ops);
2045 	if (!p)
2046 		goto out3;
2047 
2048 	base_res = request_region(base, 3, p->name);
2049 	if (!base_res)
2050 		goto out4;
2051 
2052 	memcpy(ops, &parport_pc_ops, sizeof(struct parport_operations));
2053 	priv->ctr = 0xc;
2054 	priv->ctr_writable = ~0x10;
2055 	priv->ecr = 0;
2056 	priv->fifo_depth = 0;
2057 	priv->dma_buf = NULL;
2058 	priv->dma_handle = 0;
2059 	INIT_LIST_HEAD(&priv->list);
2060 	priv->port = p;
2061 
2062 	p->dev = dev;
2063 	p->base_hi = base_hi;
2064 	p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
2065 	p->private_data = priv;
2066 
2067 	if (base_hi) {
2068 		ECR_res = request_region(base_hi, 3, p->name);
2069 		if (ECR_res)
2070 			parport_ECR_present(p);
2071 	}
2072 
2073 	if (base != 0x3bc) {
2074 		EPP_res = request_region(base+0x3, 5, p->name);
2075 		if (EPP_res)
2076 			if (!parport_EPP_supported(p))
2077 				parport_ECPEPP_supported(p);
2078 	}
2079 	if (!parport_SPP_supported(p))
2080 		/* No port. */
2081 		goto out5;
2082 	if (priv->ecr)
2083 		parport_ECPPS2_supported(p);
2084 	else
2085 		parport_PS2_supported(p);
2086 
2087 	p->size = (p->modes & PARPORT_MODE_EPP) ? 8 : 3;
2088 
2089 	pr_info("%s: PC-style at 0x%lx", p->name, p->base);
2090 	if (p->base_hi && priv->ecr)
2091 		pr_cont(" (0x%lx)", p->base_hi);
2092 	if (p->irq == PARPORT_IRQ_AUTO) {
2093 		p->irq = PARPORT_IRQ_NONE;
2094 		parport_irq_probe(p);
2095 	} else if (p->irq == PARPORT_IRQ_PROBEONLY) {
2096 		p->irq = PARPORT_IRQ_NONE;
2097 		parport_irq_probe(p);
2098 		probedirq = p->irq;
2099 		p->irq = PARPORT_IRQ_NONE;
2100 	}
2101 	if (p->irq != PARPORT_IRQ_NONE) {
2102 		pr_cont(", irq %d", p->irq);
2103 		priv->ctr_writable |= 0x10;
2104 
2105 		if (p->dma == PARPORT_DMA_AUTO) {
2106 			p->dma = PARPORT_DMA_NONE;
2107 			parport_dma_probe(p);
2108 		}
2109 	}
2110 	if (p->dma == PARPORT_DMA_AUTO) /* To use DMA, giving the irq
2111 					   is mandatory (see above) */
2112 		p->dma = PARPORT_DMA_NONE;
2113 
2114 #ifdef CONFIG_PARPORT_PC_FIFO
2115 	if (parport_ECP_supported(p) &&
2116 	    p->dma != PARPORT_DMA_NOFIFO &&
2117 	    priv->fifo_depth > 0 && p->irq != PARPORT_IRQ_NONE) {
2118 		p->modes |= PARPORT_MODE_ECP | PARPORT_MODE_COMPAT;
2119 		p->ops->compat_write_data = parport_pc_compat_write_block_pio;
2120 #ifdef CONFIG_PARPORT_1284
2121 		p->ops->ecp_write_data = parport_pc_ecp_write_block_pio;
2122 		/* currently broken, but working on it.. (FB) */
2123 		/* p->ops->ecp_read_data = parport_pc_ecp_read_block_pio; */
2124 #endif /* IEEE 1284 support */
2125 		if (p->dma != PARPORT_DMA_NONE) {
2126 			pr_cont(", dma %d", p->dma);
2127 			p->modes |= PARPORT_MODE_DMA;
2128 		} else
2129 			pr_cont(", using FIFO");
2130 	} else
2131 		/* We can't use the DMA channel after all. */
2132 		p->dma = PARPORT_DMA_NONE;
2133 #endif /* Allowed to use FIFO/DMA */
2134 
2135 	pr_cont(" [");
2136 
2137 #define printmode(x)							\
2138 do {									\
2139 	if (p->modes & PARPORT_MODE_##x)				\
2140 		pr_cont("%s%s", f++ ? "," : "", #x);			\
2141 } while (0)
2142 
2143 	{
2144 		int f = 0;
2145 		printmode(PCSPP);
2146 		printmode(TRISTATE);
2147 		printmode(COMPAT);
2148 		printmode(EPP);
2149 		printmode(ECP);
2150 		printmode(DMA);
2151 	}
2152 #undef printmode
2153 #ifndef CONFIG_PARPORT_1284
2154 	pr_cont("(,...)");
2155 #endif /* CONFIG_PARPORT_1284 */
2156 	pr_cont("]\n");
2157 	if (probedirq != PARPORT_IRQ_NONE)
2158 		pr_info("%s: irq %d detected\n", p->name, probedirq);
2159 
2160 	/* If No ECP release the ports grabbed above. */
2161 	if (ECR_res && (p->modes & PARPORT_MODE_ECP) == 0) {
2162 		release_region(base_hi, 3);
2163 		ECR_res = NULL;
2164 	}
2165 	/* Likewise for EEP ports */
2166 	if (EPP_res && (p->modes & PARPORT_MODE_EPP) == 0) {
2167 		release_region(base+3, 5);
2168 		EPP_res = NULL;
2169 	}
2170 	if (p->irq != PARPORT_IRQ_NONE) {
2171 		if (request_irq(p->irq, parport_irq_handler,
2172 				 irqflags, p->name, p)) {
2173 			pr_warn("%s: irq %d in use, resorting to polled operation\n",
2174 				p->name, p->irq);
2175 			p->irq = PARPORT_IRQ_NONE;
2176 			p->dma = PARPORT_DMA_NONE;
2177 		}
2178 
2179 #ifdef CONFIG_PARPORT_PC_FIFO
2180 #ifdef HAS_DMA
2181 		if (p->dma != PARPORT_DMA_NONE) {
2182 			if (request_dma(p->dma, p->name)) {
2183 				pr_warn("%s: dma %d in use, resorting to PIO operation\n",
2184 					p->name, p->dma);
2185 				p->dma = PARPORT_DMA_NONE;
2186 			} else {
2187 				priv->dma_buf =
2188 				  dma_alloc_coherent(dev,
2189 						       PAGE_SIZE,
2190 						       &priv->dma_handle,
2191 						       GFP_KERNEL);
2192 				if (!priv->dma_buf) {
2193 					pr_warn("%s: cannot get buffer for DMA, resorting to PIO operation\n",
2194 						p->name);
2195 					free_dma(p->dma);
2196 					p->dma = PARPORT_DMA_NONE;
2197 				}
2198 			}
2199 		}
2200 #endif
2201 #endif
2202 	}
2203 
2204 	/* Done probing.  Now put the port into a sensible start-up state. */
2205 	if (priv->ecr)
2206 		/*
2207 		 * Put the ECP detected port in PS2 mode.
2208 		 * Do this also for ports that have ECR but don't do ECP.
2209 		 */
2210 		ECR_WRITE(p, 0x34);
2211 
2212 	parport_pc_write_data(p, 0);
2213 	parport_pc_data_forward(p);
2214 
2215 	/* Now that we've told the sharing engine about the port, and
2216 	   found out its characteristics, let the high-level drivers
2217 	   know about it. */
2218 	spin_lock(&ports_lock);
2219 	list_add(&priv->list, &ports_list);
2220 	spin_unlock(&ports_lock);
2221 	parport_announce_port(p);
2222 
2223 	return p;
2224 
2225 out5:
2226 	if (ECR_res)
2227 		release_region(base_hi, 3);
2228 	if (EPP_res)
2229 		release_region(base+0x3, 5);
2230 	release_region(base, 3);
2231 out4:
2232 	parport_del_port(p);
2233 out3:
2234 	kfree(priv);
2235 out2:
2236 	kfree(ops);
2237 out1:
2238 	if (pdev)
2239 		platform_device_unregister(pdev);
2240 	return NULL;
2241 }
2242 EXPORT_SYMBOL(parport_pc_probe_port);
2243 
parport_pc_unregister_port(struct parport * p)2244 void parport_pc_unregister_port(struct parport *p)
2245 {
2246 	struct parport_pc_private *priv = p->private_data;
2247 	struct parport_operations *ops = p->ops;
2248 
2249 	parport_remove_port(p);
2250 	spin_lock(&ports_lock);
2251 	list_del_init(&priv->list);
2252 	spin_unlock(&ports_lock);
2253 #if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA)
2254 	if (p->dma != PARPORT_DMA_NONE)
2255 		free_dma(p->dma);
2256 #endif
2257 	if (p->irq != PARPORT_IRQ_NONE)
2258 		free_irq(p->irq, p);
2259 	release_region(p->base, 3);
2260 	if (p->size > 3)
2261 		release_region(p->base + 3, p->size - 3);
2262 	if (p->modes & PARPORT_MODE_ECP)
2263 		release_region(p->base_hi, 3);
2264 #if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA)
2265 	if (priv->dma_buf)
2266 		dma_free_coherent(p->physport->dev, PAGE_SIZE,
2267 				    priv->dma_buf,
2268 				    priv->dma_handle);
2269 #endif
2270 	kfree(p->private_data);
2271 	parport_del_port(p);
2272 	kfree(ops); /* hope no-one cached it */
2273 }
2274 EXPORT_SYMBOL(parport_pc_unregister_port);
2275 
2276 #ifdef CONFIG_PCI
2277 
2278 /* ITE support maintained by Rich Liu <richliu@poorman.org> */
sio_ite_8872_probe(struct pci_dev * pdev,int autoirq,int autodma,const struct parport_pc_via_data * via)2279 static int sio_ite_8872_probe(struct pci_dev *pdev, int autoirq, int autodma,
2280 			      const struct parport_pc_via_data *via)
2281 {
2282 	short inta_addr[6] = { 0x2A0, 0x2C0, 0x220, 0x240, 0x1E0 };
2283 	u32 ite8872set;
2284 	u32 ite8872_lpt, ite8872_lpthi;
2285 	u8 ite8872_irq, type;
2286 	int irq;
2287 	int i;
2288 
2289 	pr_debug("sio_ite_8872_probe()\n");
2290 
2291 	/* make sure which one chip */
2292 	for (i = 0; i < 5; i++) {
2293 		if (request_region(inta_addr[i], 32, "it887x")) {
2294 			int test;
2295 			pci_write_config_dword(pdev, 0x60,
2296 						0xe5000000 | inta_addr[i]);
2297 			pci_write_config_dword(pdev, 0x78,
2298 						0x00000000 | inta_addr[i]);
2299 			test = inb(inta_addr[i]);
2300 			if (test != 0xff)
2301 				break;
2302 			release_region(inta_addr[i], 32);
2303 		}
2304 	}
2305 	if (i >= 5) {
2306 		pr_info("parport_pc: cannot find ITE8872 INTA\n");
2307 		return 0;
2308 	}
2309 
2310 	type = inb(inta_addr[i] + 0x18);
2311 	type &= 0x0f;
2312 
2313 	switch (type) {
2314 	case 0x2:
2315 		pr_info("parport_pc: ITE8871 found (1P)\n");
2316 		ite8872set = 0x64200000;
2317 		break;
2318 	case 0xa:
2319 		pr_info("parport_pc: ITE8875 found (1P)\n");
2320 		ite8872set = 0x64200000;
2321 		break;
2322 	case 0xe:
2323 		pr_info("parport_pc: ITE8872 found (2S1P)\n");
2324 		ite8872set = 0x64e00000;
2325 		break;
2326 	case 0x6:
2327 		pr_info("parport_pc: ITE8873 found (1S)\n");
2328 		release_region(inta_addr[i], 32);
2329 		return 0;
2330 	case 0x8:
2331 		pr_info("parport_pc: ITE8874 found (2S)\n");
2332 		release_region(inta_addr[i], 32);
2333 		return 0;
2334 	default:
2335 		pr_info("parport_pc: unknown ITE887x\n");
2336 		pr_info("parport_pc: please mail 'lspci -nvv' output to Rich.Liu@ite.com.tw\n");
2337 		release_region(inta_addr[i], 32);
2338 		return 0;
2339 	}
2340 
2341 	pci_read_config_byte(pdev, 0x3c, &ite8872_irq);
2342 	pci_read_config_dword(pdev, 0x1c, &ite8872_lpt);
2343 	ite8872_lpt &= 0x0000ff00;
2344 	pci_read_config_dword(pdev, 0x20, &ite8872_lpthi);
2345 	ite8872_lpthi &= 0x0000ff00;
2346 	pci_write_config_dword(pdev, 0x6c, 0xe3000000 | ite8872_lpt);
2347 	pci_write_config_dword(pdev, 0x70, 0xe3000000 | ite8872_lpthi);
2348 	pci_write_config_dword(pdev, 0x80, (ite8872_lpthi<<16) | ite8872_lpt);
2349 	/* SET SPP&EPP , Parallel Port NO DMA , Enable All Function */
2350 	/* SET Parallel IRQ */
2351 	pci_write_config_dword(pdev, 0x9c,
2352 				ite8872set | (ite8872_irq * 0x11111));
2353 
2354 	pr_debug("ITE887x: The IRQ is %d\n", ite8872_irq);
2355 	pr_debug("ITE887x: The PARALLEL I/O port is 0x%x\n", ite8872_lpt);
2356 	pr_debug("ITE887x: The PARALLEL I/O porthi is 0x%x\n", ite8872_lpthi);
2357 
2358 	/* Let the user (or defaults) steer us away from interrupts */
2359 	irq = ite8872_irq;
2360 	if (autoirq != PARPORT_IRQ_AUTO)
2361 		irq = PARPORT_IRQ_NONE;
2362 
2363 	/*
2364 	 * Release the resource so that parport_pc_probe_port can get it.
2365 	 */
2366 	release_region(inta_addr[i], 32);
2367 	if (parport_pc_probe_port(ite8872_lpt, ite8872_lpthi,
2368 				   irq, PARPORT_DMA_NONE, &pdev->dev, 0)) {
2369 		pr_info("parport_pc: ITE 8872 parallel port: io=0x%X",
2370 			ite8872_lpt);
2371 		if (irq != PARPORT_IRQ_NONE)
2372 			pr_cont(", irq=%d", irq);
2373 		pr_cont("\n");
2374 		return 1;
2375 	}
2376 
2377 	return 0;
2378 }
2379 
2380 /* VIA 8231 support by Pavel Fedin <sonic_amiga@rambler.ru>
2381    based on VIA 686a support code by Jeff Garzik <jgarzik@pobox.com> */
2382 static int parport_init_mode;
2383 
2384 /* Data for two known VIA chips */
2385 static struct parport_pc_via_data via_686a_data = {
2386 	0x51,
2387 	0x50,
2388 	0x85,
2389 	0x02,
2390 	0xE2,
2391 	0xF0,
2392 	0xE6
2393 };
2394 static struct parport_pc_via_data via_8231_data = {
2395 	0x45,
2396 	0x44,
2397 	0x50,
2398 	0x04,
2399 	0xF2,
2400 	0xFA,
2401 	0xF6
2402 };
2403 
sio_via_probe(struct pci_dev * pdev,int autoirq,int autodma,const struct parport_pc_via_data * via)2404 static int sio_via_probe(struct pci_dev *pdev, int autoirq, int autodma,
2405 			 const struct parport_pc_via_data *via)
2406 {
2407 	u8 tmp, tmp2, siofunc;
2408 	u8 ppcontrol = 0;
2409 	int dma, irq;
2410 	unsigned port1, port2;
2411 	unsigned have_epp = 0;
2412 
2413 	printk(KERN_DEBUG "parport_pc: VIA 686A/8231 detected\n");
2414 
2415 	switch (parport_init_mode) {
2416 	case 1:
2417 		printk(KERN_DEBUG "parport_pc: setting SPP mode\n");
2418 		siofunc = VIA_FUNCTION_PARPORT_SPP;
2419 		break;
2420 	case 2:
2421 		printk(KERN_DEBUG "parport_pc: setting PS/2 mode\n");
2422 		siofunc = VIA_FUNCTION_PARPORT_SPP;
2423 		ppcontrol = VIA_PARPORT_BIDIR;
2424 		break;
2425 	case 3:
2426 		printk(KERN_DEBUG "parport_pc: setting EPP mode\n");
2427 		siofunc = VIA_FUNCTION_PARPORT_EPP;
2428 		ppcontrol = VIA_PARPORT_BIDIR;
2429 		have_epp = 1;
2430 		break;
2431 	case 4:
2432 		printk(KERN_DEBUG "parport_pc: setting ECP mode\n");
2433 		siofunc = VIA_FUNCTION_PARPORT_ECP;
2434 		ppcontrol = VIA_PARPORT_BIDIR;
2435 		break;
2436 	case 5:
2437 		printk(KERN_DEBUG "parport_pc: setting EPP+ECP mode\n");
2438 		siofunc = VIA_FUNCTION_PARPORT_ECP;
2439 		ppcontrol = VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP;
2440 		have_epp = 1;
2441 		break;
2442 	default:
2443 		printk(KERN_DEBUG "parport_pc: probing current configuration\n");
2444 		siofunc = VIA_FUNCTION_PROBE;
2445 		break;
2446 	}
2447 	/*
2448 	 * unlock super i/o configuration
2449 	 */
2450 	pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp);
2451 	tmp |= via->via_pci_superio_config_data;
2452 	pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp);
2453 
2454 	/* Bits 1-0: Parallel Port Mode / Enable */
2455 	outb(via->viacfg_function, VIA_CONFIG_INDEX);
2456 	tmp = inb(VIA_CONFIG_DATA);
2457 	/* Bit 5: EPP+ECP enable; bit 7: PS/2 bidirectional port enable */
2458 	outb(via->viacfg_parport_control, VIA_CONFIG_INDEX);
2459 	tmp2 = inb(VIA_CONFIG_DATA);
2460 	if (siofunc == VIA_FUNCTION_PROBE) {
2461 		siofunc = tmp & VIA_FUNCTION_PARPORT_DISABLE;
2462 		ppcontrol = tmp2;
2463 	} else {
2464 		tmp &= ~VIA_FUNCTION_PARPORT_DISABLE;
2465 		tmp |= siofunc;
2466 		outb(via->viacfg_function, VIA_CONFIG_INDEX);
2467 		outb(tmp, VIA_CONFIG_DATA);
2468 		tmp2 &= ~(VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP);
2469 		tmp2 |= ppcontrol;
2470 		outb(via->viacfg_parport_control, VIA_CONFIG_INDEX);
2471 		outb(tmp2, VIA_CONFIG_DATA);
2472 	}
2473 
2474 	/* Parallel Port I/O Base Address, bits 9-2 */
2475 	outb(via->viacfg_parport_base, VIA_CONFIG_INDEX);
2476 	port1 = inb(VIA_CONFIG_DATA) << 2;
2477 
2478 	printk(KERN_DEBUG "parport_pc: Current parallel port base: 0x%X\n",
2479 	       port1);
2480 	if (port1 == 0x3BC && have_epp) {
2481 		outb(via->viacfg_parport_base, VIA_CONFIG_INDEX);
2482 		outb((0x378 >> 2), VIA_CONFIG_DATA);
2483 		printk(KERN_DEBUG "parport_pc: Parallel port base changed to 0x378\n");
2484 		port1 = 0x378;
2485 	}
2486 
2487 	/*
2488 	 * lock super i/o configuration
2489 	 */
2490 	pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp);
2491 	tmp &= ~via->via_pci_superio_config_data;
2492 	pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp);
2493 
2494 	if (siofunc == VIA_FUNCTION_PARPORT_DISABLE) {
2495 		pr_info("parport_pc: VIA parallel port disabled in BIOS\n");
2496 		return 0;
2497 	}
2498 
2499 	/* Bits 7-4: PnP Routing for Parallel Port IRQ */
2500 	pci_read_config_byte(pdev, via->via_pci_parport_irq_reg, &tmp);
2501 	irq = ((tmp & VIA_IRQCONTROL_PARALLEL) >> 4);
2502 
2503 	if (siofunc == VIA_FUNCTION_PARPORT_ECP) {
2504 		/* Bits 3-2: PnP Routing for Parallel Port DMA */
2505 		pci_read_config_byte(pdev, via->via_pci_parport_dma_reg, &tmp);
2506 		dma = ((tmp & VIA_DMACONTROL_PARALLEL) >> 2);
2507 	} else
2508 		/* if ECP not enabled, DMA is not enabled, assumed
2509 		   bogus 'dma' value */
2510 		dma = PARPORT_DMA_NONE;
2511 
2512 	/* Let the user (or defaults) steer us away from interrupts and DMA */
2513 	if (autoirq == PARPORT_IRQ_NONE) {
2514 		irq = PARPORT_IRQ_NONE;
2515 		dma = PARPORT_DMA_NONE;
2516 	}
2517 	if (autodma == PARPORT_DMA_NONE)
2518 		dma = PARPORT_DMA_NONE;
2519 
2520 	switch (port1) {
2521 	case 0x3bc:
2522 		port2 = 0x7bc; break;
2523 	case 0x378:
2524 		port2 = 0x778; break;
2525 	case 0x278:
2526 		port2 = 0x678; break;
2527 	default:
2528 		pr_info("parport_pc: Weird VIA parport base 0x%X, ignoring\n",
2529 			port1);
2530 		return 0;
2531 	}
2532 
2533 	/* filter bogus IRQs */
2534 	switch (irq) {
2535 	case 0:
2536 	case 2:
2537 	case 8:
2538 	case 13:
2539 		irq = PARPORT_IRQ_NONE;
2540 		break;
2541 
2542 	default: /* do nothing */
2543 		break;
2544 	}
2545 
2546 	/* finally, do the probe with values obtained */
2547 	if (parport_pc_probe_port(port1, port2, irq, dma, &pdev->dev, 0)) {
2548 		pr_info("parport_pc: VIA parallel port: io=0x%X", port1);
2549 		if (irq != PARPORT_IRQ_NONE)
2550 			pr_cont(", irq=%d", irq);
2551 		if (dma != PARPORT_DMA_NONE)
2552 			pr_cont(", dma=%d", dma);
2553 		pr_cont("\n");
2554 		return 1;
2555 	}
2556 
2557 	pr_warn("parport_pc: Strange, can't probe VIA parallel port: io=0x%X, irq=%d, dma=%d\n",
2558 		port1, irq, dma);
2559 	return 0;
2560 }
2561 
2562 
2563 enum parport_pc_sio_types {
2564 	sio_via_686a = 0,   /* Via VT82C686A motherboard Super I/O */
2565 	sio_via_8231,	    /* Via VT8231 south bridge integrated Super IO */
2566 	sio_ite_8872,
2567 	last_sio
2568 };
2569 
2570 /* each element directly indexed from enum list, above */
2571 static struct parport_pc_superio {
2572 	int (*probe) (struct pci_dev *pdev, int autoirq, int autodma,
2573 		      const struct parport_pc_via_data *via);
2574 	const struct parport_pc_via_data *via;
2575 } parport_pc_superio_info[] = {
2576 	{ sio_via_probe, &via_686a_data, },
2577 	{ sio_via_probe, &via_8231_data, },
2578 	{ sio_ite_8872_probe, NULL, },
2579 };
2580 
2581 enum parport_pc_pci_cards {
2582 	siig_1p_10x = last_sio,
2583 	siig_2p_10x,
2584 	siig_1p_20x,
2585 	siig_2p_20x,
2586 	lava_parallel,
2587 	lava_parallel_dual_a,
2588 	lava_parallel_dual_b,
2589 	boca_ioppar,
2590 	plx_9050,
2591 	timedia_4006a,
2592 	timedia_4014,
2593 	timedia_4008a,
2594 	timedia_4018,
2595 	timedia_9018a,
2596 	syba_2p_epp,
2597 	syba_1p_ecp,
2598 	titan_010l,
2599 	avlab_1p,
2600 	avlab_2p,
2601 	oxsemi_952,
2602 	oxsemi_954,
2603 	oxsemi_840,
2604 	oxsemi_pcie_pport,
2605 	aks_0100,
2606 	mobility_pp,
2607 	netmos_9705,
2608 	netmos_9715,
2609 	netmos_9755,
2610 	netmos_9805,
2611 	netmos_9815,
2612 	netmos_9901,
2613 	netmos_9865,
2614 	quatech_sppxp100,
2615 	wch_ch382l,
2616 };
2617 
2618 
2619 /* each element directly indexed from enum list, above
2620  * (but offset by last_sio) */
2621 static struct parport_pc_pci {
2622 	int numports;
2623 	struct { /* BAR (base address registers) numbers in the config
2624 		    space header */
2625 		int lo;
2626 		int hi;
2627 		/* -1 if not there, >6 for offset-method (max BAR is 6) */
2628 	} addr[4];
2629 
2630 	/* If set, this is called immediately after pci_enable_device.
2631 	 * If it returns non-zero, no probing will take place and the
2632 	 * ports will not be used. */
2633 	int (*preinit_hook) (struct pci_dev *pdev, int autoirq, int autodma);
2634 
2635 	/* If set, this is called after probing for ports.  If 'failed'
2636 	 * is non-zero we couldn't use any of the ports. */
2637 	void (*postinit_hook) (struct pci_dev *pdev, int failed);
2638 } cards[] = {
2639 	/* siig_1p_10x */		{ 1, { { 2, 3 }, } },
2640 	/* siig_2p_10x */		{ 2, { { 2, 3 }, { 4, 5 }, } },
2641 	/* siig_1p_20x */		{ 1, { { 0, 1 }, } },
2642 	/* siig_2p_20x */		{ 2, { { 0, 1 }, { 2, 3 }, } },
2643 	/* lava_parallel */		{ 1, { { 0, -1 }, } },
2644 	/* lava_parallel_dual_a */	{ 1, { { 0, -1 }, } },
2645 	/* lava_parallel_dual_b */	{ 1, { { 0, -1 }, } },
2646 	/* boca_ioppar */		{ 1, { { 0, -1 }, } },
2647 	/* plx_9050 */			{ 2, { { 4, -1 }, { 5, -1 }, } },
2648 	/* timedia_4006a */             { 1, { { 0, -1 }, } },
2649 	/* timedia_4014  */             { 2, { { 0, -1 }, { 2, -1 }, } },
2650 	/* timedia_4008a */             { 1, { { 0, 1 }, } },
2651 	/* timedia_4018  */             { 2, { { 0, 1 }, { 2, 3 }, } },
2652 	/* timedia_9018a */             { 2, { { 0, 1 }, { 2, 3 }, } },
2653 					/* SYBA uses fixed offsets in
2654 					   a 1K io window */
2655 	/* syba_2p_epp AP138B */	{ 2, { { 0, 0x078 }, { 0, 0x178 }, } },
2656 	/* syba_1p_ecp W83787 */	{ 1, { { 0, 0x078 }, } },
2657 	/* titan_010l */		{ 1, { { 3, -1 }, } },
2658 	/* avlab_1p		*/	{ 1, { { 0, 1}, } },
2659 	/* avlab_2p		*/	{ 2, { { 0, 1}, { 2, 3 },} },
2660 	/* The Oxford Semi cards are unusual: 954 doesn't support ECP,
2661 	 * and 840 locks up if you write 1 to bit 2! */
2662 	/* oxsemi_952 */		{ 1, { { 0, 1 }, } },
2663 	/* oxsemi_954 */		{ 1, { { 0, -1 }, } },
2664 	/* oxsemi_840 */		{ 1, { { 0, 1 }, } },
2665 	/* oxsemi_pcie_pport */		{ 1, { { 0, 1 }, } },
2666 	/* aks_0100 */                  { 1, { { 0, -1 }, } },
2667 	/* mobility_pp */		{ 1, { { 0, 1 }, } },
2668 
2669 	/* The netmos entries below are untested */
2670 	/* netmos_9705 */               { 1, { { 0, -1 }, } },
2671 	/* netmos_9715 */               { 2, { { 0, 1 }, { 2, 3 },} },
2672 	/* netmos_9755 */               { 2, { { 0, 1 }, { 2, 3 },} },
2673 	/* netmos_9805 */		{ 1, { { 0, 1 }, } },
2674 	/* netmos_9815 */		{ 2, { { 0, 1 }, { 2, 3 }, } },
2675 	/* netmos_9901 */               { 1, { { 0, -1 }, } },
2676 	/* netmos_9865 */               { 1, { { 0, -1 }, } },
2677 	/* quatech_sppxp100 */		{ 1, { { 0, 1 }, } },
2678 	/* wch_ch382l */		{ 1, { { 2, -1 }, } },
2679 };
2680 
2681 static const struct pci_device_id parport_pc_pci_tbl[] = {
2682 	/* Super-IO onboard chips */
2683 	{ 0x1106, 0x0686, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_686a },
2684 	{ 0x1106, 0x8231, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_8231 },
2685 	{ PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
2686 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_ite_8872 },
2687 
2688 	/* PCI cards */
2689 	{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_10x,
2690 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_10x },
2691 	{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_10x,
2692 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_10x },
2693 	{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_20x,
2694 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_20x },
2695 	{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_20x,
2696 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_20x },
2697 	{ PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PARALLEL,
2698 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel },
2699 	{ PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_A,
2700 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_a },
2701 	{ PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_B,
2702 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_b },
2703 	{ PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_BOCA_IOPPAR,
2704 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, boca_ioppar },
2705 	{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2706 	  PCI_SUBVENDOR_ID_EXSYS, PCI_SUBDEVICE_ID_EXSYS_4014, 0, 0, plx_9050 },
2707 	/* PCI_VENDOR_ID_TIMEDIA/SUNIX has many differing cards ...*/
2708 	{ 0x1409, 0x7268, 0x1409, 0x0101, 0, 0, timedia_4006a },
2709 	{ 0x1409, 0x7268, 0x1409, 0x0102, 0, 0, timedia_4014 },
2710 	{ 0x1409, 0x7268, 0x1409, 0x0103, 0, 0, timedia_4008a },
2711 	{ 0x1409, 0x7268, 0x1409, 0x0104, 0, 0, timedia_4018 },
2712 	{ 0x1409, 0x7268, 0x1409, 0x9018, 0, 0, timedia_9018a },
2713 	{ PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_2P_EPP,
2714 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_2p_epp },
2715 	{ PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_1P_ECP,
2716 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_1p_ecp },
2717 	{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_010L,
2718 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_010l },
2719 	/* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/
2720 	/* AFAVLAB_TK9902 */
2721 	{ 0x14db, 0x2120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1p},
2722 	{ 0x14db, 0x2121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2p},
2723 	{ PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952PP,
2724 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_952 },
2725 	{ PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954PP,
2726 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_954 },
2727 	{ PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_12PCI840,
2728 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_840 },
2729 	{ PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840,
2730 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2731 	{ PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840_G,
2732 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2733 	{ PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0,
2734 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2735 	{ PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0_G,
2736 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2737 	{ PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1,
2738 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2739 	{ PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_G,
2740 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2741 	{ PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_U,
2742 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2743 	{ PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_GU,
2744 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2745 	{ PCI_VENDOR_ID_AKS, PCI_DEVICE_ID_AKS_ALADDINCARD,
2746 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, aks_0100 },
2747 	{ 0x14f2, 0x0121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, mobility_pp },
2748 	/* NetMos communication controllers */
2749 	{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9705,
2750 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9705 },
2751 	{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9715,
2752 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9715 },
2753 	{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9755,
2754 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9755 },
2755 	{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9805,
2756 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9805 },
2757 	{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9815,
2758 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9815 },
2759 	{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
2760 	  0xA000, 0x2000, 0, 0, netmos_9901 },
2761 	{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
2762 	  0xA000, 0x1000, 0, 0, netmos_9865 },
2763 	{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
2764 	  0xA000, 0x2000, 0, 0, netmos_9865 },
2765 	/* Quatech SPPXP-100 Parallel port PCI ExpressCard */
2766 	{ PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SPPXP_100,
2767 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, quatech_sppxp100 },
2768 	/* WCH CH382L PCI-E single parallel port card */
2769 	{ 0x1c00, 0x3050, 0x1c00, 0x3050, 0, 0, wch_ch382l },
2770 	{ 0, } /* terminate list */
2771 };
2772 MODULE_DEVICE_TABLE(pci, parport_pc_pci_tbl);
2773 
2774 struct pci_parport_data {
2775 	int num;
2776 	struct parport *ports[2];
2777 };
2778 
parport_pc_pci_probe(struct pci_dev * dev,const struct pci_device_id * id)2779 static int parport_pc_pci_probe(struct pci_dev *dev,
2780 					   const struct pci_device_id *id)
2781 {
2782 	int err, count, n, i = id->driver_data;
2783 	struct pci_parport_data *data;
2784 
2785 	if (i < last_sio)
2786 		/* This is an onboard Super-IO and has already been probed */
2787 		return 0;
2788 
2789 	/* This is a PCI card */
2790 	i -= last_sio;
2791 	count = 0;
2792 	err = pci_enable_device(dev);
2793 	if (err)
2794 		return err;
2795 
2796 	data = kmalloc(sizeof(struct pci_parport_data), GFP_KERNEL);
2797 	if (!data)
2798 		return -ENOMEM;
2799 
2800 	if (cards[i].preinit_hook &&
2801 	    cards[i].preinit_hook(dev, PARPORT_IRQ_NONE, PARPORT_DMA_NONE)) {
2802 		kfree(data);
2803 		return -ENODEV;
2804 	}
2805 
2806 	for (n = 0; n < cards[i].numports; n++) {
2807 		int lo = cards[i].addr[n].lo;
2808 		int hi = cards[i].addr[n].hi;
2809 		int irq;
2810 		unsigned long io_lo, io_hi;
2811 		io_lo = pci_resource_start(dev, lo);
2812 		io_hi = 0;
2813 		if ((hi >= 0) && (hi <= 6))
2814 			io_hi = pci_resource_start(dev, hi);
2815 		else if (hi > 6)
2816 			io_lo += hi; /* Reinterpret the meaning of
2817 					"hi" as an offset (see SYBA
2818 					def.) */
2819 		/* TODO: test if sharing interrupts works */
2820 		irq = dev->irq;
2821 		if (irq == IRQ_NONE) {
2822 			printk(KERN_DEBUG "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx)\n",
2823 			       id->vendor, id->device, io_lo, io_hi);
2824 			irq = PARPORT_IRQ_NONE;
2825 		} else {
2826 			printk(KERN_DEBUG "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx), IRQ %d\n",
2827 			       id->vendor, id->device, io_lo, io_hi, irq);
2828 		}
2829 		data->ports[count] =
2830 			parport_pc_probe_port(io_lo, io_hi, irq,
2831 					       PARPORT_DMA_NONE, &dev->dev,
2832 					       IRQF_SHARED);
2833 		if (data->ports[count])
2834 			count++;
2835 	}
2836 
2837 	data->num = count;
2838 
2839 	if (cards[i].postinit_hook)
2840 		cards[i].postinit_hook(dev, count == 0);
2841 
2842 	if (count) {
2843 		pci_set_drvdata(dev, data);
2844 		return 0;
2845 	}
2846 
2847 	kfree(data);
2848 
2849 	return -ENODEV;
2850 }
2851 
parport_pc_pci_remove(struct pci_dev * dev)2852 static void parport_pc_pci_remove(struct pci_dev *dev)
2853 {
2854 	struct pci_parport_data *data = pci_get_drvdata(dev);
2855 	int i;
2856 
2857 	if (data) {
2858 		for (i = data->num - 1; i >= 0; i--)
2859 			parport_pc_unregister_port(data->ports[i]);
2860 
2861 		kfree(data);
2862 	}
2863 }
2864 
2865 static struct pci_driver parport_pc_pci_driver = {
2866 	.name		= "parport_pc",
2867 	.id_table	= parport_pc_pci_tbl,
2868 	.probe		= parport_pc_pci_probe,
2869 	.remove		= parport_pc_pci_remove,
2870 };
2871 
parport_pc_init_superio(int autoirq,int autodma)2872 static int __init parport_pc_init_superio(int autoirq, int autodma)
2873 {
2874 	const struct pci_device_id *id;
2875 	struct pci_dev *pdev = NULL;
2876 	int ret = 0;
2877 
2878 	for_each_pci_dev(pdev) {
2879 		id = pci_match_id(parport_pc_pci_tbl, pdev);
2880 		if (id == NULL || id->driver_data >= last_sio)
2881 			continue;
2882 
2883 		if (parport_pc_superio_info[id->driver_data].probe(
2884 			pdev, autoirq, autodma,
2885 			parport_pc_superio_info[id->driver_data].via)) {
2886 			ret++;
2887 		}
2888 	}
2889 
2890 	return ret; /* number of devices found */
2891 }
2892 #else
2893 static struct pci_driver parport_pc_pci_driver;
parport_pc_init_superio(int autoirq,int autodma)2894 static int __init parport_pc_init_superio(int autoirq, int autodma)
2895 {
2896 	return 0;
2897 }
2898 #endif /* CONFIG_PCI */
2899 
2900 #ifdef CONFIG_PNP
2901 
2902 static const struct pnp_device_id parport_pc_pnp_tbl[] = {
2903 	/* Standard LPT Printer Port */
2904 	{.id = "PNP0400", .driver_data = 0},
2905 	/* ECP Printer Port */
2906 	{.id = "PNP0401", .driver_data = 0},
2907 	{ }
2908 };
2909 
2910 MODULE_DEVICE_TABLE(pnp, parport_pc_pnp_tbl);
2911 
parport_pc_pnp_probe(struct pnp_dev * dev,const struct pnp_device_id * id)2912 static int parport_pc_pnp_probe(struct pnp_dev *dev,
2913 						const struct pnp_device_id *id)
2914 {
2915 	struct parport *pdata;
2916 	unsigned long io_lo, io_hi;
2917 	int dma, irq;
2918 
2919 	if (pnp_port_valid(dev, 0) &&
2920 		!(pnp_port_flags(dev, 0) & IORESOURCE_DISABLED)) {
2921 		io_lo = pnp_port_start(dev, 0);
2922 	} else
2923 		return -EINVAL;
2924 
2925 	if (pnp_port_valid(dev, 1) &&
2926 		!(pnp_port_flags(dev, 1) & IORESOURCE_DISABLED)) {
2927 		io_hi = pnp_port_start(dev, 1);
2928 	} else
2929 		io_hi = 0;
2930 
2931 	if (pnp_irq_valid(dev, 0) &&
2932 		!(pnp_irq_flags(dev, 0) & IORESOURCE_DISABLED)) {
2933 		irq = pnp_irq(dev, 0);
2934 	} else
2935 		irq = PARPORT_IRQ_NONE;
2936 
2937 	if (pnp_dma_valid(dev, 0) &&
2938 		!(pnp_dma_flags(dev, 0) & IORESOURCE_DISABLED)) {
2939 		dma = pnp_dma(dev, 0);
2940 	} else
2941 		dma = PARPORT_DMA_NONE;
2942 
2943 	dev_info(&dev->dev, "reported by %s\n", dev->protocol->name);
2944 	pdata = parport_pc_probe_port(io_lo, io_hi, irq, dma, &dev->dev, 0);
2945 	if (pdata == NULL)
2946 		return -ENODEV;
2947 
2948 	pnp_set_drvdata(dev, pdata);
2949 	return 0;
2950 }
2951 
parport_pc_pnp_remove(struct pnp_dev * dev)2952 static void parport_pc_pnp_remove(struct pnp_dev *dev)
2953 {
2954 	struct parport *pdata = (struct parport *)pnp_get_drvdata(dev);
2955 	if (!pdata)
2956 		return;
2957 
2958 	parport_pc_unregister_port(pdata);
2959 }
2960 
2961 /* we only need the pnp layer to activate the device, at least for now */
2962 static struct pnp_driver parport_pc_pnp_driver = {
2963 	.name		= "parport_pc",
2964 	.id_table	= parport_pc_pnp_tbl,
2965 	.probe		= parport_pc_pnp_probe,
2966 	.remove		= parport_pc_pnp_remove,
2967 };
2968 
2969 #else
2970 static struct pnp_driver parport_pc_pnp_driver;
2971 #endif /* CONFIG_PNP */
2972 
parport_pc_platform_probe(struct platform_device * pdev)2973 static int parport_pc_platform_probe(struct platform_device *pdev)
2974 {
2975 	/* Always succeed, the actual probing is done in
2976 	 * parport_pc_probe_port(). */
2977 	return 0;
2978 }
2979 
2980 static struct platform_driver parport_pc_platform_driver = {
2981 	.driver = {
2982 		.name	= "parport_pc",
2983 	},
2984 	.probe		= parport_pc_platform_probe,
2985 };
2986 
2987 /* This is called by parport_pc_find_nonpci_ports (in asm/parport.h) */
2988 static int __attribute__((unused))
parport_pc_find_isa_ports(int autoirq,int autodma)2989 parport_pc_find_isa_ports(int autoirq, int autodma)
2990 {
2991 	int count = 0;
2992 
2993 	if (parport_pc_probe_port(0x3bc, 0x7bc, autoirq, autodma, NULL, 0))
2994 		count++;
2995 	if (parport_pc_probe_port(0x378, 0x778, autoirq, autodma, NULL, 0))
2996 		count++;
2997 	if (parport_pc_probe_port(0x278, 0x678, autoirq, autodma, NULL, 0))
2998 		count++;
2999 
3000 	return count;
3001 }
3002 
3003 /* This function is called by parport_pc_init if the user didn't
3004  * specify any ports to probe.  Its job is to find some ports.  Order
3005  * is important here -- we want ISA ports to be registered first,
3006  * followed by PCI cards (for least surprise), but before that we want
3007  * to do chipset-specific tests for some onboard ports that we know
3008  * about.
3009  *
3010  * autoirq is PARPORT_IRQ_NONE, PARPORT_IRQ_AUTO, or PARPORT_IRQ_PROBEONLY
3011  * autodma is PARPORT_DMA_NONE or PARPORT_DMA_AUTO
3012  */
parport_pc_find_ports(int autoirq,int autodma)3013 static void __init parport_pc_find_ports(int autoirq, int autodma)
3014 {
3015 	int count = 0, err;
3016 
3017 #ifdef CONFIG_PARPORT_PC_SUPERIO
3018 	detect_and_report_it87();
3019 	detect_and_report_winbond();
3020 	detect_and_report_smsc();
3021 #endif
3022 
3023 	/* Onboard SuperIO chipsets that show themselves on the PCI bus. */
3024 	count += parport_pc_init_superio(autoirq, autodma);
3025 
3026 	/* PnP ports, skip detection if SuperIO already found them */
3027 	if (!count) {
3028 		err = pnp_register_driver(&parport_pc_pnp_driver);
3029 		if (!err)
3030 			pnp_registered_parport = 1;
3031 	}
3032 
3033 	/* ISA ports and whatever (see asm/parport.h). */
3034 	parport_pc_find_nonpci_ports(autoirq, autodma);
3035 
3036 	err = pci_register_driver(&parport_pc_pci_driver);
3037 	if (!err)
3038 		pci_registered_parport = 1;
3039 }
3040 
3041 /*
3042  *	Piles of crap below pretend to be a parser for module and kernel
3043  *	parameters.  Say "thank you" to whoever had come up with that
3044  *	syntax and keep in mind that code below is a cleaned up version.
3045  */
3046 
3047 static int __initdata io[PARPORT_PC_MAX_PORTS+1] = {
3048 	[0 ... PARPORT_PC_MAX_PORTS] = 0
3049 };
3050 static int __initdata io_hi[PARPORT_PC_MAX_PORTS+1] = {
3051 	[0 ... PARPORT_PC_MAX_PORTS] = PARPORT_IOHI_AUTO
3052 };
3053 static int __initdata dmaval[PARPORT_PC_MAX_PORTS] = {
3054 	[0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_DMA_NONE
3055 };
3056 static int __initdata irqval[PARPORT_PC_MAX_PORTS] = {
3057 	[0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_IRQ_PROBEONLY
3058 };
3059 
parport_parse_param(const char * s,int * val,int automatic,int none,int nofifo)3060 static int __init parport_parse_param(const char *s, int *val,
3061 				int automatic, int none, int nofifo)
3062 {
3063 	if (!s)
3064 		return 0;
3065 	if (!strncmp(s, "auto", 4))
3066 		*val = automatic;
3067 	else if (!strncmp(s, "none", 4))
3068 		*val = none;
3069 	else if (nofifo && !strncmp(s, "nofifo", 6))
3070 		*val = nofifo;
3071 	else {
3072 		char *ep;
3073 		unsigned long r = simple_strtoul(s, &ep, 0);
3074 		if (ep != s)
3075 			*val = r;
3076 		else {
3077 			pr_err("parport: bad specifier `%s'\n", s);
3078 			return -1;
3079 		}
3080 	}
3081 	return 0;
3082 }
3083 
parport_parse_irq(const char * irqstr,int * val)3084 static int __init parport_parse_irq(const char *irqstr, int *val)
3085 {
3086 	return parport_parse_param(irqstr, val, PARPORT_IRQ_AUTO,
3087 				     PARPORT_IRQ_NONE, 0);
3088 }
3089 
parport_parse_dma(const char * dmastr,int * val)3090 static int __init parport_parse_dma(const char *dmastr, int *val)
3091 {
3092 	return parport_parse_param(dmastr, val, PARPORT_DMA_AUTO,
3093 				     PARPORT_DMA_NONE, PARPORT_DMA_NOFIFO);
3094 }
3095 
3096 #ifdef CONFIG_PCI
parport_init_mode_setup(char * str)3097 static int __init parport_init_mode_setup(char *str)
3098 {
3099 	printk(KERN_DEBUG "parport_pc.c: Specified parameter parport_init_mode=%s\n",
3100 	       str);
3101 
3102 	if (!strcmp(str, "spp"))
3103 		parport_init_mode = 1;
3104 	if (!strcmp(str, "ps2"))
3105 		parport_init_mode = 2;
3106 	if (!strcmp(str, "epp"))
3107 		parport_init_mode = 3;
3108 	if (!strcmp(str, "ecp"))
3109 		parport_init_mode = 4;
3110 	if (!strcmp(str, "ecpepp"))
3111 		parport_init_mode = 5;
3112 	return 1;
3113 }
3114 #endif
3115 
3116 #ifdef MODULE
3117 static char *irq[PARPORT_PC_MAX_PORTS];
3118 static char *dma[PARPORT_PC_MAX_PORTS];
3119 
3120 MODULE_PARM_DESC(io, "Base I/O address (SPP regs)");
3121 module_param_hw_array(io, int, ioport, NULL, 0);
3122 MODULE_PARM_DESC(io_hi, "Base I/O address (ECR)");
3123 module_param_hw_array(io_hi, int, ioport, NULL, 0);
3124 MODULE_PARM_DESC(irq, "IRQ line");
3125 module_param_hw_array(irq, charp, irq, NULL, 0);
3126 MODULE_PARM_DESC(dma, "DMA channel");
3127 module_param_hw_array(dma, charp, dma, NULL, 0);
3128 #if defined(CONFIG_PARPORT_PC_SUPERIO) || \
3129        (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
3130 MODULE_PARM_DESC(verbose_probing, "Log chit-chat during initialisation");
3131 module_param(verbose_probing, int, 0644);
3132 #endif
3133 #ifdef CONFIG_PCI
3134 static char *init_mode;
3135 MODULE_PARM_DESC(init_mode,
3136 	"Initialise mode for VIA VT8231 port (spp, ps2, epp, ecp or ecpepp)");
3137 module_param(init_mode, charp, 0);
3138 #endif
3139 
parse_parport_params(void)3140 static int __init parse_parport_params(void)
3141 {
3142 	unsigned int i;
3143 	int val;
3144 
3145 #ifdef CONFIG_PCI
3146 	if (init_mode)
3147 		parport_init_mode_setup(init_mode);
3148 #endif
3149 
3150 	for (i = 0; i < PARPORT_PC_MAX_PORTS && io[i]; i++) {
3151 		if (parport_parse_irq(irq[i], &val))
3152 			return 1;
3153 		irqval[i] = val;
3154 		if (parport_parse_dma(dma[i], &val))
3155 			return 1;
3156 		dmaval[i] = val;
3157 	}
3158 	if (!io[0]) {
3159 		/* The user can make us use any IRQs or DMAs we find. */
3160 		if (irq[0] && !parport_parse_irq(irq[0], &val))
3161 			switch (val) {
3162 			case PARPORT_IRQ_NONE:
3163 			case PARPORT_IRQ_AUTO:
3164 				irqval[0] = val;
3165 				break;
3166 			default:
3167 				pr_warn("parport_pc: irq specified without base address.  Use 'io=' to specify one\n");
3168 			}
3169 
3170 		if (dma[0] && !parport_parse_dma(dma[0], &val))
3171 			switch (val) {
3172 			case PARPORT_DMA_NONE:
3173 			case PARPORT_DMA_AUTO:
3174 				dmaval[0] = val;
3175 				break;
3176 			default:
3177 				pr_warn("parport_pc: dma specified without base address.  Use 'io=' to specify one\n");
3178 			}
3179 	}
3180 	return 0;
3181 }
3182 
3183 #else
3184 
3185 static int parport_setup_ptr __initdata;
3186 
3187 /*
3188  * Acceptable parameters:
3189  *
3190  * parport=0
3191  * parport=auto
3192  * parport=0xBASE[,IRQ[,DMA]]
3193  *
3194  * IRQ/DMA may be numeric or 'auto' or 'none'
3195  */
parport_setup(char * str)3196 static int __init parport_setup(char *str)
3197 {
3198 	char *endptr;
3199 	char *sep;
3200 	int val;
3201 
3202 	if (!str || !*str || (*str == '0' && !*(str+1))) {
3203 		/* Disable parport if "parport=0" in cmdline */
3204 		io[0] = PARPORT_DISABLE;
3205 		return 1;
3206 	}
3207 
3208 	if (!strncmp(str, "auto", 4)) {
3209 		irqval[0] = PARPORT_IRQ_AUTO;
3210 		dmaval[0] = PARPORT_DMA_AUTO;
3211 		return 1;
3212 	}
3213 
3214 	val = simple_strtoul(str, &endptr, 0);
3215 	if (endptr == str) {
3216 		pr_warn("parport=%s not understood\n", str);
3217 		return 1;
3218 	}
3219 
3220 	if (parport_setup_ptr == PARPORT_PC_MAX_PORTS) {
3221 		pr_err("parport=%s ignored, too many ports\n", str);
3222 		return 1;
3223 	}
3224 
3225 	io[parport_setup_ptr] = val;
3226 	irqval[parport_setup_ptr] = PARPORT_IRQ_NONE;
3227 	dmaval[parport_setup_ptr] = PARPORT_DMA_NONE;
3228 
3229 	sep = strchr(str, ',');
3230 	if (sep++) {
3231 		if (parport_parse_irq(sep, &val))
3232 			return 1;
3233 		irqval[parport_setup_ptr] = val;
3234 		sep = strchr(sep, ',');
3235 		if (sep++) {
3236 			if (parport_parse_dma(sep, &val))
3237 				return 1;
3238 			dmaval[parport_setup_ptr] = val;
3239 		}
3240 	}
3241 	parport_setup_ptr++;
3242 	return 1;
3243 }
3244 
parse_parport_params(void)3245 static int __init parse_parport_params(void)
3246 {
3247 	return io[0] == PARPORT_DISABLE;
3248 }
3249 
3250 __setup("parport=", parport_setup);
3251 
3252 /*
3253  * Acceptable parameters:
3254  *
3255  * parport_init_mode=[spp|ps2|epp|ecp|ecpepp]
3256  */
3257 #ifdef CONFIG_PCI
3258 __setup("parport_init_mode=", parport_init_mode_setup);
3259 #endif
3260 #endif
3261 
3262 /* "Parser" ends here */
3263 
parport_pc_init(void)3264 static int __init parport_pc_init(void)
3265 {
3266 	int err;
3267 
3268 	if (parse_parport_params())
3269 		return -EINVAL;
3270 
3271 	err = platform_driver_register(&parport_pc_platform_driver);
3272 	if (err)
3273 		return err;
3274 
3275 	if (io[0]) {
3276 		int i;
3277 		/* Only probe the ports we were given. */
3278 		user_specified = 1;
3279 		for (i = 0; i < PARPORT_PC_MAX_PORTS; i++) {
3280 			if (!io[i])
3281 				break;
3282 			if (io_hi[i] == PARPORT_IOHI_AUTO)
3283 				io_hi[i] = 0x400 + io[i];
3284 			parport_pc_probe_port(io[i], io_hi[i],
3285 					irqval[i], dmaval[i], NULL, 0);
3286 		}
3287 	} else
3288 		parport_pc_find_ports(irqval[0], dmaval[0]);
3289 
3290 	return 0;
3291 }
3292 
parport_pc_exit(void)3293 static void __exit parport_pc_exit(void)
3294 {
3295 	if (pci_registered_parport)
3296 		pci_unregister_driver(&parport_pc_pci_driver);
3297 	if (pnp_registered_parport)
3298 		pnp_unregister_driver(&parport_pc_pnp_driver);
3299 	platform_driver_unregister(&parport_pc_platform_driver);
3300 
3301 	while (!list_empty(&ports_list)) {
3302 		struct parport_pc_private *priv;
3303 		struct parport *port;
3304 		struct device *dev;
3305 		priv = list_entry(ports_list.next,
3306 				  struct parport_pc_private, list);
3307 		port = priv->port;
3308 		dev = port->dev;
3309 		parport_pc_unregister_port(port);
3310 		if (dev && dev->bus == &platform_bus_type)
3311 			platform_device_unregister(to_platform_device(dev));
3312 	}
3313 }
3314 
3315 MODULE_AUTHOR("Phil Blundell, Tim Waugh, others");
3316 MODULE_DESCRIPTION("PC-style parallel port driver");
3317 MODULE_LICENSE("GPL");
3318 module_init(parport_pc_init)
3319 module_exit(parport_pc_exit)
3320