Home
last modified time | relevance | path

Searched refs:mmVM_L2_CACHE_PARITY_CNTL (Results 1 – 6 of 6) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/mmhub/
Dmmhub_1_0_offset.h1316 #define mmVM_L2_CACHE_PARITY_CNTL … macro
Dmmhub_9_1_offset.h1348 #define mmVM_L2_CACHE_PARITY_CNTL … macro
Dmmhub_9_3_0_offset.h1332 #define mmVM_L2_CACHE_PARITY_CNTL … macro
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h1217 #define mmVM_L2_CACHE_PARITY_CNTL … macro
Dgc_9_1_offset.h1243 #define mmVM_L2_CACHE_PARITY_CNTL … macro
Dgc_9_2_1_offset.h1181 #define mmVM_L2_CACHE_PARITY_CNTL … macro