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Searched refs:mmVM_CONTEXT1_CNTL (Results 1 – 16 of 16) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/amdgpu/
Dgmc_v6_0.c398 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v6_0_set_fault_enable_default()
411 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v6_0_set_fault_enable_default()
545 WREG32(mmVM_CONTEXT1_CNTL, in gmc_v6_0_gart_enable()
593 WREG32(mmVM_CONTEXT1_CNTL, 0); in gmc_v6_0_gart_disable()
1050 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v6_0_vm_fault_interrupt_state()
1052 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v6_0_vm_fault_interrupt_state()
1058 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v6_0_vm_fault_interrupt_state()
1060 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v6_0_vm_fault_interrupt_state()
Dgmc_v7_0.c530 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v7_0_set_fault_enable_default()
543 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v7_0_set_fault_enable_default()
692 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v7_0_gart_enable()
697 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v7_0_gart_enable()
746 WREG32(mmVM_CONTEXT1_CNTL, 0); in gmc_v7_0_gart_disable()
1249 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v7_0_vm_fault_interrupt_state()
1251 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v7_0_vm_fault_interrupt_state()
1259 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v7_0_vm_fault_interrupt_state()
1261 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v7_0_vm_fault_interrupt_state()
Dgmc_v8_0.c751 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v8_0_set_fault_enable_default()
766 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v8_0_set_fault_enable_default()
931 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v8_0_gart_enable()
943 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v8_0_gart_enable()
986 WREG32(mmVM_CONTEXT1_CNTL, 0); in gmc_v8_0_gart_disable()
1417 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v8_0_vm_fault_interrupt_state()
1419 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v8_0_vm_fault_interrupt_state()
1427 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v8_0_vm_fault_interrupt_state()
1429 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v8_0_vm_fault_interrupt_state()
Dgfxhub_v1_0.c263 tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i); in gfxhub_v1_0_setup_vmid_config()
293 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, in gfxhub_v1_0_setup_vmid_config()
435 hub->ctx_distance = mmVM_CONTEXT1_CNTL - mmVM_CONTEXT0_CNTL; in gfxhub_v1_0_init()
Dmmhub_v1_0.c245 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i); in mmhub_v1_0_setup_vmid_config()
271 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, in mmhub_v1_0_setup_vmid_config()
439 hub->ctx_distance = mmVM_CONTEXT1_CNTL - mmVM_CONTEXT0_CNTL; in mmhub_v1_0_init()
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_7_0_d.h546 #define mmVM_CONTEXT1_CNTL 0x505 macro
Dgmc_8_2_d.h604 #define mmVM_CONTEXT1_CNTL 0x505 macro
Dgmc_6_0_d.h1231 #define mmVM_CONTEXT1_CNTL 0x0505 macro
Dgmc_7_1_d.h579 #define mmVM_CONTEXT1_CNTL 0x505 macro
Dgmc_8_1_d.h602 #define mmVM_CONTEXT1_CNTL 0x505 macro
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/mmhub/
Dmmhub_1_0_offset.h1326 #define mmVM_CONTEXT1_CNTL … macro
Dmmhub_9_1_offset.h1358 #define mmVM_CONTEXT1_CNTL … macro
Dmmhub_9_3_0_offset.h1342 #define mmVM_CONTEXT1_CNTL … macro
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h1234 #define mmVM_CONTEXT1_CNTL … macro
Dgc_9_1_offset.h1253 #define mmVM_CONTEXT1_CNTL … macro
Dgc_9_2_1_offset.h1191 #define mmVM_CONTEXT1_CNTL … macro