| /linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| D | uvd_4_0_d.h | 94 #define mmUVD_VCPU_CNTL 0x3D98 macro
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| D | uvd_4_2_d.h | 66 #define mmUVD_VCPU_CNTL 0x3d98 macro
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| D | uvd_3_1_d.h | 68 #define mmUVD_VCPU_CNTL 0x3d98 macro
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| D | uvd_5_0_d.h | 72 #define mmUVD_VCPU_CNTL 0x3d98 macro
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| D | uvd_6_0_d.h | 88 #define mmUVD_VCPU_CNTL 0x3d98 macro
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| D | uvd_7_0_offset.h | 190 #define mmUVD_VCPU_CNTL … macro
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| /linux-5.19.10/drivers/gpu/drm/amd/amdgpu/ |
| D | vcn_v2_5.c | 799 VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v2_5_start_dpg_mode()
859 VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v2_5_start_dpg_mode()
953 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), in vcn_v2_5_start()
1016 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, in vcn_v2_5_start()
1036 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), in vcn_v2_5_start()
1040 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, in vcn_v2_5_start()
1377 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), in vcn_v2_5_stop()
1382 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, in vcn_v2_5_stop()
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| D | vcn_v3_0.c | 965 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v3_0_start_dpg_mode()
1025 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v3_0_start_dpg_mode()
1034 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v3_0_start_dpg_mode()
1123 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), in vcn_v3_0_start()
1184 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, in vcn_v3_0_start()
1201 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), in vcn_v3_0_start()
1205 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, in vcn_v3_0_start()
1564 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), in vcn_v3_0_stop()
1569 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, in vcn_v3_0_stop()
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| D | uvd_v3_1.c | 341 WREG32(mmUVD_VCPU_CNTL, 1 << 9); in uvd_v3_1_start()
492 WREG32_P(mmUVD_VCPU_CNTL, 0, ~(1 << 9)); in uvd_v3_1_stop()
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| D | uvd_v4_2.c | 299 WREG32(mmUVD_VCPU_CNTL, 1 << 9); in uvd_v4_2_start()
450 WREG32_P(mmUVD_VCPU_CNTL, 0, ~(1 << 9)); in uvd_v4_2_stop()
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| D | uvd_v5_0.c | 375 WREG32(mmUVD_VCPU_CNTL, 1 << 9); in uvd_v5_0_start()
470 WREG32(mmUVD_VCPU_CNTL, 0x0); in uvd_v5_0_stop()
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| D | uvd_v7_0.c | 899 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), in uvd_v7_0_sriov_start()
1030 WREG32_SOC15(UVD, k, mmUVD_VCPU_CNTL, in uvd_v7_0_start()
1157 WREG32_SOC15(UVD, i, mmUVD_VCPU_CNTL, 0x0); in uvd_v7_0_stop()
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| D | vcn_v1_0.c | 851 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK); in vcn_v1_0_start_spg_mode()
984 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CNTL, tmp, 0xFFFFFFFF, 0); in vcn_v1_0_start_dpg_mode()
1139 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0, in vcn_v1_0_stop_spg_mode()
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| D | vcn_v2_0.c | 817 UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v2_0_start_dpg_mode()
953 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), in vcn_v2_0_start()
1169 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0, in vcn_v2_0_stop()
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| D | uvd_v6_0.c | 789 WREG32(mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK); in uvd_v6_0_start()
901 WREG32(mmUVD_VCPU_CNTL, 0x0); in uvd_v6_0_stop()
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| /linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| D | vcn_1_0_offset.h | 376 #define mmUVD_VCPU_CNTL … macro
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| D | vcn_2_5_offset.h | 729 #define mmUVD_VCPU_CNTL … macro
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| D | vcn_2_0_0_offset.h | 658 #define mmUVD_VCPU_CNTL … macro
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| D | vcn_3_0_0_offset.h | 1105 #define mmUVD_VCPU_CNTL … macro
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