1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_TPC6_CFG_REGS_H_ 14 #define ASIC_REG_TPC6_CFG_REGS_H_ 15 16 /* 17 ***************************************** 18 * TPC6_CFG (Prototype: TPC) 19 ***************************************** 20 */ 21 22 #define mmTPC6_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xF86400 23 24 #define mmTPC6_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xF86404 25 26 #define mmTPC6_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xF86408 27 28 #define mmTPC6_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xF8640C 29 30 #define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xF86410 31 32 #define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xF86414 33 34 #define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET 0xF86418 35 36 #define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xF8641C 37 38 #define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xF86420 39 40 #define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET 0xF86424 41 42 #define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xF86428 43 44 #define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xF8642C 45 46 #define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET 0xF86430 47 48 #define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xF86434 49 50 #define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xF86438 51 52 #define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET 0xF8643C 53 54 #define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xF86440 55 56 #define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xF86444 57 58 #define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET 0xF86448 59 60 #define mmTPC6_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xF8644C 61 62 #define mmTPC6_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xF86450 63 64 #define mmTPC6_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xF86454 65 66 #define mmTPC6_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xF86458 67 68 #define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xF8645C 69 70 #define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xF86460 71 72 #define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET 0xF86464 73 74 #define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xF86468 75 76 #define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xF8646C 77 78 #define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET 0xF86470 79 80 #define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xF86474 81 82 #define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xF86478 83 84 #define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET 0xF8647C 85 86 #define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xF86480 87 88 #define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xF86484 89 90 #define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET 0xF86488 91 92 #define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xF8648C 93 94 #define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xF86490 95 96 #define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET 0xF86494 97 98 #define mmTPC6_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xF86498 99 100 #define mmTPC6_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xF8649C 101 102 #define mmTPC6_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xF864A0 103 104 #define mmTPC6_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xF864A4 105 106 #define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xF864A8 107 108 #define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xF864AC 109 110 #define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET 0xF864B0 111 112 #define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xF864B4 113 114 #define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xF864B8 115 116 #define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET 0xF864BC 117 118 #define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xF864C0 119 120 #define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xF864C4 121 122 #define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET 0xF864C8 123 124 #define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xF864CC 125 126 #define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xF864D0 127 128 #define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET 0xF864D4 129 130 #define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xF864D8 131 132 #define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xF864DC 133 134 #define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET 0xF864E0 135 136 #define mmTPC6_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xF864E4 137 138 #define mmTPC6_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xF864E8 139 140 #define mmTPC6_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xF864EC 141 142 #define mmTPC6_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xF864F0 143 144 #define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xF864F4 145 146 #define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xF864F8 147 148 #define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET 0xF864FC 149 150 #define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xF86500 151 152 #define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xF86504 153 154 #define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET 0xF86508 155 156 #define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xF8650C 157 158 #define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xF86510 159 160 #define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET 0xF86514 161 162 #define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xF86518 163 164 #define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xF8651C 165 166 #define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET 0xF86520 167 168 #define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xF86524 169 170 #define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xF86528 171 172 #define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET 0xF8652C 173 174 #define mmTPC6_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xF86530 175 176 #define mmTPC6_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xF86534 177 178 #define mmTPC6_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xF86538 179 180 #define mmTPC6_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xF8653C 181 182 #define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xF86540 183 184 #define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xF86544 185 186 #define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET 0xF86548 187 188 #define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xF8654C 189 190 #define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xF86550 191 192 #define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET 0xF86554 193 194 #define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xF86558 195 196 #define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xF8655C 197 198 #define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET 0xF86560 199 200 #define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xF86564 201 202 #define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xF86568 203 204 #define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET 0xF8656C 205 206 #define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xF86570 207 208 #define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xF86574 209 210 #define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET 0xF86578 211 212 #define mmTPC6_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xF8657C 213 214 #define mmTPC6_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xF86580 215 216 #define mmTPC6_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xF86584 217 218 #define mmTPC6_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xF86588 219 220 #define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xF8658C 221 222 #define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xF86590 223 224 #define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET 0xF86594 225 226 #define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xF86598 227 228 #define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xF8659C 229 230 #define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET 0xF865A0 231 232 #define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xF865A4 233 234 #define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xF865A8 235 236 #define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET 0xF865AC 237 238 #define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xF865B0 239 240 #define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xF865B4 241 242 #define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET 0xF865B8 243 244 #define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xF865BC 245 246 #define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xF865C0 247 248 #define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET 0xF865C4 249 250 #define mmTPC6_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xF865C8 251 252 #define mmTPC6_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xF865CC 253 254 #define mmTPC6_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xF865D0 255 256 #define mmTPC6_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xF865D4 257 258 #define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xF865D8 259 260 #define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xF865DC 261 262 #define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET 0xF865E0 263 264 #define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xF865E4 265 266 #define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xF865E8 267 268 #define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET 0xF865EC 269 270 #define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xF865F0 271 272 #define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xF865F4 273 274 #define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET 0xF865F8 275 276 #define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xF865FC 277 278 #define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xF86600 279 280 #define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET 0xF86604 281 282 #define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xF86608 283 284 #define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xF8660C 285 286 #define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET 0xF86610 287 288 #define mmTPC6_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xF86614 289 290 #define mmTPC6_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xF86618 291 292 #define mmTPC6_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xF8661C 293 294 #define mmTPC6_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xF86620 295 296 #define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xF86624 297 298 #define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xF86628 299 300 #define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET 0xF8662C 301 302 #define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xF86630 303 304 #define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xF86634 305 306 #define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET 0xF86638 307 308 #define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xF8663C 309 310 #define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xF86640 311 312 #define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET 0xF86644 313 314 #define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xF86648 315 316 #define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xF8664C 317 318 #define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET 0xF86650 319 320 #define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xF86654 321 322 #define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xF86658 323 324 #define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET 0xF8665C 325 326 #define mmTPC6_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xF86660 327 328 #define mmTPC6_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xF86664 329 330 #define mmTPC6_CFG_KERNEL_TID_BASE_DIM_0 0xF86668 331 332 #define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_0 0xF8666C 333 334 #define mmTPC6_CFG_KERNEL_TID_BASE_DIM_1 0xF86670 335 336 #define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_1 0xF86674 337 338 #define mmTPC6_CFG_KERNEL_TID_BASE_DIM_2 0xF86678 339 340 #define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_2 0xF8667C 341 342 #define mmTPC6_CFG_KERNEL_TID_BASE_DIM_3 0xF86680 343 344 #define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_3 0xF86684 345 346 #define mmTPC6_CFG_KERNEL_TID_BASE_DIM_4 0xF86688 347 348 #define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_4 0xF8668C 349 350 #define mmTPC6_CFG_KERNEL_SRF_0 0xF86690 351 352 #define mmTPC6_CFG_KERNEL_SRF_1 0xF86694 353 354 #define mmTPC6_CFG_KERNEL_SRF_2 0xF86698 355 356 #define mmTPC6_CFG_KERNEL_SRF_3 0xF8669C 357 358 #define mmTPC6_CFG_KERNEL_SRF_4 0xF866A0 359 360 #define mmTPC6_CFG_KERNEL_SRF_5 0xF866A4 361 362 #define mmTPC6_CFG_KERNEL_SRF_6 0xF866A8 363 364 #define mmTPC6_CFG_KERNEL_SRF_7 0xF866AC 365 366 #define mmTPC6_CFG_KERNEL_SRF_8 0xF866B0 367 368 #define mmTPC6_CFG_KERNEL_SRF_9 0xF866B4 369 370 #define mmTPC6_CFG_KERNEL_SRF_10 0xF866B8 371 372 #define mmTPC6_CFG_KERNEL_SRF_11 0xF866BC 373 374 #define mmTPC6_CFG_KERNEL_SRF_12 0xF866C0 375 376 #define mmTPC6_CFG_KERNEL_SRF_13 0xF866C4 377 378 #define mmTPC6_CFG_KERNEL_SRF_14 0xF866C8 379 380 #define mmTPC6_CFG_KERNEL_SRF_15 0xF866CC 381 382 #define mmTPC6_CFG_KERNEL_SRF_16 0xF866D0 383 384 #define mmTPC6_CFG_KERNEL_SRF_17 0xF866D4 385 386 #define mmTPC6_CFG_KERNEL_SRF_18 0xF866D8 387 388 #define mmTPC6_CFG_KERNEL_SRF_19 0xF866DC 389 390 #define mmTPC6_CFG_KERNEL_SRF_20 0xF866E0 391 392 #define mmTPC6_CFG_KERNEL_SRF_21 0xF866E4 393 394 #define mmTPC6_CFG_KERNEL_SRF_22 0xF866E8 395 396 #define mmTPC6_CFG_KERNEL_SRF_23 0xF866EC 397 398 #define mmTPC6_CFG_KERNEL_SRF_24 0xF866F0 399 400 #define mmTPC6_CFG_KERNEL_SRF_25 0xF866F4 401 402 #define mmTPC6_CFG_KERNEL_SRF_26 0xF866F8 403 404 #define mmTPC6_CFG_KERNEL_SRF_27 0xF866FC 405 406 #define mmTPC6_CFG_KERNEL_SRF_28 0xF86700 407 408 #define mmTPC6_CFG_KERNEL_SRF_29 0xF86704 409 410 #define mmTPC6_CFG_KERNEL_SRF_30 0xF86708 411 412 #define mmTPC6_CFG_KERNEL_SRF_31 0xF8670C 413 414 #define mmTPC6_CFG_KERNEL_KERNEL_CONFIG 0xF86710 415 416 #define mmTPC6_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xF86714 417 418 #define mmTPC6_CFG_RESERVED_DESC_END 0xF86738 419 420 #define mmTPC6_CFG_ROUND_CSR 0xF867FC 421 422 #define mmTPC6_CFG_TBUF_BASE_ADDR_LOW 0xF86800 423 424 #define mmTPC6_CFG_TBUF_BASE_ADDR_HIGH 0xF86804 425 426 #define mmTPC6_CFG_SEMAPHORE 0xF86808 427 428 #define mmTPC6_CFG_VFLAGS 0xF8680C 429 430 #define mmTPC6_CFG_SFLAGS 0xF86810 431 432 #define mmTPC6_CFG_LFSR_POLYNOM 0xF86818 433 434 #define mmTPC6_CFG_STATUS 0xF8681C 435 436 #define mmTPC6_CFG_CFG_BASE_ADDRESS_HIGH 0xF86820 437 438 #define mmTPC6_CFG_CFG_SUBTRACT_VALUE 0xF86824 439 440 #define mmTPC6_CFG_SM_BASE_ADDRESS_LOW 0xF86828 441 442 #define mmTPC6_CFG_SM_BASE_ADDRESS_HIGH 0xF8682C 443 444 #define mmTPC6_CFG_TPC_CMD 0xF86830 445 446 #define mmTPC6_CFG_TPC_EXECUTE 0xF86838 447 448 #define mmTPC6_CFG_TPC_STALL 0xF8683C 449 450 #define mmTPC6_CFG_ICACHE_BASE_ADDERESS_LOW 0xF86840 451 452 #define mmTPC6_CFG_ICACHE_BASE_ADDERESS_HIGH 0xF86844 453 454 #define mmTPC6_CFG_MSS_CONFIG 0xF86854 455 456 #define mmTPC6_CFG_TPC_INTR_CAUSE 0xF86858 457 458 #define mmTPC6_CFG_TPC_INTR_MASK 0xF8685C 459 460 #define mmTPC6_CFG_TSB_CONFIG 0xF86860 461 462 #define mmTPC6_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xF86A00 463 464 #define mmTPC6_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xF86A04 465 466 #define mmTPC6_CFG_QM_TENSOR_0_PADDING_VALUE 0xF86A08 467 468 #define mmTPC6_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xF86A0C 469 470 #define mmTPC6_CFG_QM_TENSOR_0_DIM_0_SIZE 0xF86A10 471 472 #define mmTPC6_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xF86A14 473 474 #define mmTPC6_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET 0xF86A18 475 476 #define mmTPC6_CFG_QM_TENSOR_0_DIM_1_SIZE 0xF86A1C 477 478 #define mmTPC6_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xF86A20 479 480 #define mmTPC6_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET 0xF86A24 481 482 #define mmTPC6_CFG_QM_TENSOR_0_DIM_2_SIZE 0xF86A28 483 484 #define mmTPC6_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xF86A2C 485 486 #define mmTPC6_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET 0xF86A30 487 488 #define mmTPC6_CFG_QM_TENSOR_0_DIM_3_SIZE 0xF86A34 489 490 #define mmTPC6_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xF86A38 491 492 #define mmTPC6_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET 0xF86A3C 493 494 #define mmTPC6_CFG_QM_TENSOR_0_DIM_4_SIZE 0xF86A40 495 496 #define mmTPC6_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xF86A44 497 498 #define mmTPC6_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET 0xF86A48 499 500 #define mmTPC6_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xF86A4C 501 502 #define mmTPC6_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xF86A50 503 504 #define mmTPC6_CFG_QM_TENSOR_1_PADDING_VALUE 0xF86A54 505 506 #define mmTPC6_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xF86A58 507 508 #define mmTPC6_CFG_QM_TENSOR_1_DIM_0_SIZE 0xF86A5C 509 510 #define mmTPC6_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xF86A60 511 512 #define mmTPC6_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET 0xF86A64 513 514 #define mmTPC6_CFG_QM_TENSOR_1_DIM_1_SIZE 0xF86A68 515 516 #define mmTPC6_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xF86A6C 517 518 #define mmTPC6_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET 0xF86A70 519 520 #define mmTPC6_CFG_QM_TENSOR_1_DIM_2_SIZE 0xF86A74 521 522 #define mmTPC6_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xF86A78 523 524 #define mmTPC6_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET 0xF86A7C 525 526 #define mmTPC6_CFG_QM_TENSOR_1_DIM_3_SIZE 0xF86A80 527 528 #define mmTPC6_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xF86A84 529 530 #define mmTPC6_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET 0xF86A88 531 532 #define mmTPC6_CFG_QM_TENSOR_1_DIM_4_SIZE 0xF86A8C 533 534 #define mmTPC6_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xF86A90 535 536 #define mmTPC6_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET 0xF86A94 537 538 #define mmTPC6_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xF86A98 539 540 #define mmTPC6_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xF86A9C 541 542 #define mmTPC6_CFG_QM_TENSOR_2_PADDING_VALUE 0xF86AA0 543 544 #define mmTPC6_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xF86AA4 545 546 #define mmTPC6_CFG_QM_TENSOR_2_DIM_0_SIZE 0xF86AA8 547 548 #define mmTPC6_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xF86AAC 549 550 #define mmTPC6_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET 0xF86AB0 551 552 #define mmTPC6_CFG_QM_TENSOR_2_DIM_1_SIZE 0xF86AB4 553 554 #define mmTPC6_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xF86AB8 555 556 #define mmTPC6_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET 0xF86ABC 557 558 #define mmTPC6_CFG_QM_TENSOR_2_DIM_2_SIZE 0xF86AC0 559 560 #define mmTPC6_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xF86AC4 561 562 #define mmTPC6_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET 0xF86AC8 563 564 #define mmTPC6_CFG_QM_TENSOR_2_DIM_3_SIZE 0xF86ACC 565 566 #define mmTPC6_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xF86AD0 567 568 #define mmTPC6_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET 0xF86AD4 569 570 #define mmTPC6_CFG_QM_TENSOR_2_DIM_4_SIZE 0xF86AD8 571 572 #define mmTPC6_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xF86ADC 573 574 #define mmTPC6_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET 0xF86AE0 575 576 #define mmTPC6_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xF86AE4 577 578 #define mmTPC6_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xF86AE8 579 580 #define mmTPC6_CFG_QM_TENSOR_3_PADDING_VALUE 0xF86AEC 581 582 #define mmTPC6_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xF86AF0 583 584 #define mmTPC6_CFG_QM_TENSOR_3_DIM_0_SIZE 0xF86AF4 585 586 #define mmTPC6_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xF86AF8 587 588 #define mmTPC6_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET 0xF86AFC 589 590 #define mmTPC6_CFG_QM_TENSOR_3_DIM_1_SIZE 0xF86B00 591 592 #define mmTPC6_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xF86B04 593 594 #define mmTPC6_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET 0xF86B08 595 596 #define mmTPC6_CFG_QM_TENSOR_3_DIM_2_SIZE 0xF86B0C 597 598 #define mmTPC6_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xF86B10 599 600 #define mmTPC6_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET 0xF86B14 601 602 #define mmTPC6_CFG_QM_TENSOR_3_DIM_3_SIZE 0xF86B18 603 604 #define mmTPC6_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xF86B1C 605 606 #define mmTPC6_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET 0xF86B20 607 608 #define mmTPC6_CFG_QM_TENSOR_3_DIM_4_SIZE 0xF86B24 609 610 #define mmTPC6_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xF86B28 611 612 #define mmTPC6_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET 0xF86B2C 613 614 #define mmTPC6_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xF86B30 615 616 #define mmTPC6_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xF86B34 617 618 #define mmTPC6_CFG_QM_TENSOR_4_PADDING_VALUE 0xF86B38 619 620 #define mmTPC6_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xF86B3C 621 622 #define mmTPC6_CFG_QM_TENSOR_4_DIM_0_SIZE 0xF86B40 623 624 #define mmTPC6_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xF86B44 625 626 #define mmTPC6_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET 0xF86B48 627 628 #define mmTPC6_CFG_QM_TENSOR_4_DIM_1_SIZE 0xF86B4C 629 630 #define mmTPC6_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xF86B50 631 632 #define mmTPC6_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET 0xF86B54 633 634 #define mmTPC6_CFG_QM_TENSOR_4_DIM_2_SIZE 0xF86B58 635 636 #define mmTPC6_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xF86B5C 637 638 #define mmTPC6_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET 0xF86B60 639 640 #define mmTPC6_CFG_QM_TENSOR_4_DIM_3_SIZE 0xF86B64 641 642 #define mmTPC6_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xF86B68 643 644 #define mmTPC6_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET 0xF86B6C 645 646 #define mmTPC6_CFG_QM_TENSOR_4_DIM_4_SIZE 0xF86B70 647 648 #define mmTPC6_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xF86B74 649 650 #define mmTPC6_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET 0xF86B78 651 652 #define mmTPC6_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xF86B7C 653 654 #define mmTPC6_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xF86B80 655 656 #define mmTPC6_CFG_QM_TENSOR_5_PADDING_VALUE 0xF86B84 657 658 #define mmTPC6_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xF86B88 659 660 #define mmTPC6_CFG_QM_TENSOR_5_DIM_0_SIZE 0xF86B8C 661 662 #define mmTPC6_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xF86B90 663 664 #define mmTPC6_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET 0xF86B94 665 666 #define mmTPC6_CFG_QM_TENSOR_5_DIM_1_SIZE 0xF86B98 667 668 #define mmTPC6_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xF86B9C 669 670 #define mmTPC6_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET 0xF86BA0 671 672 #define mmTPC6_CFG_QM_TENSOR_5_DIM_2_SIZE 0xF86BA4 673 674 #define mmTPC6_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xF86BA8 675 676 #define mmTPC6_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET 0xF86BAC 677 678 #define mmTPC6_CFG_QM_TENSOR_5_DIM_3_SIZE 0xF86BB0 679 680 #define mmTPC6_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xF86BB4 681 682 #define mmTPC6_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET 0xF86BB8 683 684 #define mmTPC6_CFG_QM_TENSOR_5_DIM_4_SIZE 0xF86BBC 685 686 #define mmTPC6_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xF86BC0 687 688 #define mmTPC6_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET 0xF86BC4 689 690 #define mmTPC6_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xF86BC8 691 692 #define mmTPC6_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xF86BCC 693 694 #define mmTPC6_CFG_QM_TENSOR_6_PADDING_VALUE 0xF86BD0 695 696 #define mmTPC6_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xF86BD4 697 698 #define mmTPC6_CFG_QM_TENSOR_6_DIM_0_SIZE 0xF86BD8 699 700 #define mmTPC6_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xF86BDC 701 702 #define mmTPC6_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET 0xF86BE0 703 704 #define mmTPC6_CFG_QM_TENSOR_6_DIM_1_SIZE 0xF86BE4 705 706 #define mmTPC6_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xF86BE8 707 708 #define mmTPC6_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET 0xF86BEC 709 710 #define mmTPC6_CFG_QM_TENSOR_6_DIM_2_SIZE 0xF86BF0 711 712 #define mmTPC6_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xF86BF4 713 714 #define mmTPC6_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET 0xF86BF8 715 716 #define mmTPC6_CFG_QM_TENSOR_6_DIM_3_SIZE 0xF86BFC 717 718 #define mmTPC6_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xF86C00 719 720 #define mmTPC6_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET 0xF86C04 721 722 #define mmTPC6_CFG_QM_TENSOR_6_DIM_4_SIZE 0xF86C08 723 724 #define mmTPC6_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xF86C0C 725 726 #define mmTPC6_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET 0xF86C10 727 728 #define mmTPC6_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xF86C14 729 730 #define mmTPC6_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xF86C18 731 732 #define mmTPC6_CFG_QM_TENSOR_7_PADDING_VALUE 0xF86C1C 733 734 #define mmTPC6_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xF86C20 735 736 #define mmTPC6_CFG_QM_TENSOR_7_DIM_0_SIZE 0xF86C24 737 738 #define mmTPC6_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xF86C28 739 740 #define mmTPC6_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET 0xF86C2C 741 742 #define mmTPC6_CFG_QM_TENSOR_7_DIM_1_SIZE 0xF86C30 743 744 #define mmTPC6_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xF86C34 745 746 #define mmTPC6_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET 0xF86C38 747 748 #define mmTPC6_CFG_QM_TENSOR_7_DIM_2_SIZE 0xF86C3C 749 750 #define mmTPC6_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xF86C40 751 752 #define mmTPC6_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET 0xF86C44 753 754 #define mmTPC6_CFG_QM_TENSOR_7_DIM_3_SIZE 0xF86C48 755 756 #define mmTPC6_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xF86C4C 757 758 #define mmTPC6_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET 0xF86C50 759 760 #define mmTPC6_CFG_QM_TENSOR_7_DIM_4_SIZE 0xF86C54 761 762 #define mmTPC6_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xF86C58 763 764 #define mmTPC6_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET 0xF86C5C 765 766 #define mmTPC6_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xF86C60 767 768 #define mmTPC6_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xF86C64 769 770 #define mmTPC6_CFG_QM_TID_BASE_DIM_0 0xF86C68 771 772 #define mmTPC6_CFG_QM_TID_SIZE_DIM_0 0xF86C6C 773 774 #define mmTPC6_CFG_QM_TID_BASE_DIM_1 0xF86C70 775 776 #define mmTPC6_CFG_QM_TID_SIZE_DIM_1 0xF86C74 777 778 #define mmTPC6_CFG_QM_TID_BASE_DIM_2 0xF86C78 779 780 #define mmTPC6_CFG_QM_TID_SIZE_DIM_2 0xF86C7C 781 782 #define mmTPC6_CFG_QM_TID_BASE_DIM_3 0xF86C80 783 784 #define mmTPC6_CFG_QM_TID_SIZE_DIM_3 0xF86C84 785 786 #define mmTPC6_CFG_QM_TID_BASE_DIM_4 0xF86C88 787 788 #define mmTPC6_CFG_QM_TID_SIZE_DIM_4 0xF86C8C 789 790 #define mmTPC6_CFG_QM_SRF_0 0xF86C90 791 792 #define mmTPC6_CFG_QM_SRF_1 0xF86C94 793 794 #define mmTPC6_CFG_QM_SRF_2 0xF86C98 795 796 #define mmTPC6_CFG_QM_SRF_3 0xF86C9C 797 798 #define mmTPC6_CFG_QM_SRF_4 0xF86CA0 799 800 #define mmTPC6_CFG_QM_SRF_5 0xF86CA4 801 802 #define mmTPC6_CFG_QM_SRF_6 0xF86CA8 803 804 #define mmTPC6_CFG_QM_SRF_7 0xF86CAC 805 806 #define mmTPC6_CFG_QM_SRF_8 0xF86CB0 807 808 #define mmTPC6_CFG_QM_SRF_9 0xF86CB4 809 810 #define mmTPC6_CFG_QM_SRF_10 0xF86CB8 811 812 #define mmTPC6_CFG_QM_SRF_11 0xF86CBC 813 814 #define mmTPC6_CFG_QM_SRF_12 0xF86CC0 815 816 #define mmTPC6_CFG_QM_SRF_13 0xF86CC4 817 818 #define mmTPC6_CFG_QM_SRF_14 0xF86CC8 819 820 #define mmTPC6_CFG_QM_SRF_15 0xF86CCC 821 822 #define mmTPC6_CFG_QM_SRF_16 0xF86CD0 823 824 #define mmTPC6_CFG_QM_SRF_17 0xF86CD4 825 826 #define mmTPC6_CFG_QM_SRF_18 0xF86CD8 827 828 #define mmTPC6_CFG_QM_SRF_19 0xF86CDC 829 830 #define mmTPC6_CFG_QM_SRF_20 0xF86CE0 831 832 #define mmTPC6_CFG_QM_SRF_21 0xF86CE4 833 834 #define mmTPC6_CFG_QM_SRF_22 0xF86CE8 835 836 #define mmTPC6_CFG_QM_SRF_23 0xF86CEC 837 838 #define mmTPC6_CFG_QM_SRF_24 0xF86CF0 839 840 #define mmTPC6_CFG_QM_SRF_25 0xF86CF4 841 842 #define mmTPC6_CFG_QM_SRF_26 0xF86CF8 843 844 #define mmTPC6_CFG_QM_SRF_27 0xF86CFC 845 846 #define mmTPC6_CFG_QM_SRF_28 0xF86D00 847 848 #define mmTPC6_CFG_QM_SRF_29 0xF86D04 849 850 #define mmTPC6_CFG_QM_SRF_30 0xF86D08 851 852 #define mmTPC6_CFG_QM_SRF_31 0xF86D0C 853 854 #define mmTPC6_CFG_QM_KERNEL_CONFIG 0xF86D10 855 856 #define mmTPC6_CFG_QM_SYNC_OBJECT_MESSAGE 0xF86D14 857 858 #define mmTPC6_CFG_ARUSER 0xF86D18 859 860 #define mmTPC6_CFG_AWUSER 0xF86D1C 861 862 #define mmTPC6_CFG_FUNC_MBIST_CNTRL 0xF86E00 863 864 #define mmTPC6_CFG_FUNC_MBIST_PAT 0xF86E04 865 866 #define mmTPC6_CFG_FUNC_MBIST_MEM_0 0xF86E08 867 868 #define mmTPC6_CFG_FUNC_MBIST_MEM_1 0xF86E0C 869 870 #define mmTPC6_CFG_FUNC_MBIST_MEM_2 0xF86E10 871 872 #define mmTPC6_CFG_FUNC_MBIST_MEM_3 0xF86E14 873 874 #define mmTPC6_CFG_FUNC_MBIST_MEM_4 0xF86E18 875 876 #define mmTPC6_CFG_FUNC_MBIST_MEM_5 0xF86E1C 877 878 #define mmTPC6_CFG_FUNC_MBIST_MEM_6 0xF86E20 879 880 #define mmTPC6_CFG_FUNC_MBIST_MEM_7 0xF86E24 881 882 #define mmTPC6_CFG_FUNC_MBIST_MEM_8 0xF86E28 883 884 #define mmTPC6_CFG_FUNC_MBIST_MEM_9 0xF86E2C 885 886 #endif /* ASIC_REG_TPC6_CFG_REGS_H_ */ 887