Searched refs:mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL (Results 1 – 16 of 16) sorted by relevance
| /linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/sdma0/ |
| D | sdma0_4_1_offset.h | 78 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL … macro
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| D | sdma0_4_0_offset.h | 80 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 macro
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| D | sdma0_4_2_2_offset.h | 80 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL … macro
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| D | sdma0_4_2_offset.h | 80 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL … macro
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| /linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/oss/ |
| D | oss_2_4_d.h | 165 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x3409 macro
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| D | oss_3_0_1_d.h | 162 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x3409 macro
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| D | oss_2_0_d.h | 228 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x3409 macro
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| D | oss_3_0_d.h | 299 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x3409 macro
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| /linux-5.19.10/drivers/gpu/drm/amd/amdgpu/ |
| D | sdma_v2_4.c | 435 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); in sdma_v2_4_gfx_resume()
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| D | cik_sdma.c | 459 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); in cik_sdma_gfx_resume()
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| D | sdma_v3_0.c | 673 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); in sdma_v3_0_gfx_resume()
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| D | sdma_v5_2.c | 625 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); in sdma_v5_2_gfx_resume()
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| D | sdma_v5_0.c | 724 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); in sdma_v5_0_gfx_resume()
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| D | sdma_v4_0.c | 1496 WREG32_SDMA(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL, 0); in sdma_v4_0_start()
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| /linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| D | gc_10_1_0_offset.h | 55 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL … macro
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| D | gc_10_3_0_offset.h | 60 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL … macro
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