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Searched refs:mmSDMA0_POWER_CNTL (Results 1 – 15 of 15) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/amdgpu/
Dcik_sdma.c913 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); in cik_enable_sdma_mgls()
916 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
918 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); in cik_enable_sdma_mgls()
921 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
923 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); in cik_enable_sdma_mgls()
926 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
928 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); in cik_enable_sdma_mgls()
931 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
Dsdma_v4_0.c96 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000),
142 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051),
288 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003fff07, 0x40000051),
1365 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); in sdma_v4_1_init_power_gating()
1368 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); in sdma_v4_1_init_power_gating()
1377 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); in sdma_v4_1_init_power_gating()
1384 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); in sdma_v4_1_init_power_gating()
2319 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL); in sdma_v4_0_update_medium_grain_light_sleep()
2322 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data); in sdma_v4_0_update_medium_grain_light_sleep()
2327 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL); in sdma_v4_0_update_medium_grain_light_sleep()
[all …]
Dsdma_v3_0.c151 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
171 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
1490 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); in sdma_v3_0_update_sdma_medium_grain_light_sleep()
1494 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); in sdma_v3_0_update_sdma_medium_grain_light_sleep()
1498 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); in sdma_v3_0_update_sdma_medium_grain_light_sleep()
1502 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); in sdma_v3_0_update_sdma_medium_grain_light_sleep()
1550 data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[0]); in sdma_v3_0_get_clockgating_state()
Dsdma_v5_2.c1697 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); in sdma_v5_2_update_medium_grain_light_sleep()
1700 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); in sdma_v5_2_update_medium_grain_light_sleep()
1704 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); in sdma_v5_2_update_medium_grain_light_sleep()
1707 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); in sdma_v5_2_update_medium_grain_light_sleep()
1761 data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL)); in sdma_v5_2_get_clockgating_state()
Dsdma_v5_0.c1704 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); in sdma_v5_0_update_medium_grain_light_sleep()
1707 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); in sdma_v5_0_update_medium_grain_light_sleep()
1711 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); in sdma_v5_0_update_medium_grain_light_sleep()
1714 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); in sdma_v5_0_update_medium_grain_light_sleep()
1764 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL)); in sdma_v5_0_get_clockgating_state()
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/sdma0/
Dsdma0_4_1_offset.h64 #define mmSDMA0_POWER_CNTL … macro
Dsdma0_4_0_offset.h66 #define mmSDMA0_POWER_CNTL 0x001a macro
Dsdma0_4_2_2_offset.h66 #define mmSDMA0_POWER_CNTL … macro
Dsdma0_4_2_offset.h66 #define mmSDMA0_POWER_CNTL … macro
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_4_d.h159 #define mmSDMA0_POWER_CNTL 0x3402 macro
Doss_3_0_1_d.h156 #define mmSDMA0_POWER_CNTL 0x3402 macro
Doss_2_0_d.h221 #define mmSDMA0_POWER_CNTL 0x3402 macro
Doss_3_0_d.h293 #define mmSDMA0_POWER_CNTL 0x3402 macro
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_10_1_0_offset.h41 #define mmSDMA0_POWER_CNTL … macro
Dgc_10_3_0_offset.h46 #define mmSDMA0_POWER_CNTL … macro