Searched refs:mmSDMA0_PHASE1_QUANTUM (Results 1 – 15 of 15) sorted by relevance
| /linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/sdma0/ |
| D | sdma0_4_1_offset.h | 102 #define mmSDMA0_PHASE1_QUANTUM … macro
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| D | sdma0_4_0_offset.h | 104 #define mmSDMA0_PHASE1_QUANTUM 0x002d macro
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| D | sdma0_4_2_2_offset.h | 104 #define mmSDMA0_PHASE1_QUANTUM … macro
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| D | sdma0_4_2_offset.h | 104 #define mmSDMA0_PHASE1_QUANTUM … macro
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| /linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/oss/ |
| D | oss_2_4_d.h | 177 #define mmSDMA0_PHASE1_QUANTUM 0x3415 macro
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| D | oss_3_0_1_d.h | 175 #define mmSDMA0_PHASE1_QUANTUM 0x3415 macro
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| D | oss_2_0_d.h | 240 #define mmSDMA0_PHASE1_QUANTUM 0x3415 macro
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| D | oss_3_0_d.h | 312 #define mmSDMA0_PHASE1_QUANTUM 0x3415 macro
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| /linux-5.19.10/drivers/gpu/drm/amd/amdgpu/ |
| D | cik_sdma.c | 386 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i], in cik_ctx_switch_enable()
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| D | sdma_v3_0.c | 597 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i], in sdma_v3_0_ctx_switch_enable()
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| D | sdma_v5_2.c | 558 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), in sdma_v5_2_ctx_switch_enable()
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| D | sdma_v5_0.c | 661 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), in sdma_v5_0_ctx_switch_enable()
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| D | sdma_v4_0.c | 1101 WREG32_SDMA(i, mmSDMA0_PHASE1_QUANTUM, phase_quantum); in sdma_v4_0_ctx_switch_enable()
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| /linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| D | gc_10_1_0_offset.h | 79 #define mmSDMA0_PHASE1_QUANTUM … macro
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| D | gc_10_3_0_offset.h | 84 #define mmSDMA0_PHASE1_QUANTUM … macro
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