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Searched refs:mmSDMA0_GFX_RB_WPTR_POLL_CNTL (Results 1 – 14 of 14) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/amdgpu/
Dsdma_v5_0.c69 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
95 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
750 mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); in sdma_v5_0_gfx_resume()
754 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), in sdma_v5_0_gfx_resume()
980 mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); in sdma_v5_0_mqd_init()
Dsdma_v4_0.c93 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
141 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
162 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
287 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
1230 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL); in sdma_v4_0_gfx_resume()
1234 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl); in sdma_v4_0_gfx_resume()
Dsdma_v5_2.c651 mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); in sdma_v5_2_gfx_resume()
655 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), in sdma_v5_2_gfx_resume()
924 mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); in sdma_v5_2_mqd_init()
Dsdma_v3_0.c722 wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]); in sdma_v3_0_gfx_resume()
734 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl); in sdma_v3_0_gfx_resume()
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/sdma0/
Dsdma0_4_1_offset.h218 #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL … macro
Dsdma0_4_0_offset.h222 #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x0087 macro
Dsdma0_4_2_2_offset.h222 #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL … macro
Dsdma0_4_2_offset.h218 #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL … macro
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_4_d.h192 #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x3485 macro
Doss_3_0_1_d.h219 #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x3485 macro
Doss_2_0_d.h251 #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x3485 macro
Doss_3_0_d.h344 #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x3485 macro
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_10_1_0_offset.h216 #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL … macro
Dgc_10_3_0_offset.h202 #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL … macro